10/31/2020 VLSI Physical Design: Physical Design Interview Question Part 1

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Saturday, 20 February 2016

Physical Design Interview Question Part 1

1. Explain concept of cross talk?

2. How can you overcome cross talk problem?
3. what is shielding? how it avoid avoids crosstalk problem?
4. how spacing h reducing crosstalk noise?
5. Why double spacing and multiple vias are used related to clock?
6. where do you insert buffer to avoid crosstalk? how buffer insertion solve the problem?
7. Difference between Chip Design and Block level design?
8. What are the ways to place macros in a full chip design?
9. what are the differences between Hierarchical Design and flat design?
10. Why 500 MHz clock design is complex than 48Mhz design?
11. What all tools used in physical verification?
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12. what are the inputs you will give in physical verification
13. how will you solve the congestion between two macros?
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14. what all parameters you will consider while estimating die size?
15. What is each macro size and number of standard cell count?
16. Depends on your design. Email *
17. What are the input needs for your design?
18. What does SDC (Synopsys design contraint) file contains?
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19. how will give Clock definitions ?
20. what are timing Timing exception, how will you constraint them?
21. what is Input and Output delays, what are prime time commands for it?
22. How did you do power planning?
23. Explain, how will you find number of power pad and IO power pads?
24. How the number of power straps calculate? Send

25. How to find total power of chip, What are the problems you can faced with respect to timing?
26. what is setup and hold problem, how will you solve it?
27. which is preferable layer for clock routing and why?
28. what do you mean by IR drop problem, how will you overcome by this problem?
29. what is antenna effect, how does it impact the and how would you resolve antennae effect
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problem?
30. How are the PVT conditions? Describe using graph? Search
31. Describe the physical design flow?
32. what all the and inputs and outputs for each step of physical design?
33. Translate
34. What is cell delay and net delay, how will you reduce this delays?
35. What are the different timing delay models available? Select Language ▼
36. What is wire load model (WLM)?
37. Why higher metal layers are preferred for power?
38. What do you mean by logic optimization techniques, how it will work?
39. what is slack, how will you calculate slack?
40. what are the parameters on which slack depends on?
41. What do you mean by of negative slack, how will u make it positive?
42. What is EM and it effects?

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10/31/2020 VLSI Physical Design: Physical Design Interview Question Part 1
43. What are types of routing ? Blog Archive
44. What do you mean by clock latency? what are the types of clock latecies?
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Physical Design interview Questions
Posted by Akshay at 21:26 With Answers P...
Physical Design Interview Question
Part 1
1 comment: Physical Design Interview Question
Part 2
STA Interview Questions Part 1
Anonymous 26 April 2016 at 18:54
STA Interview Questions Part 2
Tks very much for your post.
STA Interview Question Part 3

Avoid surprises — interviews need preparation. Some questions come up time and time Physical Design Interview Question
again — usually about you, your experience and the job itself. We've gathered together the Part 3

most common questions so you can get your preparation off to a flying start. Physical Design (Floorplanning)
interview Question...
You also find all interview questions at link at the end of this post. Physical Design (Power planning)
Interview Questio...
Source: Download Ebook: Ultimate Guide To Job Interview Questions Answers: Physical Design (VLSI) Interview
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