1/5/2021 Congestion in VLSI Physical Design FLow ~ VLSI Basics And Interview Questions

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Congestion in VLSI Physical

Design FLow
Physical Design
Congestion in VLSI Physical Design Flow Tutorials

Here let us discuss about congestion. What is Congestion?

What are the reasons for Congestion? How congestion can
be xed? Popular Posts

Physical Design (PD)

What is Congestion? Interview Questions -
If the number of routing tracks available for routing in one Floorplanning
particular area is less than the required routing tracks then     1.   What is oorplaning?
the area said to be congested. There will be a limit for    A.   Floor planing is the
number of nets that can be routed through particular area. process of placing
Blocks/Macros in the
chip/core area, thereby
determining ...

IR Drop Analysis
What is IR Drop Analysis?
How it effects the timing?
The power supply in the
chip is distributed
What are the reasons for Congestion? uniformly through metal
High Standard cell density in small area layers (Vdd a...
Placement of standard cells near macros
High pin density at the edge of macro
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1/5/2021 Congestion in VLSI Physical Design FLow ~ VLSI Basics And Interview Questions

Bad oorplan Congestion in

During IO optimization tool does buffering, So lot of cells VLSI Physical
placed in the core area Design FLow
How congestion can be Analysed? Congestion in
Congestion can be analysed by using congestion map as VLSI Physical Design Flow
shown below gure. Here let us discuss about
congestion. What is
Congestion? What are the
reasons for Congestion?
H...

Static Timing
Analysis (STA)
If the congestion is not too severe, The actual route can be Interview
detoured around congested area. The detoured nets will Questions
have worse RC delays than actual VR estimates.
Static Timing Analysis
If the congestion is too severe, the design can be un- Interview Questions Static
routable. This is really not good. It is important to Timing Analysis plays
minimize or eliminate the congestion before continuing. major role in physical
design(PD) ow. It checks
the design...

Clock Tree
Synthesis (CTS)
- Overview
Clock Tree

How to x Congestion? Synthesis Clock Tree

Rerun the fast placement with Congestion driven option Synthesis (CTS) is the

(Congestion driven placement) process of inserting

Modify physical constraints such as adjust cell density in buffers/inverters along the
clock paths of the ASIC
congested areas. Because higher cell density cause for
design to...
congestion. 
Use/Modify proper blockages. i.e., Soft blockages, Hard Blockages and Halos
blockages, Macro Padding are used proper locations to BLOCKAGES: Blockages are
minimize the congestion near macros. speci c locations where
Modify oorplaning such as moving macros, change core placing of cells are
shape/size, Move pins to give enough room for routing prevented or blocked. These
What happens during congestion driven placement?
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1/5/2021 Congestion in VLSI Physical Design FLow ~ VLSI Basics And Interview Questions

As discussed earlier, Congestion driven placement is act as guidelines for placing

performed to reduce the congestion. During congestion std cel...
driven placement, the cells (Higher cell density) which
IR Drop
caused for congestion are spread apart. If the cells along Analysis
timing critical paths are spread apart to minimize Interview
congestion, What happens?  Questions
IR Drop Analysis Interview
If the cells along timing critical paths spread apart, the Questions 1. What is IR
timing constraints along that particular paths are not met Drop Analysis?  A. The
which cause for timing violations. But these violations can power supply in the chip is
be xed during incremental optimization.  distributed uniformly
through met...
What are the care should be taken using congestion
Floorplan
driven option?
Control
If there is some congestion, use medium effort option
Parameters
If the congestion is bad, use high effort option
The following
If there is no congestion, Don't use congestion driven
are the Control Parameters
option. If we use congestion driven option in this case, It
during Floorplan 1. Aspect
takes more rum time for placement.
Ratio: Core Utilization
How modify physical constraints reduce congestion?
Aspect ratio (H/W)
As discussed earlier, Higher cell density can cause for Row/Core ratio 2.W...
congestion. By default the cell density can be upto 95%.
We can reduce the cell density at congested areas by using IR Drop Analysis using
Redhawk - Overview
coordinate option.
As shown in below gure, we can set cell density to a IR Drop Analysis using

exible number to reduce the congestion by using the Redhawk: Redhawk

performs several types of
command 
power analysis on a circuit.
set_congestion_options - max_util 0.6\
Static Voltage (IR) drop
                                        - coordinate {x1 y1 x2 y2}
with average c...

Here we set the maximum cell density  upto 60% and given Sanity Checks in Physical
the coordinates for the particular area. Design Flow
 Sanity Checks in Physical
Design Flow check_library
check_timing 
report_constraint 

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1/5/2021 Congestion in VLSI Physical Design FLow ~ VLSI Basics And Interview Questions

report_timing  report_qor
check_design c...

Blog archive
► 2016 (2)

▼ 2014 (5)

▼ April (2)

Tie Cells Insertion

Congestion in VLSI
Physical Design
How blockages and macro padding(Halos) reduce
FLow
congestion?
► March (1)
  By using blockages and halos, They prevent the tool
placing cells in that particular locations to give enough ► February (2)

space for routing near the macros. For more details, please ► 2013 (21)

refer Blockages halos post.

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be placed in this region which give more routing resources

to the signal routes.

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References:
Synopsys IC Compiler manual

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Related Posts: vlsi.projectguru

Basic Terminology in Physical Design

Design: A circuit that performs one or more logical +1
functions. Cell: An instance of a design or library
primitive within a design. Port: The input or output
of a design. Pin: The input or output of a cell. Net: A wire t…
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Congestion in VLSI Physical Design FLow
Congestion in VLSI Physical Design Flow Here let us
discuss about congestion. What is Congestion? What Search This Blog
are the reasons for Congestion? How congestion can
SEARCH
be xed? What is Congestion? If the number of routing tracks
av… Read More

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High Fanout Net Synthesis (HFNS)
High Fan-out Net Synthesis Before going to discuss Posts
about we have to know the basic terminology like
Comments
What is Fanout? What are High Fanout Nets (HFN)?

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Why we are going for High Fanout Net Synthesis (HFNS)? What is
fanout?… Read More

Tie Cells Insertion

Tie Cells Insertion Here I am going to discuss about
Tie Cells Insertion. Before going to know about Tie
Cells Insertion, We have to know what Tie Cells are. 
Tie Cells: Tie cells are special purpose standard cells … Read
More

Power Planning - Power Network Synthesis

(PNS)
Power Planning - Power Network Synthesis (PNS) In
ICC Design Planning ow, Power Network Synthesis
creates macro power rings, creates the power grid. PNS
automates power topology de nition, Calculations of the width
and n… Read More

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