Laboratory practice 1: Logic Gates

Canche Marcial Daniel Misael II. IMPLEMENTATION

Facultad de Ingeniería, UADY A. Design Propierties
Mérida, México
A14001846@alumnos.uady.mx First, we need select the FPGA, we select XC3S100E of
the family SpartanE3 and the language VHDL.
Abstract— B. VHDL Module
Now we need include a VHDL Module in the device and
Boolean Functions are very important to Digital Systems. In this
report we have a first contact with XIlinz program and how define the number of inputs and outputs, for this case, as we
design a FPGA with logic gates. need to check the correct function of the logic gates will be
two inputs and seven outputs.
I. INTRODUCTION In the VHD sheet, now, we need implement the logic gates
The Boolean algebra will apply in digital systems through as follows.
logic gates for manipulate the signals of input and output. And
the logic gates are codificated on FPGA's.
The software of Xilinz help us to design FPGA's and the
basic logical operators are AND, OR, NOT, NAND, XOR &
XNOR. With the basic logical operators, we can do a lot of
arrangements for manipulate the signals.

Figure 1 Implementation code vhd

C. Implementation Constraints File

Later we need define where are in the physical FPGA, for
this we help ourselves from the document
Basys2_100_250General.ucf and then, we write the code in
the UCF sheet as follows.

Figure 2Implementation code ucf

D. Schematic representation
The schematic representation of the design is available on
the synthesize and show us a representation of the pre-
optimized design.

III. SIMULATION
A. VHDL Test Bench
Figure 1 Logic Gates Truth Tables Then we star the simulation, for this we need to include a
source VHDL Test Bench and assign values to inputs, by
default some values are assigned with a certain period,
however we must eliminate them for this practice.
Values assigned for the inputs are:
x <= '0','1' after 100 ns;
y <= '0','1' after 50 ns, '0' after 100 ns, '1' after 150 ns;
B. ISIM Simulator
Last, we use the ISIM simulator to get the graphic of the
inputs and outputs in the time as follows.
V. ANALYSIS AND CONCLUSION
In the practice we use six LUTs, zero FlipFlops and nine
IOBs.
The practice helps to understand how use ISE Project to
design FPGA’s with the language of VHDL, this be the first
contact with this software and was very easy. In the other
side, this practice helps to understand how the Boolean
algebra work in the design de FPGA´s.
REFERENCES
[1] Ashenden, P. J. (2010). The designer's guide to VHDL. Morgan
Kaufmann.J.
[2] Mano, M. M. (1982). Logica Digital y Diseño. Pearson Educación.
[3] A. Castillo, M. López, “Manual de prácticas de Sistemas Digitales I”,
Facultad de Ingeniería, UADY, pp. 20–24, 2012.

Figure 3 Simulation

IV. RESULTS
The results of the simulation are presented in the table in
the four times in which the value of the inputs changes: 0ns,
50ns, 100ns and 150ns. In this way we can obtain the 4
possible combinations in the inputs, to compare them with the
truth tables of the logic gates.
As we see, the table be supported for the truth’s tables, so
the objective was reached, and we can conclude that the logic
gates worked
Table 1 Signals vs Time (Simulation)

Time
Signal
0 ns 50 ns 100 ns 150 ns
X 0 0 1 1

Y 0 1 0 1

And 0 0 0 1

Or 0 1 1 1

Not (X) 1 0 1 0

Nand 1 1 1 0

Nor 1 0 0 0

Xor 0 1 1 0

Xnor 1 0 0 1