PROC.
28th INTERNATIONAL CONFERENCE ON MICROELECTRONICS (MIEL 2012), NIŠ, SERBIA, 13-16 MAY, 2012
CMOS Positive Feedback Latch Structures for
Complementary Signal Edge Alignment
Miodrag Nikolić, Vladimir Milovanović and Horst Zimmermann
Abstract— This paper presents both fully complemen-
tary and symmetrical CMOS latch structures for com-
plementary signal edge alignment, derived from NOR
and NAND based CMOS latch implementations. Inher-
ent edge misalignment, e.g. such caused by a technology
imperfection or a design asymmetry, could decrease the
robustness of a CMOS realisation of the latch structure.
Therefore, latch topologies which employ positive feed-
back are introduced here in order to address this issue.
The latches were designed and compared in the sense
of the robustness by simulations using the TSMC 40nm
CMOS technology device models.
I. Introduction
Sequential logic circuits require storage of state infor-
mation, thereby differentiating themselves from combi-
national logic circuits whose output is only a combina-
tion of the current input values [1]. For the property
of the information storage the former class require a
widely-employed basic storage element. A latch is an
essential level-sensitive electronic component that has
two stable states and that can be used to store the state
information [1]. It is employed, for instance, in the
construction of an edge-triggered register, which con-
trary to level-sensitive latches, only samples the input
on a clock transition. As such, latches are indispensable
building blocks of digital electronic circuits. Although
they have a rather simple purpose to store logic infor-
mation, i.e. to memorise either a logic 1 or a 0, they
can be realised in a wide variety of static and dynamic
implementations [1]. The most often implementation
form is using a positive feedback or regeneration. In
such a case intentional connections between the out-
put and the input of a combinational circuit are made.
Memories based on the positive feedback are grouped
in the class of elements called multivibrator circuits [1],
with the bistable element being its most popular repre-
sentative. Additionally, monostable and astable circuits
are also frequently used [1].
Opposite to this application area, the latch can also
be employed as a building block in highly sensitive ana-
logue integrated circuits, where its aim is to align the
complementary signal edges at the output of a certain
block, e.g. of a comparator. Unlike open loop com-
parators which can achieve the required gain with the
Miodrag Nikolić, Vladimir Milovanović and Horst Zimmermann
are with the Institute of Electrodynamics, Microwave and Circuit
Engineering, Vienna University of Technology (Technische Uni-
versität Wien), Gußhausstraße 25/354, 1040 Vienna, Austria, E-
mail: miodrag.nikolic@tuwien.ac.at
978-1-4673-0238-8/12/$31.00 © 2012 IEEE
365
cascade of several low- to moderate-gain stages without
concern for stability in feedback [2], regenerative com-
parators achieve the required gain due to the positive
exponential rise function of a latch [3]. The positive
feedback of a latch is widely used in clocked regenera-
tive comparators to force a fast decision [4], for instance
in [5], [6]. Also, a latch-type sense amplifier in 1.5V
0.13µm CMOS for use in SRAMs is analysed in [7].
It is not for memory element realisations, but for
the latter category of the latch applications that
this paper addresses. A highlight of possible, and
(only) for this purpose suited, latch topologies is
given. Also, the implementation issues in ultra-deep
submicrometer (UDSM) complementary metal-oxide-
semiconductor (CMOS) technologies, i.e. in those
CMOS technologies with the minimum transistor chan-
nel length which is less than 0.1µm, are addressed. The
simulation results verify the proposed behaviour.
II. Operating Principles
The system which has pole(s) in the right complex
half plane has the positively increasing exponential re-
sponse (envelope). This is the case with the most simple
two-cross coupled inverter latch of Fig. 1a whose time
response on an initial condition at t = 0 reads [8]
vo2 (t) − vo1 (t) = et·gm /C · (vo2 (0) − vo1 (0)), (1)
where gm = gmN + gmP is the sum of transconduc-
tances of nMOS and pMOS transistors, and C repre-
sents the total capacitance seen at each latch output.
Fig. 2 shows the normalised time domain response of
the latch, where the positive power supply voltage VDD
was used as the voltage normalisation factor. There-
fore, for a given input signal difference the circuit dif-
ferential output will exponentially rise, because of the
positive feedback, until reaching (ideally) the positive
supply rail. As this initial difference is larger, rise time
is smaller, as could be observed from Fig. 2.
The common problem in fully differential digital sig-
nalling is the alignment of the complementary fall-time
and rise-time edges. The positive feedback latch is a
suitable circuit part to remedy some existing edge mis-
alignment if it can be cascaded to the electronic network
of the interest. For example, the edge misalignment
could be caused by a technology parameter and bias
variation or a simple design issue. If the misaligned in-
put differential signal is able to trigger the latch at the
Fig. 1. Three CMOS latches. (a) The most simple two cross-coupled inverters CMOS latch. (b) NOR based SR (set-reset) latch. (c)
NAND based SR latch.
1 both able to store and control the memory states as
0.8
(vo2 (t) − vo1 (t))/VDD
0.6
vo2 (0) − vo1 (0)
0.4
0.2
0 The NOR (or NAND) gate inputs which are not em-
0 1 2 3
Normalised time (tgm /C )
Fig. 2. Normalised time response to an initial condition of the
simple two cross-coupled inverters latch of Fig. 1a. The cal-
culated time response is governed by (1). It may be observed
that as the initial condition voltage is larger, the latch takes
less time t for its outputs to reach the supply rails. Time
in the figure plot was also normalised with the latch time
constant.
correct moment altogether and produce response that
pulls the differential potentials to rails as seen in Fig. 2,
this complementary edge imperfection will not be visi-
ble by the succeeding block (which is driven by the very
output of Fig. 2) thus eliminating this circuit flaw.
III. Structure Development
Although the cross-coupled inverter pair (Fig. 1a)
could store a binary variable in a stable way, additional
circuitry must be added to enable the control of mem-
ory states. Otherwise, in absence of any triggering, the
circuit remains in a single stable state. To address this
issue, the cross-coupled inverter pair circuit evolved into
two other topologies — NOR-based set-reset (SR) latch
(Fig. 1b), and NAND-based SR latch (Fig. 1c) [1] —
function of their inputs. These circuits are similar to
the cross-coupled inverter pair with NOR and NAND
gates replacing the inverters, in the first and the sec-
ond case, respectively. Hence, three of the four pos-
sible input combinations, with the exception of the so
called forbidden state, are both allowed and necessary
to accomplish the function of storing logical state in-
formation in the latches of Fig. 1b and Fig. 1c. The
forbidden state is determined by a different input com-
bination depending on the type of the latch realisation
and in that state the outputs are not complementary.
4 5
ployed in the feedback path are connected to the trigger
inputs of the latch circuit, denoted with S and R (or S
and R), whose purpose is to enforce the outputs Q and
Q to a desired state. Data is written by overpowering
the feedback loop using these inputs. In the case of the
NOR-based latch the forbidden state is defined by the
input combination S = 1, R = 1, while in the case of
the NAND-based latch with S = 0, R = 0.
On the basis of the last section elaboration on the
topic of the complementary signal edge alignment, it
follows that the latch with only two input signal com-
binations, the complementary ones, should be, indeed,
enough to fulfil this purpose. Also, it is desirable for
this latch architecture to be both fully complementary
and symmetrical. It should be noted that in such appli-
cations, the circuit is not intended to work as a memory
element, but rather to perform a function of providing
aligned complementary outputs for misaligned comple-
mentary inputs. In that sense, two latch structures
which are both fully complementary and symmetrical
could be derived from NOR and NAND based latches,
in one case eliminating the redundant transistors and
in the other case leaving them to configure the circuit,
as shown in Fig. 3 and Fig. 4, respectively. As well
366
Fig. 3. Complementary signal edge alignment CMOS latch whose
topology is derived from the set-reset (SR) latches of Fig. 1b
and Fig. 1c. Cross-coupled inverter latch core is composed
of complementary pairs N1 /P1 and N2 /P2 , while transistors
N3 /P3 and N4 /P4 form the input-output interface inverters.
as the NOR and NAND CMOS latches, the proposed
structures also consume no static power. Though simi-
lar, the two proposed latch structures turn out to have
a different robustness against transistor dimensions.
It could be observed that the topology of Fig. 4 is
just the supplemented Fig. 3 with the additional tran-
sistors N5 /P5 and N6 /P6 . The operating principle of
Fig. 3 is basically the same as the two cross-coupled
inverters of Fig. 1a, as the two inverters N3 /P3 and
N4 /P4 serve just as interface between the preceding
block and the latch itself, i.e. as the extra circuitry
needed to control the memory states in the latches of
Fig. 1b and Fig. 1c. These two inverters should fulfil
two opposite requirements. On the one hand, they have
to be strong enough (large transistor widths) as to be
able to pull the latch out of one saturation state and
trigger its positive feedback that leads the output to
another rail and consequently positively saturates the
latch in another state. On the other hand, the two in-
verters should be also weak enough (small transistor
widths) as to escape from the case where their outputs
are firmly dictated by themselves because in this case
the cascaded cross-coupled inverter pair latch loses its
purpose. Hence, it is clear that there must exist a com-
promise between the two opposite requests. Of course,
this compromise can easily be found in a circuit sim-
ulator, but the achieved simulation accuracy depends
on the device models which are always tricky to use
and interpret in the cases where small signal variations
make large repercussions, what is certainly the case
in the positive feedback systems. Especially UDSM
CMOS technologies have pronounced large parameter
variations, so the implementation in such a technology
367
Fig. 4. Proposed complementary signal edge alignment latch
with the improved robustness with respect to the one of Fig.
3. Additional complementary transistor pairs N5 /P5 and
N6 /P6 are responsible for this robustness improvement, while
all other transistors have the same purpose as previously.
could be very critical in terms of the reliability and the
robustness.
The way to avoid this possible robustness issue is
in the addition of the two supplemental complemen-
tary pairs of transistors. Although they do not bring
some performance benefits with respect to the versions
without them, their contribution is in relaxation of the
alignment latch design criterion. The advantage of the
ratioed logic to reduce the number of transistors re-
quired to implement a given function, at the cost of the
reduced robustness and extra power dissipation may not
be always so advantageous. Hence, the drawback of a
reduction of the number of transistors over the latch
version shown in Fig. 2 is that transistor sizing be-
comes critical in ensuring proper functionality. This is
shown in the following analysis.
Consider the case where vo2 is low, vo1 is high and
a positive pulse is applied at vi1 . The following action
then takes place observing the circuit of Fig 4. As vi1
goes high P3 , P5 will switch off, and N3 , N5 will switch
on. This causes vo1 to go low. When vo1 and vi2 are
low, then N2 , N4 , N6 are off, and P2 , P4 , P6 on, which
causes vo2 to go high. This in turn supports on state of
N1 and off state of P1 , which means that vo1 will stay
low. On the other hand, behaviour of the circuit in Fig.

1
0 speed. For larger input voltage difference than applied
[V]
out
−1
V
0 0.05 0.1 0.15 0.2
Time [ns]
[V] ,
1 V. Conclusion
in
V
width of N /P and N /P
3 3 4 4
0
−1
0 0.05 0.1 0.15 0.2
Time [ns]
Fig. 5. Simulated step response of the alignment latches of Fig.
3 (upper subplot) and Fig. 4 (lower subplot) for the fixed
cross-coupled inverter sizes and multiple linearly increasing
interface inverter sizes (solid curves). Supply voltage was
1V while the input signal is denoted by the dashed line. it
may be observed that the robustness of the second latch is
improved with the respect to the first one as in all test cases
the latch does change its state.
3 is more complex, as during switching it forms a ra-
tioed inverter [1], so the function it performs strongly
depends on its sizing. Assuming the same initial condi-
tions, and applying the same pulse to the circuit of Fig.
3 ratioed, pseudo nMOS inverter N3 -P1 will be formed.
In order to make the latch switch, vo1 must be brought
below the switching threshold of the inverter N2 -P2 .
Once this is achieved, the positive feedback causes the
latch to invert states. This requirement forces an in-
crease of the sizes of transistors N3 , N4 , P3 , and P4 .
The boundary conditions on the transistor sizes can
be approximately analytically derived by equating the
currents in the inverter for vo1 equalling the inverter
threshold. By analogy, similar analysis holds for both
circuits in the opposite case, i.e. when vo2 is high, vo1
is low and a positive pulse is applied at vi2 .
IV. Simulation Results
The alignment latches of Fig. 3 and Fig. 4 were de-
signed using ultra-deep submicrometer CMOS technol-
ogy compact device models — TSMC 40nm CMOS pro-
cess. The step response simulation results for certain
fixed cross-coupled inverter transistor sizes and ten lin-
early increasing interface inverter sizes of the both latch
structures are given in Fig. 5 upper and lower subplot.
The nominal transistor width was W = 120nm, the
length was minimal for this technology L = 40nm, and
the power supply was VDD = 1V. It may be, indeed, ob-
served that for the lower interface inverter sizes of Fig.
3 the cross-coupled latch is not pulled-out of its positive
feedback saturation state, and hence triggering its feed-
back that leads it to another rail is not possible. This is
not the case with the proposed improved latch version
368
of Fig. 4 where for all identical interface inverter sizes
the latch state change is accomplished thanks to N5 /P5
and N6 /P6 , while the only difference is the transitions
in the simulations, the latch would take less time for its
outputs to reach the supply rails, as it is visible from
Fig. 1.
Quantitative analysis of the CMOS complementary
signal edge alignment latches was presented in this pa-
per. Two fully complementary and symmetrical latch
topologies, suitable for use as an output stage of a com-
parator, were derived from the NOR and NAND based
CMOS latch implementations. In such analogue ap-
plications they provide alignment of the complemen-
tary output signals of the previous stage as well as the
rail-to-rail output swing requiring no static power con-
sumption. However, the proposed structures differ in
the terms of the robustness, and it was shown that the
improved robustness implies the relaxation of the latch
design criterion.
Acknowledgment
The authors would like to thank Lantiq A GmbH,
Austria, for supporting the work presented in this pa-
per. Financial funding from the Austrian BMVIT via
FFG in the project xPLC is also appreciated.
References
[1] J. Rabaey, A. Chandrakasan, and B. Nikolić Digital Inte-
grated Circuits: A Design Perspective, 2nd ed. NJ, USA:
Prentice-Hall, 2003
[2] T. Sepke, J. K. Fiorenza, C. G. Sodini, P. Holloway, Hae-
Seung Lee, ’Comparator-based switched-capacitor circuits
for scaled CMOS technologies,’ ISSCC Dig. Tech. Papers,
San Francisco, CA, USA, Feb. 2006, pp. 812-821
[3] P. E. Allen and D. R. Holberg, CMOS Analog Circuit De-
sign, 2nd ed. New York City, NY / Oxford, UK: Oxford
University Press, 2002
[4] H. J. M. Veendrick, ’The Behavior of Flip-Flops Used as
Synchronizers and Prediction of Their Failure Rate,’ IEEE
Journal of Solid-State Circuits, Vol. 15, No. 2, pp. 169176,
1980
[5] B. Goll, H. Zimmermann, ’A 65nm CMOS comparator
with modified latch to achieve 7GHz/1.3mW at 1.2V and
700MHz/47W at 0.6V,’ ISSCC Dig. Tech. Papers, San Fran-
cisco, CA, USA, Feb. 2009, pp. 328-329, 329a
[6] B. Goll, H. Zimmermann, ’A Clocked, Regenerative Com-
parator in 0.12m CMOS with Tunable Sensitivity,’ European
Solid-State Circuits Conf., Munich, Germany, Sept., 2007,
pp. 408-411
[7] B. Wicht, T. Nirschl, and D. Schmitt-Landsiedel, ’Yield and
Speed Optimization of a Latch-Type Voltage Sense Ampli-
fier,’ IEEE Journal of Solid-State Circuits, vol. 39, pp. 1148-
1158, July, 2004
[8] B. J. McCarroll, and C. G. Sodini, and H.-S. Lee, ’A high-
speed CMOS comparator for use in an ADC,’ IEEE Journal
of Solid-State Circuits, vol. 23, no. 1, pp. 159-165, Feb 1988