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Cellular Nanoscale Network Cell with Memristors

for Local Implication Logic and Synapses


Mika Laiho, Eero Lehtonen
Microelectronics Laboratory, University of Turku
Joukahaisenkatu 3-5, 20014 Turku, Finland
Email: {mlaiho, elleht}@utu.fi

Abstract—This paper describes a cellular nanoscale network over existing SPICE models are highlighted. Then, using mem-
cell structure that is aimed to be built as a CMOS-nanomemristor ristors for performing material implication logic is reviewed.
hybrid. The processing cell uses memristors as ON-OFF pro- Finally, the structure of a CNN cell (CMOS/memristor hybrid)
grammable synapses, local logic and memory. Local logic is based
on memristor computations using material implication. Only 15 is described and simulation results are shown.
CMOS transistors per cell are used, independent of the size of
II. M EMRISTOR M ODEL WITH P ROGRAMMING
the neighborhood, since memristors are used as synapses. Also,
space-dependent templates (weight matrices) are possible at no T HRESHOLD
extra hardware cost. The operation of the cell is described and The memristor reported in [4] was programmed linearly by
simulation results are shown to illustrate the operation. passing charge through the device. However, the resistance of
the memristor reported in [6] exhibits a nonlinear dependence
I. I NTRODUCTION
on the voltage over the memristor. The latter device is of
Cellular architectures are usually seen to be well especial interest here because the nonlinearity allows a specific
suited for nanoscale technologies because of their regu- programming threshold [9], i.e., the devices can be operated
lar, locally connected network topology. The cellular neu- either in programming or readout mode depending on the volt-
ral/nonlinear/nanoscale network (CNN) theory [1] is a age over the device. Many memristor SPICE models without
paradigm that describes dynamics of processing cells based the programming threshold exist, e.g., [10]. In this paper a
on local interaction. The interaction between cells is pro- SPICE model introduced in [7], based on the experimental
grammable via weight matrices (templates) that can be pro- data and model of [6] is used. In the model of [7], the current
grammed on the fly allowing sequences of neighbor operations through the memristor is
to be run successively, while intermediate results can be stored
I = wn β sinh(αV ) + χ(exp(γV ) − 1). (1)
in local memories [2].
The memristor, invented by Chua in 1971 [3], is a nanoscale Here w is the state variable of the memristor [4] and the
resistive memory, the resistance (memristance) of which can constants α,β,χ and γ depend on the physical properties of
be programmed by passing charge through the device. In order the component. The time derivative of the state variable w is
for the memristance effect to be significant, the device has modeled as
dw
to be fabricated in nanoscale. While many groups have run = a · f (w) · V q , (2)
into the memristance effect in their experiments, HP Labs was dt
the first to identify their titanium oxide- based device as a where a is a constant, f : [0, 1] → R is a window function [4]
memristor [4].
f (w) = 1 − (2w − 1)2p (3)
The memristor can be constructed in a crossbar formation
allowing very dense programmable wiring fabrics. These are of where p is a positive integer. The state derivative depends
great interest in terms of building compact large neighborhood on the q’th power of V , making a proper programming
CNNs, especially since memristors can be processed on top threshold for large values of q. In the simulations of this
of CMOS circuits (CMOS/nanomemristor hybrids) [5]. The paper n was 4 and q was 13. A large q is needed in order to
memristor can be programmed to multiple resistive states [6], model the highly nonlinear dependency of the oxygen vacancy
and such a CNN was proposed [7], but programming the drift velocity on the applied voltage. More details of the
device into two states (ON, OFF state) can be done with much model and parameters can be found from [7]. Figure 1 shows
simpler hardware for controlling the programming. In [8] it Eldo simulations (Eldo is a commercial variant of SPICE) of
was shown that the ON-OFF programmability is sufficient for the memristor model. The top left subfigure shows voltage
performing CNN operations with binary inputs/outputs. over the memristor, the top right subfigure shows the current
In this paper, an ON-OFF programmable CNN with memris- through the memristor whereas the bottom left subfigure shows
tors acting as synapses, local logic and memory is studied. This the state variable w. It can be observed that small voltages
paper is organized so that first, a modified SPICE model of over the memristor do not affect w which demonstrates the
a memristor used in the simulations is described, and benefits existence of a proper programming threshold. The bottom
right subfigure shows the current-voltage characteristics of a programming is interrupted and m2 ends up in an intermediate
memristor showing a proper signature of a memristive device. state between ON/OFF states. In [11] it was assumed that pro-
It should be emphasized that, even thought the model is based gramming was instantaneous making the problem nonexistent.
on the experimental data of [6] it is not aiming to be an Here a keeper circuit, shown in Section IV, is used in parallel
accurate physical model (there is not enough data available to RO to guarantee a complete programming.
to do that); the model is aiming at reproducing the general
characteristics/behavior of a memristor. Also, it should be Vcond Vset
noted that here the state variable w is hard limited between
m1 m2
0.05 and 0.95. This avoids the problems in the extremes of w
described in [10].
m1 m2 m2 = m1 → m2
−6
RO
2 2
x 10 0 0 1
0 1 1
1
1
1 0 0
0
Imem

1 1 1
Vin

0
−1
−1
Figure 2. Implication logic with memristors.
−2

−2 −3
0 1 2 3 0 1 2 3
Time −7
x 10 Time −7
x 10 B. Multi-Input NOR Using Implication
−6
x 10
1
1
The implication operation of Figure 2 can be extended
0.8 to multiple memristors. This opens up a possibility to use
0.6 0 memristors as synapses of a CNN. Figure 3 shows how
Imem
w

0.4
multi-input, programmable NOR operation can be computed
−1
0.2
with memristors. Memristor m4 is first initialized into a
−2 nonconducting state. Then, the result of the implication gives
0
0 1 2 3 −2 −1 0 1 2
Time −7
x 10 Vin

m4 = [(m1 ∧ Vcond1 ) ∨ (m2 ∧ Vcond2 ) ∨ (m3 ∧ Vcond3 )] → m4 ,


Figure 1. Memristor characteristics simulated using SPICE model.
(4)
where the programming voltages Vcondx are local and are con-
III. U SE OF M EMRISTORS IN THE CNN C ELL trolled by the outputs of the neighborhood cells. These nodes
A. Implication Logic with Memristors are either driven to Vcond or left floating (high impedance),
corresponding to logic 1 and 0. It should be noted that a pro-
Material implication p → q is a type of logic that was in [11] grammable multi-input NOR is the key elementary operation
shown to be naturally suited for computing with memristors, needed in an ON-OFF programmable CNN.
assuming that a memristor has a programming threshold.
Figure 2 shows two memristors and a resistor arranged for Vcond1 Vcond2 Vcond3 Vset
performing the implication operation, and the corresponding
m1 m2 m3 m4
truth table. Numbers 0 and 1 in the table correspond to the
memristor being in OFF (nonconducting) and ON (conducting)
state, respectively. It is assumed that RO be much larger than RO
m1 or m2 in ON state and Vcond < Vset . The table shows
that only when memristor m1 is ON and m2 is OFF, the
result m2 = m1 → m2 will be OFF. In this case voltage Figure 3. Programmable multi-input NOR using memristors.
over m2 is Vset − Vcond which is designed to be below the
programming threshold of a memristor. It is well known that
IV. P ROCESSING C ELL
together with the false condition (⊥), implication forms a
functionally complete set H = {→, ⊥}. The processing cell shown in Figure 4 is constructed of
When it comes to practical realization, this simple circuit of the following blocks: neighborhood connections, work mem-
Figure 2 has a problem. Namely, assume that m1 is OFF, m2 ristors, keeper circuit and two sets of access circuits controlled
is OFF and voltages Vcond and Vset are applied as in Figure by row and column decoding signals. Also shown is a driver
2. In the beginning of the programming, voltage over m2 is circuit that drives the cell output Y to the neighborhood when
Vset −VRo ≈ Vset (VRO is very small). Therefore, m2 starts to activated by the RU N signal. Control signal AB can be used
become more conductive (state variable w increases). Because to separate the state node X from the output node Y . The
of this, current through m2 increases; this increases voltage cell is suitable for processing binary templates that do not use
over R0 (VRo ) and thus decreases voltage over m2 . Therefore, threshold logic.
neighbor connections
A. Programming of Neighborhood Connections
Figure 4 shows the structure of an ON-OFF programmable
CNN cell using memristors. The memristors used for neigh-
bor connections, are shown on the top (N, W, S, E and mW mS mE mS mSFB
self-feedback connections are drawn). These memristors are
connected between output node OU T , and state node X.
Memristors can be connected to the neighborhood in a floss- work memristors
bar arrangement [13], allowing nearly symmetric large neigh- VIMP1 VIMP2 VIMP3 VIMP4
borhoods. The templates are programmed so that similarly to
RUN
cross-bar memories: each cell has two sets of row and column m1 m2 m3 m4
decoding signals, namely R− ini,j , C− ini,j and R− outi,j , X
AB Y
C− outi,j . Control signal M ASK can be used to make the Vbias1 Vbias2
programming conditional on the state variable Y of the CNN MASK Y VSS
OUT

cell. Control voltages Vprog1 and Vprog2 define whether the VSS R_outi,j

memristors are turned ON or OFF. Here Vprog1 and Vprog2 R_ini,j KEEP

are programmed to either 0 or 2V. If both sets of decoding C_ini,j

signals and M ASK and are active, voltage over all the Vprog1
Vprog2 C_outi,j
neighbor connection memristors is Vprog1 − Vprog2 . This way, VSS
all neighborhood connections can be turned either ON or OFF keeper

simultaneously.
If weights are to be programmed individually, it has to Figure 4. Structure of an ON-OFF programmable CNN cell using memristors.
be done by conducting a procedure depicted in Figure 5.
Rin Cin
It shows how different activation patterns are produced with Rout Cout Weight N

input and output decoders so that the northern neighborhood


connections are turned ON. Six different patterns are needed
in this case, in order to avoid unwanted programming of
connections. All other template elements can be programmed
in a similar manner. It is easy to see that global programming
of space-dependent weights is possible by activating just one
cell as input and one cell as output at a time.
Figure 5. Programming pattern for northern neighborhood connection.
If the control signal M ASK is inactive, the voltage at node
Y affects the writing of template values: if Y is LO, Vprog1 is
not conveyed to node X, preventing the write operation. On
X LO unless one of the input memristors (work memristors
the other hand, if voltage at Y is HI, memristor programming
or neighbor memristors), is conducting. In the latter case the
is possible. This feature can be used to create transient mask:
node is in a HI potential. The keeper circuit is then activated
no incoming connections are programmed into the ON state
by setting control signal KEEP HI: the keeper keeps the
if Y is LO. In effect, the transient mask is a special case of
node LO if it was LO initially, otherwise it does not affect the
space dependent weights being determined by in-cell memory
voltage of X.
contents.
B. Work Memristors C. Simulation Results
Figure 4 also shows 4 work memristors that are used as Figure 6 shows a simulated processing sequence with the
memories and for computing implication operations in order cell structure proposed in this paper. The simulations were
to perform local logic. In [12] it was shown that any Boolean carried out for a single cell with Eldo using the SPICE model
operation can be computed with the work memristors, if three described in Section II of this paper and using 65nm CMOS
memristors are allocated for storing intermediate processing simulation parameters for the transistors. All transistors were
results. A very large local memory is possible because of the the same size (0.4um/0.28um), which is the minimum size for
compact memristor implementation. It should be noted that 2.5V transistors in the particular process. In the beginning of
the work memristors do not get programmed unintentionally the sequence all memristors were initialized in an intermediate
when weights are being programmed, because the implication state, the state variable w being 0.3. The upper subfigure shows
voltages VIMP 1 - VIMP 4 are normally kept in the middle of the voltages over memristors mSF B, m1 and m4 and after
the voltage range. applying a sequence of control signals. The corresponding
The circuit block labeled as keeper in Figure 4 shows the state variables of memristors mSF B, m1 and m4 are shown
keeper circuit. The keeper circuit is activated when performing in the lower subfigure.
implication or programmable NOR operation. It works so that The sequence proceeds so that first mSF B is reset (w
first the transistor controlled by Vbias1 (acts as RO ) pulls node is driven LO). After that, the w of mSF B is programmed
HI. This demonstrates that the programming to OFF and ON 2
VX−VOUT
states works. After that, memristor m4 is driven into ON 1
VX−VIMP1
state, followed by m1 being reset to OFF state. After that, 0 VY−VIMP4
NOR implication operation is performed. Before doing the −1
implication, control signal AB is taken LO so that there is no −2
connection between nodes X and Y . During the implication, 0 0.2 0.4
Time
0.6 0.8 1
−6

control signal RU N is HI, Y is HI because m4 is conducting x 10


1
and, thus, output node OU T is pulled HI. Furthermore, as wsfb
mSF B is conducting, X is pulled HI. At this point, the keeper wwm1

circuit is activated, but it has no effect on X. Therefore, m1 0.5 wwm4

remains in a nonconductive state as a result of the implication.


0
0 0.2 0.4 0.6 0.8 1
2 Time −6
VX−VOUT x 10
1
VX−VIMP1
Figure 7. Processing sequence: self-feedback memristor mSF B is pro-
0 VY−VIMP4
grammed nonconducting.
−1

−2
0 0.2 0.4 0.6 0.8 1
Time x 10
−6 thing is that the neighborhood can be increased without adding
1 CMOS transistors (but again template programming time is
wsfb increased). A major benefit is that only 15 CMOS transis-
wwm1
tors/cell are needed, making very dense arrays possible. Also,
0.5 wwm4
space-dependent templates are available for use. Therefore,
the proposed cell is suited for applications that require large
0
0 0.2 0.4 0.6 0.8 1
neighborhoods and/or space dependent templates but in which
Time x 10
−6
the templates do not need to be programmed very fast.
Figure 6. Processing sequence: self-feedback memristor mSF B is pro- ACKNOWLEDGMENTS
grammed conducting.
This work was funded by the Academy of Finland (131295),
Geta graduate school and Nokia Foundation.
Figure 7 shows the same simulation with the difference
that mSF B is left into OFF state. Therefore, state node X R EFERENCES
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