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Qucs-0.0.19S: A new open-source circuit simulator and its application for

hardware design

Conference Paper · May 2016

DOI: 10.1109/SIBCON.2016.7491696

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Mike Brinson Vadim Kuznetsov

London Metropolitan University, Holloway, London, Uk X-FAB Semiconductor Foundries
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Qucs-0.0.19S: a new open-source circuit simulator and its
application for hardware design

Vadim Kuznetsov 1 , ra3xdh@gmail.com

Mike Brinson 2 , mbrin72043@yahoo.co.uk

1
Bauman Moscow State Technical University, Kaluga branch
2
Centre for Communications Technology, London Metropolitan University, UK

May 13, 2016

1 / 13
About Qucs circuit simulator
Qucs is open-source cross-platform An example of microwave amplifier circuit simulation
free post-SPICE circuit simulator. with Qucs
Main features are:
New simulation kernel
Qucsator (SPICE
incompatible);
Advanced RF and microwave
circuits analysis:
S,Z,Y-matrix analysis,
impedance and SWR
analysis;
RF components: substrates,
transmission lines, RF
semiconductor devices.
Advanced postprocessor and Qucs development team: G.B. Torri (Project Leader,
visualization system for Nikhef); C. Girardi (Intel Corporation); M. Brin-
frequency domain analysis: son (London Metropolitan University); F. Salfelder
complex plane plots, Smith (Frankfurt University)
charts, Impedance chart;
Verilog-A support via ADMS

Qucs packages for three platforms (Linux, Windows, Mac) could be

downloaded from the official website: https://qucs.github.io/ 2 / 13
Qucs-0.0.19S — Qucs extension with SPICE support
Qucs-S is special Qucs version with
SPICE support by V. Kuznetsov An example of switching power circuit
and M. Brinson simulation with Qucs-S
Qucs-S supports Ngspice
www.ngspice.org and XYCE
https://xyce.sandia.gov/
backends;
Improved switching circuits
supports;
Simulation of large realistic
circuits with Ngspice backend
Full support of the SPICE
models provided by
components manufacturers
Full support of the standard
SPICE-3f5 simulation types
(.AC, .TRAN, .DISTO,
.NOISE, .FOUR )

Release candidate Qucs-0.0.19S-RC5 is available here:

https://github.com/ra3xdh/qucs/releases/tag/0.0.19S-rc5 3 / 13
Spice4qucs initiative tasks

Spice4qucs initative tasks:

Correct known weaknesses observed with the Qucs<—>Ngspice/Xyce interfacing schematic

current Qucs simulation engine qucsator .
Qucs Schematic
Provide Qucs users with a choice of simulator Component 1 Component N
selected from qucsator, ngspice and Xyce.
getQucsNetlist() ... getQucsNetlist()
Extend Qucs subcircuit, EDD, RFEDD and getSpiceNetlist() getSpiceNetlist()
Verilog-A device modelling capabilities.
Access to the additional simulation tools and
extra component and device models provided Qucsator Netlist Builder Ngspice Netlist Builder Xyce Netlist Builder

by ngspice and Xyce. Qucs GUI level

Mixed-mode analogue-digital circuit simulation

capability using Qucs/ngspice/XSPICE Simulation kernel level.
Execution outside Qucs Qucsator Engine Ngspice Engine Xyce Engine
simulation. or
Gnucap Engine
Qucs GUI level
Currently implemnted in Qucs-0.0.19:
Ngspice sim output Xyce sim output
Ngspice, Xyce (both serial and parallel) to Qucs data converter to Qucs data converter
support
Qucsator Ngspice Xyce
interface interface interface
Basic simulations support (.DC, .AC, .TRAN)
Advanced simulation support (.FOUR,
.DISTO, .NOISE, .HB) Qucs data visualization engine
Qucs GUI level
Semiconductor devices with full SPICE
definition
Spice4qucs online documentation available here:
Qucs equations, parametrization (.PARAM), https://qucs- help.readthedocs.org/en/spice4qucs/index.html
and Ngnutmeg scripts support
Custom Ngspice simulation technique — User
ngnutmeg simulation scripts support.

4 / 13
 Ngspice and Xyce simulation techniques: Legacy Qucs circuit simulated
with Ngspice and Xyce

Spice netlist Qucs data visualization system

Qucs schematic capture
* Qucs 0.0.19 /home/vvk/.qucs/BJT.sch Magnitude response and output
Pr1
.PARAM Rload={47k} voltage waveform of a BJT amplifier
R5 Q2N2222A_1 _net1 _net0 _net2
R=4.7k V1 + QMOD_Q2N2222A_1 AREA=1 TEMP=26.85 10
R3 out U=12 V .MODEL QMOD_Q2N2222A_1 npn (Is=8.11e-14 Nf=1
R=24 kOhm
+ Nr=1 Ikf=0.5 Ikr=0.225 Vaf=113 Var=24
in + Ise=1.06e-11 Ne=2 Isc=0 Nc=2 Bf=205 Br=4

BJT_ngspice:ac.k
+ Rbm=0 Irb=0 Rc=0.137 Re=0.343 Rb=1.37
Q2N2222A_1 C2 + Cje=2.95e-11 Vje=0.75 Mje=0.33 Cjc=1.52e-11
C=0.1 uF 5
+ Vjc=0.75 Mjc=0.33 Xcjc=1 Cjs=0 Vjs=0.75
R1
+ Mjs=0 Fc=0.5 Tf=3.97e-10 Xtf=0 Vtf=0 Itf=0
C1 R=2 kOhm
+ Tr=8.5e-08 Kf=0 Af=1 Ptf=0 Xtb=1.5 Xti=3
C=0.1 uF
V2 + Eg=1.11 Tnom=26.85 )
R2 Netlist biulder
U=200 mV R1 0 _net0 2K
R4 Ngspice/Xyce output parser 0
f=4 kHz R=470 Ohm R2 0 _net2 470
R=Rload 100 1e3 1e4 1e5 1e6 1e7
C1 in _net0 0.1U
R3 _net0 _net3 24K frequency
C2 _net1 out 0.1U
R5 _net1 _net3 4.7K 2
Equation
V2 in 0 DC 0 SIN(0 200M 4K 0 0) AC 200M
Eqn1 transient ac simulation dc simulation R4 0 out {RLOAD}

BJT_ngspice:tran.v(out)
BJT_ngspice:tran.v(in)
VPr1 _net4 _net3 DC 0 AC 0 1
Rload=47k simulation V1 _net4 0 DC 12
K=out.v/in.v
.control
Pwr=(out.Vt*out.Vt)/Rload 0
AC1 DC1 set filetype=ascii
TR1 Type=lin echo "" > spice4qucs.cir.noise
Type=lin Start=100 Hz let Rload=47k -1
Start=0 Stop=10 MHz TRAN 1e-06 0.001 0
Stop=1 ms Points=2000 let Pwr=(V(out)*V(out))/Rload
write BJT_tran.txt VPr1#branch v(in) v(out) Pwr -2
destroy all 0 2e-4 4e-4 6e-4 8e-4 1e-3
reset time
time
AC LIN 2000 100 10MEG
let K=V(out)/V(in) 2
write BJT_ac.txt VPr1#branch v(in) v(out) K
destroy all

BJT_xyce:ac.V(OUT)
reset

exit 1
.endc
.END

0
100 1e3 1e4 1e5 1e6 1e7
FREQUENCY
5 / 13
Ngspice and Xyce simulation techniques: Realistic circuits simulation with
Ngspice and Xyce

This example shows realistic circuit simulation technique with Ngspice. BJT
audio amplifier is simulated in both frequency and time domain.
C11
R16 C=33n
R=330

D814D_4 C3 R26
C=22n R13 R=68
C4 14
R=120
C=500u R31 R28
R=1k V3
KS139A_1 R11 R=2 KT818A_1 12
U=25
R=39
R1 R5
KT814B_1 10

audio_amp_ngspice:ac.v(out)
R=1k R=15k

audio_amp_xyce:ac.V(OUT)
KT814A_1

8
KT3102A_2
R19
R=120 6
KT3102A_1 R29
C9 R=120
C=68n R18
D2D212A_2 R=68 4
R20
in
C6 C10 R=0.39
C=500u R9 R34 C=33n 2
R3 R4 R=10k R=10
R=1k R=27k out
R7 R8 0
R=68 R=1k 1 10 100 1e3 1e4 1e5 1e6
C8 R32
D2D212A_1 frequency
C=10u R23 R=8
C13
V1 R=0.39 FREQUENCY
C=1000p R21
U=1 V C7 R=68
C1 C=500u R10 R33
C=1000p
R=10k R=15 15
KT3107A_2
R22
KT815A_1 R=120
R30 10
KT3107A_1 R=120

R12 KT815B_1
5

audio_amp_ngspice:tran.v(out)
R=39 R27
R24 R=2 KT819A_1
R14 R=1k
KS139A_2 R=120
C2 0
R2 C=22n
R=1k R6
R=15k R25
C5 R=68 -5
D814D_1 C=500u V2
U=25

-10
C12
R17 C=33n
R=330
-15

ac simulation dc simulation transient 0 1e-4 2e-4 3e-4 4e-4 5e-4 6e-4 7e-4 8e-4 9e-4 1e-3
simulation time
AC1 DC1
Type=lin
Start=1 Hz TR1
Stop=1 MHz Type=lin
Points=200 Start=0
Stop=1 ms

6 / 13
Compact modeling with Qucs and Ngspice/Xyce: XSPICE macromodels
usage
Embedding of SPICE-model in Qucs libraries is allowed since Qucs-0.0.19
Applications of this feature:
Direct simulation of SPICE-defined components
XSPICE macromodels usage
LM358 XSPICE macromodel usage example (noninverting amplifier)
LM358 XSPICE macromodel

.SUBCKT LM358 1 2 3 4 5
*
2 C1 11 12 5.544E-12
transient C2 6 7 20.00E-12
LM358_test_ngspice:tran.v(out)
LM358_test_ngspice:tran.v(in)
DC 5 53 DX
simulation DE 54 5 DX
DLP 90 91 DX
V2 0 DLN 92 90 DX
U=5 V TR1 DP 4 3 DX
Type=lin EGND 99 0 POLY(2) (3,0) (4,0) 0 .5 .5
Start=0 FB 7 99 POLY(5) VB VC VE VLP VLN 0 15.91E6
in Stop=1 ms -2 + -20E6 20E6 20E6 -20E6
Points=200 GA 6 0 11 12 125.7E-6
out 0 2e-4 4e-4 6e-4 8e-4 1e-3 GCM 0 6 10 99 7.067E-9
time IEE 3 10 DC 10.04E-6
V1 HLIM 90 0 VLIM 1K
U=1 V time
Q1 11 2 13 QX
f=5 kHz ac simulation Q2 12 1 14 QX
2 R2 6 9 100.0E3
OP1 AC1 RC1 4 11 7.957E3
LM358_test_ngspice:ac.v(out)

R1
Type=log RC2 4 12 7.957E3
R=10k
V3 Start=1 Hz RE1 13 10 2.773E3
U=5 V Stop=10 MHz RE2 14 10 2.773E3
R2 1 REE 10 99 19.92E6
R=10k Points=141
RO1 8 5 50
RO2 7 99 50
RP 3 4 30.31E3
0 VB 9 0 DC 0
VC 3 53 DC 2.100
1 10 100 1e3 1e4 1e5 1e6 1e7 VE 54 4 DC .6
frequency VLIM 7 8 DC 0
VLP 91 0 DC 40
VLN 0 92 DC 40
.MODEL DX D(IS=800.0E-18)
.MODEL QX PNP(IS=800.0E-18 BF=250)
.ENDS

7 / 13
XSPICE analog circuit blocks

XSPICE is SPICE 3 An overview of XSPICE blocks

extension targeted at
system-level circuit design. XSPICE
XSPICE XSPICE

XSPICE is available with + +

Ngspice backend.
- d/dt - A ∫
XSPICE allows to use a
number of predefined blocks
for system level design
XA_gain_SE1 XA_int_SE1
XA_id_dt_DE1 gain=1.0 gain=1.0
XSPICE block allows to use gain=1.0 in_offset=0.0 in_offset=0.0
out_offset=0.0
Qucs-S for control system out_lower_limit=-10.0
out_offset=0.0 out_lower_limit=-10
out_upper_limit=10
design simulation purposes out_upper_limit=10.0 limit_range=1e-6
limit_range=1e-6 out_ic=0.0
XSPICE blocks are available
with new Xanalogue.lib XSPICE XSPICE XSPICE
library
1 1

2 X 2
+

XA_mult_x21 XA_summer_x21
ig1=1.0 ig1=1.0 XA_hyst1
ig2=1.0 ig2=1.0 in_low=0.7
io1=0.0 io1=0.0 in_high=2.4
io2=0.0 io2=0.0 hyst=0.5
out_gain=1.0 out_gain=1.0 out_lower_limit=0.5
out_upper_limit=3.0
out_offset=0.0 out_offset=1.0
input_domain=0.01 8 / 13
Control system simulation with XSPICE and Qucs-S
PI-controller schematic
.MODEL
transient
simulation SpiceModel3
Line_1 =.MODEL int2 int(in_offset=0 gain=1
Line_2=+ out_lower_limit=-100 out_upper_limit=100 limit_range=1e-6 out_ic=0)
TR1
Type=lin
Start=0
Stop=10s PI-controller block

Object A_gain_SE3 out

in
A=obj_amp
A_gain_SE2
A=main_amp
A_Line 2=.model main_amp gain(gain=1)
Unity
step A_int_SE2
ADD2
source ADD1 A=int2
A =sum1
A =sum1
V1

A_int_SE1
A=int1

.MODEL
A_gain_SE1
SpiceModel2
A=FBamp
Line_1 =.MODEL int1 int(in_offset=0 gain=5
A_Line 2=.model FBamp gain(gain=-1)
Line_2=+ out_lower_limit=-100 out_upper_limit=100 limit_range=1e-6 out_ic=0)

PI-controller step response

1.5

1
Step response (V)

0.5

0 2 4 6 8 10
Time (s)
9 / 13
User simulation construction with Nutmeg scripting language

Nutmeg is embedded Z-parameter simulation constructed with

postprocessor scripting Nutmeg scripting
language for Ngspice R1 out R2
R=50 Ohm in R=50 Ohm
backend;
Ngspice
Nutmeg allows to construct L1
L=1.125mH
custom simulation
new simulation types such V1 C1 V2
CUSTOM1
as: scattering matrix and U=1 V C=450.2nF U=1 V
SpiceCode=* open port#2
alter V2 AC=0
impedance analysis, alter R2=100k
AC DEC 20 100 100k
Monte-Carlo analysis, etc. let K=V(out)/V(in)
let Z11=V(in)/V1#branch
1e4 1e4
let Z21=V(out)/V1#branch
write Z1121_data.txt Z11 Z21
* open port#1
1e3 alter V1 AC=0
1e3 alter V2 AC=1

ngspice/ac.z12
ngspice/ac.z21
alter R2=50
100 alter R1=100k
ngspice/ac.z22
ngspice/ac.z11

AC DEC 20 100 100k

let Z22=V(out)/V2#branch
100 let Z12=V(in)/V2#branch
10
write Z2212_data.txt Z22 Z12

1
10

0.1 3
100 1e3 1e4 1e5
Frequency (Hz)

10 / 13
Spectrum analysis with Nutmeg scripting
You can use nutmeg operator with ”Ngspice Custom simulation” to obtain the
output spectrum
.INCLUDE directive allows to attach the whole unchanged SPICE libraires to the
schematic using new SPICE-compatible devices symbols.
signal
J1
NJF
J=J2P307G
Content of jm.lib library file

* Library of JFET transistor model parameters

*
R5 out
* Copyright 1990 by CAD Department
R=50 Ohm * Release date: Apr '90
*
R6 .model JNT009 NJF(Vto=-1.925 Beta=4.184m Lambda=15.36m Rs=17 Rd=17
V3 R=500 + Cgs=4.5p Cgd=2.5p Fc=0.5 Pb=1 Is=10f)
U=1 mV *
f=7 MHz .model J2PS104g NJF(Vto=-1.562 Beta=816.3u Lambda=8.83m Rs=31 Rd=31
+ Cgs=3.2p Cgd=2.2p Fc=0.5 Pb=1 Is=10f)
*
J2 .model J2P303b NJF(Vto=-0.8137 Beta=2.015m Lambda=17.89m Rs=44 Rd=44
TRAN1 NJF TRAN2 + Cgs=4.2p Cgd=3.8p Fc=0.5 Pb=1 Is=10f)
J=J2P307G
L1=0.1m L1=0.1m *
L2=0.1m L2=0.1m .model J2P303e NJF(Vto=-4.125 Beta=782.5u Lambda=9.132m Rs=21 Rd=21
L3=0.1m L3=0.1m + Cgs=4.2p Cgd=3.8p Fc=0.5 Pb=1 Is=10f)
R4
K12=0.99 K12=0.99 *
R=10
K13=0.99 K13=0.99 .model J2P307b NJF(Vto=-2.617 Beta=1.578m Lambda=1.890m Rs=15 Rd=15
K23=0.99 K23=0.99
Ngspice + Cgs=3.5p Cgd=3p Fc=0.5 Pb=1 Is=10f)
Rp=1m Rp=1m *
Rs1=1m custom simulation Rs1=1m .model J2P307v NJF(Vto=-2.966 Beta=1.423m Lambda=7.299m Rs=18 Rd=18
Rs2=1m Rs2=1m + Cgs=3.5p Cgd=3p Fc=0.5 Pb=1 Is=10f)
V2
CUSTOM1 *
U=1.5 V
f=15 MHz SpiceCode= .model J2P307g NJF(Vto=-3.371 Beta=1.386m Lambda=3.532m Rs=16 Rd=16
tran 1n 10u 1u + Cgs=3.5p Cgd=3p Fc=0.5 Pb=1 Is=10f)
.INCLUDE
linearize v(out) *
fft V(out) *End of library file
SpiceInclude1
let S = db(v(out))
File=/home/vvk/SpiceModels//jm.lib

3e-4

frequency: 8e+06
2.5e-4
ngspice/ac.v(out): -8.73e-05-j3.03e-05

2e-4
ngspice/ac.v(out)

1.5e-4

1e-4

5e-5

0 5e6 1e7 1.5e7 2e7 2.5e7

frequency
3e7 3.5e7 4e7 4.5e7 5e7 11 / 13
User-defined devices

”SPICE generic device” component allows to construct user devices that

are already presented in simulation kernel, but not presented at the GUI
level.
”XSPICE generic device” component serves for construction of
user-defined A-devices. It’s need to define comma separated port list
(according allowed XSPICE devices ports) and attach .MODEL to this
component. User can attach precompiled XSPICE CodeModel libraries
and simulation-time compiled CodeModels.
Source code: cfunc.mod file
v0 v1 .MODEL
XSPICE void cm_ggain(ARGS)
{
SpiceModel1
Mif_Complex_t ac_gain;
Line_1 =.MODEL Amp1 ggain(gain=10 out_offset=0.01)
if(ANALYSIS != MIF_AC) {
A1
OUTPUT(out) = PARAM(out_offset)+PARAM(gain)*
PortList=v,v XSPICE CodeModel (INPUT(in)+PARAM(in_offset));
Model=Amp1
PARTIAL(out,in) = PARAM(gain);
XSP_CMod1 } else {
File=/home/vvk/projects/xspice_icm/cfunc.mod ac_gain.real = PARAM(gain);
File=/home/vvk/projects/xspice_icm/ifspec.ifs ac_gain.imag= 0.0;
AC_GAIN(out,in) = ac_gain;
}
}

12 / 13
Publications list

1 M. Brinson, and V. Kuznetsov, “A new approach to compact semiconductor

device modelling with Qucs Verilog-A analogue module synthesis,” in
International Journal of Numerical Modelling: Electronic Networks, Devices and
Fields, DOI:10.1002/jnm.2166, 2016
2 M. Brinson and V. Kuznetsov, “Qucs equation-defined and Verilog-A RF device
models for harmonic balance circuit simulation,” in Mixed Design of Integrated
Circuits Systems (MIXDES), 2015 22nd International Conference, June 2015, pp.
192–197.
3 V. Kuznetsov and L. Kechiev, “Charged board model ESD simulation for PCB
mounted MOS transistors,” Electromagnetic Compatibility, IEEE Transactions
on, vol. 57, no. 5, pp. 947–954, Oct 2015.
4 M. Brinson, R. Crozier, V. Kuznetsov, C. Novak, B. Roucaries, F. Schreuder, and
G. B. Torri. Qucs: An introduction to the new simulation and compact device
modelling features implemented in release 0.0.19/0.0.19Src2 of the popular GPL
circuit simulator. MOS-AK Workshop, Graz. http://www.mos-ak.org/graz_
2015/presentations/T_5_Brinson_MOS-AK_Graz_2015.pdf

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