122 Z^ß CHAPTER 2 OPERATIONAL AMPLIFIERS PROBLEMS | ^ 123

4 6
open-loop gain, is very large ( 1 0 to 10 ) and ideally infi­ • For both the inverting and the noninverting closed-loop con­
nite; and has an infinite input resistance and a zero output figurations, the 3-dB frequency is equal to f /(I+R /R ). t 2 l
VCC
resistance.
A B The maximum rate at which the op-amp output voltage
8 Negative feedback is applied to an op amp by connecting can change is called the slew rate. The slew rate, SR, is
a passive component between its output terminal and its usually specified in V/,us. Op-amp slewing can result in
DC = 15V VI = -1
inverting (negative) input terminal. Negative feedback nonlinear distortion of output signal waveforms.
V2 = 1
causes the voltage between the two input terminals to
TD =0 H The full-power bandwidth, f , is the maximum frequency
M
become very small and ideally zero. Correspondingly, a
TR = In at which an output sinusoid with an amplitude equal to the
virtual short circuit is said to exist between the two input
TF = In op-amp rated output voltage ( V ) can be produced omax
terminals. If the positive input terminal is Connected to
PW = 20YU without distortion: f = S R / 2 n : V .
M omax

DC = 15V ground, a virtual ground appears on the negative input

PER = 40YU terminal. • The input offset voltage, V , is the magnitude of dc volt­
os

age that when applied between the op amp input termi­

B The two most important assumptions in the analysis of
nals, with appropriate polarity, reduces the dc offset
VEE op-amp circuits, presuming negative feedback exists and
voltage at the output to zero.
the op amps are ideal, are: the two input terminals of the
FIGURE 2 . 5 1 Circuit for determining the slew rate of the //A741 op amp in Example 2.9. op amp are at the same voltage, and zero current flows a The effect of V on performance can be evaluated by
os

into the op-amp input terminals. including in the analysis a dc source V in series with the os
1.2 V
op-amp positive input lead. For both the inverting and the
§ With negative feedback applied and the loop closed,
noninverting configurations, V results in a dc offsetos
the closed-loop gain is almost entirely determined by
voltage at the output of V (I +
os R /R ). 2 x
0.8 V external components: For the inverting configuration,
V /Vj = -R /Ri;
0 2 and for the noninverting configura­ B Capacitively coupling an op amp reduces the dc offset
tion, V /Vi = 1
0 +R /R .
2 i
voltage at the output considerably.
0.4 V
B The noninverting closed-loop configuration features a B The average of the two dc currents, I and 7 > that How Bl B2
Slope = —0.5 V/yus in the input terminals of the op amp, is called the input
very high input resistance. A special case is the unity-gain
0V-- follower, frequently employed as a buffer amplifier to bias current, I . In a closed-loop amplifier, I gives rise to
B B

connect a high-resistance source to a low-resistance load. a dc offset voltage at the output of magnitude I R . This B 2
\ Slope = + 0 . 5 V/ytts
voltage can be reduced to I R0S by connecting a resistance
2

B For most internally compensated op amps, the open-loop in series with the positive input terminal equal to the total
-0.4 V
gain falls off with frequency at a rate of - 2 0 dB/decade, dc resistance seen by the negative input terminal. I is the os

reaching unity at a frequency / (the unity-gain band­ input offset current; that is, I = \I - I \.
os B1 B2

width). Frequency/, is also known as the gain-bandwidth

-0.8 V
product of the op amp: / = A f , where A is the dc gain,
0 b 0
B Connecting a large resistance in parallel with the capaci­
and/, is the 3-dB frequency of the open-loop gain. At any tor of an op-amp inverting integrator prevents op-amp sat­
-1.2 V frequency/(/§>/,), the op-amp gain |A| = / / / . uration (due to the effect of V and I ). os B

0 10 20 30 40 50 60 70 80
a
V(OUT)
Time Qxs)
FIGURE 2 . 5 2 Square-wave response of the ,uA741 op amp connected in the unity-gain configuration
shown in Fig. 2.51. P R O B L E M S

SECTION 2 . 1 : THE IDEAL OP AMP

SUMMARY
S The IC op amp is a versatile circuit building block. It is
easy to apply, and the performance of op-amp circuits
closely matches theoretical predictions.
positive power supply, and the negative-supply terminal
(V~) to be connected to the negative supply. The common
terminal of the two supplies is the circuit ground.
2.1 What is the minimum number of pins required for a so-
called dual-op-amp IC package, one containing two op amps?
What is the number of pins required for a so-called quad-op-
amp package, one containing four op amps?
2 . 2 The circuit of Fig. P2.2 uses an op amp that is ideal except
for having a finite gain A. Measurements indicate v = 4.0 V
0

B The op-amp terminals are the inverting input terminal (1), when v, = 4.0 V. What is the op amp gain A?
• The ideal op amp responds only to the difference input
the noninverting input terminal (2), the output terminal (3), signal, that is, ( v - v ); provides at the output, between
2 x 2 . 2 Measurement of a circuit incorporating what is thought to
1
the positive-supply terminal (V ") to be connected to the terminal 3 and ground, a signal A(v -v{),2 where A, the be an ideal op amp shows the voltage at the op amp output to be FIGURE P2.2
 1 24 CHAPTER 2 OPERATIONAL AMPLIFIERS PROBLEMS :_. 1 125

-2.000 V and that at the negative input to be -3.000 V. For the sinusoid. The output signal of the transducer is sinusoidal of
amplifier to be ideal, what would you expect the voltage at the 10-mV amplitude and 1000-Hz frequency. Give expressions
positive input to be? If the measured voltage at the positive input for vcnr v , and the total signal between each wire and the
d
is -3.020 V, what is likely to be the actual gain of the amplifier? system ground.
2 . 4 A set of experiments are run on an op amp that is ideal 2.7 Nonideal (i.e., real) operational amplifiers respond to
except for having a finite gain A. The results are tabulated both the differential and common-mode components of their
below. Are the results consistent? If not, are they reasonable, input signals (refer to Fig. 2.4 for signal representation). Thus
in view of the possibility of experimental error? What do they the output voltage of the op amp can be expressed as
show the gain to be? Using this value, predict values of the mea­
v
surements that were accidentally omitted (the blank entries). o —Av d Id + A v
where A is the differential gain (referred to simply as A in the
d many different inverting-amplifier circuit topologies are
Experiment # "i v2 v0
text) and A is the common-mode gain (assumed to be zero
cm
in the text). The op amp's effectiveness in rejecting common-
1 0.00 0.00 0.00 mode signals is measured by its CMRR, defined as
2 1.00 1.00 0.00
3 1.00 1.00
C M R R = 20 log
2.9 A particular inverting circuit uses an ideal op amp and 10 kQ
two 10-kQ resistors. What closed-loop gain would you V W
expect? If a dc voltage of +5.00 V is applied at the input,
what output result? If the 10-kQ resistors are said to be
" 5 % resistors," having values somewhere in the range
(1 ± 0.05) times the nominal value, what range of outputs
would you expect to actually measure for an input of pre­
cisely 5.00 V?
2 . 1 0 You are provided with an ideal op amp and three 10-kQ
cm Icm
resistors. Using series and parallel resistor combinations, how
FIGURE P 2 . 1 6
possible? What is the largest (noninfinite) available voltage
gain? What is the smallest (nonzero) available gain? What are
the input resistances in these two cases?
2 . 1 7 An inverting op amp circuit is fabricated with the
A, 2 . 1 1 For ideal op amps operating with the following feedback resistors R and R having x% tolerance (i.e., the value of each
t 2

4 1.00 1.10 10.1 A r networks in the inverting configuration, what closed-loop gain resistance can deviate from the nominal value by as much as
5 2.01 2.00 -0.99 Consider an op amp whose internal structure is of the type results? ±x%). What is the tolerance on the realized closed-loop gain?
6 1.99 2.00 1.00 Assume the op amp to be ideal. If the nominal closed-loop
shown in Fig. E2.3 except for a mismatch AG between the m
7 5.10 -5.10 (a) Ri = 10 k Q , R = 10 k Q
2 gain is - 1 0 0 V/V and x = 5, what is the range of gain values
transconductances of the two channels; that is,
(b) R x = 10 k Q , R = 100 k Q
2 expected from such a circuit?
(c) Ri = 10 k Q , i? = 1 k Q
2 . 5 Refer to Exercise 2.3. This problem explores an alterna­ 2

2 . 1 8 An ideal op amp with 5-kQ and 15-kQ resistors is

(d) R = 100 k Q , R = 10 M Q
tive internal structure for the op amp. In particular, we wish L 2

used to create a +5-V supply from a -15-V reference. Sketch

l + \AGm (e) R = 100 k Q , R = 1 M Q
to model the internal structure of a particular op amp using x 2

two transconductance amplifiers and one transresistance ampli­
fier. Suggest an appropriate topology. For equal transconduc-
Find expressions for A , A , and CMRR. If A is 80 dB and
d cm
the two transconductances are matched to within 0 . 1 % of
the circuit. What are the voltages at the ends of the 5-kQ
d
D2.1 2 Using an ideal op amp, what are the values of the resistor? If these resistors are so-called 1% resistors, whose
resistors R and R to be used to design amplifiers with the actual values are the range bounded by the nominal value
x 2

tances G and a transresistance R„„ find an expression for the

m each other, calculate A and CMRR. cm
closed-loop gains listed below? In your designs, use at least + 1 % , what are the limits of the output voltage produced? If
s
open-loop gain A. For G = 100 mA/V and R = 1 0 Q, what
m m
one 10-kQ resistor and another larger resistor. the -15-V supply can also vary by ± 1 % , what is the range of
value of A results? the output voltages that might be found?
SECTION 2 . 2 : THE INVERTING CONFIGURATION
(a) - 1 V/V
2 . 6 The two wires leading from the output terminals of a 2.8 Assuming ideal op amps, find the voltage gain v /v. B and (b) - 2 V/V 2 . 1 9 An inverting op-amp circuit for which the required
transducer pick up an interference signal that is a 60-Hz, 1-V input resistance R of each of the circuits in Fig. P2.8.
in (c) -0.5 V/V gain is - 5 0 V/V uses an op amp whose open-loop gain is only
(d) - 1 0 0 V/V 200 V/V. If the larger resistor used is 100 kQ, to what must
100 k O 100 kX2
the smaller be adjusted? With what resistor must a 2-kQ
D 2 . 1 3 Design an inverting op-amp circuit for which the
resistor connected to the input be shunted to achieved this
10 m gain is - 5 V/V and the total resistance used is 120 kQ.
goal? (Note that a resistor R is said to be shunted by resistor
V,- o- a

152.14 Using the circuit of Fig. 2.5 and assuming an ideal R when R is placed in parallel with R .)
b b a

op amp, design an inverting amplifier with a gain of 26 dB

having the largest possible input resistance under the con­
10 k Q
straint of having to use resistors no larger than 10 MO. What
is the input resistance of your design?
(a) (b) 2 . 1 5 An ideal op amp connected as shown in Fig. 2.5 of the
text with R = 10 kQ and R = 100 kQ. A symmetrical square-
x 2
wave signal with levels of 0 V and 1 V is applied at the input.
Sketch and clearly label the waveform of the resulting output
voltage. What is its average value? What is its highest value?
What is its lowest value?
D 2 . 2 0 (a) Design an inverting amplifier with a closed-loop
gain of - 1 0 0 V/V and an input resistance of 1 kQ.
(b) If the op amp is known to have an open-loop gain
of 1000 V/V, what do you expect the closed-loop gain
of your circuit to be (assuming the resistors have precise
values)?
(c) Give the value of a resistor you can place in parallel
(shunt) with Ri to restore the closed-loop gain to its nominal
value. Use the closest standard 1% resistor value (see
Appendix G).

2 . 1 6 For the circuit in Fig. P2.16, find the currents
through all branches and the voltages at all nodes. Since the
current supplied by the op amp is greater than the current
drawn from the input signal source, where does the addi­
tional current come from?
2 . 2 1 An op amp with an open-loop gain of 1000 V/V is
used in the inverting configuration. If in this application the
output voltage ranges from - 1 0 V to +10 V, what is the max­
imum voltage by which the "virtual ground node" departs
from its ideal value?
 1 2 6 PROBLEMS _ .I 1 27
W CHAPTER 2 OPERATIONAL AMPLIFIERS

2 . 2 2 The circuit in Fig. P2.22 is frequently used to provide For a closed-loop gain of - 1 0 0 and a gain error of <10%,
an output voltage v proportional to an input signal current i .
B t what is the minimum A required?
Derive expressions for the transresistance R = v /i and the m 0 t

input resistance R = v /i for the following cases:

f i l * 2 . 2 7 Using Eq. (2.5), determine the value of A for
which a reduction of A by x% results in a reduction
(a) A is infinite.
in \G\ by (x/k)%. Find the value of A required for the
(b) A is finite.
case in which the nominal closed-loop gain is 100, x is 50,
and k is 100.

2.28 Consider the circuit in Fig. 2.8 with R = R = R =\ Mfl,

x 2 4

and assume the op amp to be ideal. Find values for R to 3

obtain the following gains:

o v 0

(a) - 1 0 V / V
FIGURE P 2 . 3 1
(b) - 1 0 0 V/V
(c) - 2 V/V (c) Find the voltages at nodes 1, 2, 3, and 4, that is, V , V , V ,
x 2 3
(a) Find the required value for R.
FIGURE P 2 . 2 2 (b) ltR =l k Q and the op amp operates in an ideal manner so
and V in terms of (IR).
4
L

D 2 . 2 9 An inverting op-amp circuit using an ideal op amp long as v is in the range ±12 V. What range o f i s possible?
0

2 . 2 3 Derive an expression for the input resistance of the must be designed to have a gain of - 1 0 0 0 V/V using resistors 2 . 3 2 The circuit in Fig. P2.32 utilizes an ideal op amp. (c) What is the input resistance of the current amplifier? If
inverting amplifier of Fig. 2.5 taking into account the finite no larger than 100 kQ. the amplifier is fed with a current source having a current of
open-loop gain A of the op amp. (a) Find 7 I ,7 , and V .
1; 2 3 x

1 mA and a source resistance of 10 kQ, find i .

(a) For the simple two-resistor circuit, what input resistance (b) If V is not to be lower than - 1 3 V, find the maximum
0
L

* 2 . 2 4 For an inverting op amp with open-loop gain A and
nominal closed-loop gain R /R , find the minimum value
2 {
the gain A must have (in terms of R /R ) for a gain error of
0.1%, 1%, and 10%. In each case, what value of resistor R
can be used to shunt R to achieve the nominal result?
x
* 2 . 2 5 Figure P2.25 shows an op amp that is ideal except
for having a finite open-loop gain and is used to realize an
inverting amplifier whose gain has a nominal magnitude
G = R /R . To compensate for the gain reduction due to the
2 x
finite A, a resistor R is shunted across R . Show that perfect
c x
compensation is achieved when R is selected according to
would result? allowed value for R . L
2 . 3 4 Figure P2.34 shows the inverting amplifier circuit of
(c) If R is varied in the range 100 Q to 1 kQ, what is the
(b) If the circuit in Fig. 2.8 is used with three resistors of L
Fig. 2.8 redrawn to emphasize the fact that R and R can be
3 A
corresponding change in I and in V ?
2 x
maximum value, what input resistance results? What is the L 0 thought of as a voltage divider connected across the output v 0
ia
value of the smallest resistor needed? and from which a fraction of the output voltage (that avail-
able at node A) is fed back through R . Assuming R > R
2 2 3
2 . 3 0 The inverting circuit with the T network in the feed-
and thus that the loading of the feedback network can be
back is redrawn in Fig. P2.30 in a way that emphasizes the
ignored, express v as a function of v . Now express v as a
A 0 A
observation that R and R in effect are in parallel (because
2 3
function of v,. Use these two relationships to find the (approx-
the ideal op amp forces a virtual ground at the inverting input
imate) relationship between v and vj. With appropriate
0
terminal). Use this observation to derive an expression for the
manipulation, compare it with the result obtained in Exam-
gain (v /v,)
0 by first finding (v /v,) and
x (v /v ). 0 x
c
ple 2.2. Show that the exact result can be obtained by noting
that R appears in effect across R and, thus, that the voltage
2 3

A-G divider is composed of R and (R II R ).

4 3 2

l +G

FIGURE P 2 . 3 2

D2.33 Assuming the op amp to be ideal, it is required to

design the circuit shown in Fig. P2.33 to implement a current
v¡<y
amplifier with gain i /i, = 20 A/A.
L

o V„

FIGURE P2.25 FIGURE P 2 . 3 0

*2.26 Rearrange Eq. (2.5) to give the amplifier open-loop * 2 . 3 1 The circuit in Fig. P2.31 can be considered an exten- ov0
sion of the circuit in Fig. 2.8.
gain A required to realize a specified closed-loop gain FIGURE P2.34
(^nominal -R /R{] within a specified gain error e,
2
(a) Find the resistances looking into node 1, R ; node 2, R ;
x 2
D 2 . 3 5 Design the circuit shown in Fig. P2.35 to have an
node 3, R \ and node 4, R .
3 4
G-G nominal I
input resistance of 100 kQ and a gain that can be varied from
(b) Find the currents /[, I , I , and I in terms of the input
2 3 4
- 1 V/V to - 1 0 V/V using the 10-kQ potentiometer R . What 4
J
nominal current I. FIGURE P 2 . 3 3
 12S :,„3 CHAPTER 2 OPERATIONAL AMPLIFIERS
PROBLEMS ¡ 1 2 9

voltage gain results when the potentiometer is set exactly at D 2 . 4 1 Use two ideal op amps and resistors to implement (b) Design a circuit to obtain
SECTION 2 . 3 : THE NONINVERTING
its middle value? the summing function.
R 3
CONFIGURATION v0 = -2v N1 + v +2vp
Pl 2

v0 = v + 2 v - 3 v - 4v
x 2 3 4
0 2 . 4 4 Using an ideal op amp to implement designs for the The smallest resistor used should be 10 tel.
D * 2 . 4 2 In an instrumentation system, there is a need to following closed-loop gains, what values of resistors (R R ) u 2

take the difference between two signals, one of v = 3 sin(2;r x t

should be used? Where possible, use at least one 10-kQ resis- RNI
60») + 0.01 sin(2ro x 10000, volts and another of v = 2
tor as the smallest resistor in your design. v m o VW
3 sin(27r x 600 - 0.01 sin(27r x 10000 volts. Draw a circuit
(a) +1 V/V
that finds the required difference using two op amps and
(b) +2 V/V
mainly 10-kQ resistors. Since it is desirable to amplify the
(c) +101 V/V
1000-Hz component in the process, arrange to provide an
(d) +100 V/V
overall gain of 10 as well. The op amps available are ideal
except that their output voltage swing is limited to ±10 V. D2.45 Design a circuit based on the topology of the non-
inverting amplifier to obtain a gain of +1.5 V/V, using only
* 2 . 4 3 Figure P2.43 shows a circuit for a digital-to-analog 10-kQ resistors. Note that there are two possibilities. Which of vpi o W \ 1

converter (DAC). The circuit accepts a 4-bit input binary these can be easily converted to have a gain of either +1.0 V/V Rp2
FIGURE P 2 . 3 5 word a a a a , where a , a a , and a take the values of 0 or
3 2 x a 0 lt 2 3 or +2.0 V/V simply by short-circuiting a single resistor in v o W V 11
P2

1, and it provides an analog output voltage v proportional 0 each case?

236 A weighted summer circuit using an ideal op amp has to the value of the digital input. Each of the bits of the input
• 11—
three inputs using 100-kfl resistors and a feedback resistor of D2.46 Figure P2.46 shows a circuit for an analog voltmeter Rpn •
word controls the correspondingly numbered switch. For v o W V "
50 k£2. A signal v is connected to two of the inputs while a
x
instance, if a is 0 then switch S connects the 20-kO resistor of very high input resistance that uses an inexpensive Pn

2 2

signal v is connected to the third. Express v in terms of v

2 0 x
to ground, while if a is 1 then S connects the 20-kQ resistor moving-coil meter. The voltmeter measures the voltage V
and v . If T>] = 3 V and v = - 3 V, what is v 'l
2 2
^Rpp
2 2 0
to the +5-V power supply. Show that v is given by 0
applied between the op amp's positive-input terminal and
ground. Assuming that the moving coil produces full-scale
0 2 . 3 7 Design an op amp circuit to provide an output
v = — h 2 a + 2 a + 2 a^ + l a\ deflection when the current passing through it is 100 fiA, find
v = - [ 4 ^ ! + ( i i / 3 ) ] . Choose relatively low values of resis-
0 2
0
16
0 l 3

the value of R such that full-scale reading is obtained when V FIGURE P 2 . 4 7

tors but ones for which the input current (from each input
where R is in kQ. Find the value of R so that v ranges from is +10 V. Does the meter resistance shown affect the voltmeter
signal source) does not exceed 0.1 mA for 1-V input signals. f f 0

0 to - 1 2 volts. calibration? D 2 . 4 8 Design a circuit, using one ideal op amp, whose out-
D 2 . 3 8 Using the scheme illustrated in Fig. 2.10, design an put is v — v + 3v -2(v 0 n + 3v ). (Hint: Use a sUucture
I2 r} [4

op-amp circuit with inputs v\, v , and v whose output is Moving-coil meter similar to that shown in general form in Fig. P2.47.)
2 3

v = -(21»! + 4v + &v ) using small resistors but no smaller

0 2 3

than 10 tel. 2 . 4 9 Derive an expression for the voltage gain, v /v,, 0 of

the circuit in Fig. P2.49.
D 2 . 3 9 An ideal op amp is connected in the weighted sum-
mer configuration of Fig. 2.10. The feedback resistor R = f
R2

10 kfl, and six 10-kQ. resistors are connected to the inverting

input terminal of the op amp. Show, by sketching the various
circuit configurations, how this basic circuit can be used to
implement the following functions:
(a) v
0 = -(v + 2v + 3v )
i 2 3

(b) v0 = ~(V + V + 2V + 2VA)

1 2 3

(c) v
0 = H > i +5v ) 2

(d) v
0 = -6v x

FIGURE P 2 . 4 6
In each case find the input resistance seen by each of the sig-
nal sources supplying v , v , v , and v . Suggest at least
x 2 3 A two D * 2 . 4 7 (a) Use superposition to show that the output of
FIGURE P 2 . 4 9
additional summing functions that you can realize with this the circuit in Fig. P2.47 is given by
circuit. How would you realize a summing coefficient that 2 . 5 0 For the circuit in Fig. P2.50, use superposition to find
is 0.5? v
vR f R, R f 1
o = - -^v N } +-^v N 2 +- • •+ — % J v in terms of the input voltages v and v . Assume an ideal
0 x 2

D 2 . 4 0 Give a circuit, complete with component values, for op amp. For

a weighted summer that shifts the dc level of a sine-wave sig-
nal of 5 sin(fflf) V from zero to - 5 V. Assume that in addition v = 10sin(27z; x 6 0 f ) - 0 . 1 s i n ( 2 t f x 10001), volts
x

to the sine-wave signal you have a dc reference voltage of 2 V v = 10sin(2K x 6 0 0 + 0.1sin(2/r x lOOOf), volts
2
where R = R IIR ll
N m m • • • IIRm and
available. Sketch the output signal waveform.
FIGURE P 2 . 4 3 R = R //R //
P P1 P2 • • • IIRpJIRpo find v . n
 1 3 0 ' CHAPTER 2 OPERATIONAL AMPLIFIERS
PROBLEMS 1 3 1

2 . 5 5 Complete the following table for feedback amplifiers + 15 V 2 . 6 3 Consider the difference amplifier of Fig. 2.16 with the
created using one ideal op amp. Note that i? signifies input in two input terminals connected together to an input common-
resistance and R and R are feedback-network resistors as
x 2 mode signal source. For R /R = R /R ,
2 show that the input
x 4 3

labelled in the inverting and noninverting configurations. common-mode resistance is (R + R ) || (R + R ). 3 A l 2

2 . 6 4 Consider the circuit of Fig. 2.16, and let each of the %

Case Gain "IN and v signal sources have a series resistance R . What condi­
I2 s

a tion must apply in addition to the condition in Eq. (2.15) in order

-10 V/V 10 k Q
b - 1 V/V for the amplifier to function as an ideal difference amplifier?
100 kQ
c -2 V/V 100 kQ * 2 . 6 5 For the difference amplifier shown in Fig. P2.62, let
d +1V/V
e +2 V/V all the resistors be 100 kQ + x%. Find an expression for the
10 kQ
f +11 V/V worst-case common-mode gain that results. Evaluate this forx =
100 kQ
-0.5 V/V 10 kQ 0.1, 1, and 5. Also, evaluate the resulting CMRR in each case.
FIGURE P 2 . 5 0
2 . 6 6 For the difference amplifier of Fig. 2.16, show that if each
resistor has a tolerance of ±100 e% (i.e., for, say, a 5% resistor,
0 2 . 5 1 The circuit shown in Fig. P2.51 utilizes a 10-kQ D 2 . 5 6 A noninverting op-amp circuit with nominal gain of
£ = 0.05) then the worst-case CMRR is given approximately by
potentiometer to realize an adjustable-gain amplifier. 10 V/V uses an op amp with open-loop gain of 50 V/V and a
Derive an expression for the gain as a function of the poten­ lowest-value resistor of 10 kQ. What closed-loop gain actually FIGURE P 2 . S 9
J K + r
CMRR = 20 log
tiometer setting x. Assume the op amp to be ideal. What is the results? With what value resistor can which resistor be 4e
range of gains obtained? Show how to add a fixed resistor shunted to achieve the nominal gain? If in the manufacturing SECTION 2 . 4 : DIFFERENCE AMPLIFIERS where K is the nominal (ideal) value of the ratios(R-,/R ) x
so that the gain range can be 1 to 21 V/V. What should the process, an op amp of gain 100 V/V were used, what closed-
2 . 6 0 Find the voltage gain v /v for the difference ampli­ and (R /R ). Calculate the value of worst-case CMRR for an
4 3
resistor value be? loop gain would result in each case (the uncompensated one, 0 ld

fier of Fig. 2.16 for the case R = R = 10 k Q and R = R = amplifier designed to have a differential gain of ideally 100 V/V,
and the compensated one)? x 3 2 4

10-kQ pot
2 . 5 7 Using Eq. (2.11), show that if the reduction in the
AWWVVW
closed-loop gain G from the nominal value G = 1 + R /R
is to b e kept less than x% of G , then the open-loop gain
0
of the op amp must exceed G by at least a factor F = 0
o V
(100/JC) - 1 = 100/jc. Find the required F for x = 0.01, 0.1,
0
1, and 10. Utilize these results to find for each value of x the
minimum required open-loop gain to obtain closed-loop
100 kQ. What is the differential input resistance R 7 If the assuming that the op amp is ideal and that 1% resistors are used.
id
two key resistance ratios (R /R\)
2 and (R /R ) are different
4 3
D * 2 . 6 7 Design the difference amplifier circuit of Fig. 2.16
Q 1 l
from each other by 1%, what do you expect the common- to realize a differential gain of 100, a differential input resis­
mode gain A to be? Also, find the CMRR in this case.
cm
tance of 20 kQ, and a minimum CMRR of 80 dB. Assume the
op amp to be ideal. Specify both the resistor values and their
D 2 . 6 1 Using the difference amplifier configuration of
required tolerance (e.g., better than x%).
Fig. 2.16 and assuming an ideal op-amp, design the circuit to
provide the following differential gains. In each case the dif­ * 2 . 6 8 (a) Find A and A for the difference amplifier circuit
d cm

2 3
gains of 1, 10, 10 , 10 , and 1 0 V/V. 4 ferential input resistance should be 20 kQ.
shown in Fig. P2.68.
FIGURE P 2 . 5 1
(a) 1V/V (b) If the op amp is specified to operate properly so long as the
2 . 5 8 For each of the following combinations of op-amp common-mode voltage at its positive and negative inputs falls
(b) 2 V/V
D 2 . 5 2 Given the availability of resistors of value 1 kQ and open-loop gain A and nominal closed-loop gain G , calculate 0
in the range ±2.5 V, what is the corresponding limitation on the
(c) 100 V/V
10 k Q only, design a circuit based on the noninverting con­ the actual closed-loop gain G that is achieved. Also, calculate range of the input common-mode signal %,„? (This is known
(d) 0.5 V/V
figuration to realize a gain of+10 V/V. the percentage by which \G\ falls short of the nominal gain as the common-mode range of the differential amplifier).
magnitude \G \. 2 . 6 2 For the circuit shown in Fig. P2.62, express v as a
0 a
(c) The circuit is modified by connecting a 10-kQ resistor
2 . 5 3 It is required to connect a 10-V source with a source function of v and v . What is the input resistance seen by v
x 2 x
between node A and ground and another 10-kQ resistor
resistance of 100 kQ to a 1-kQ load. Find the voltage that Case (V/V) alone? By v alone? By a source connected between the two
G,. A(V/V) 2
between node B and ground. What will now be the values of
will appear across the load if:
input terminals? By a source connected to both input termi­ A , A , and the input common-mode range?
a -1 10
d cm

(a) The source is connected directly to the load. nals simultaneously?

h +1 10 100 k Q
(b) A unity-gain op-amp buffer is inserted between the source c -1 100
and the load. d +10 10
e -10 100 100 k Q
In each case find the load current and the current supplied by f % o WV
-10 1000
the source. Where does the load current come from in case (b)? +1 O v
g 2 0

vo I2 WV
2 . 5 4 Derive an expression for the gain of the voltage fol­ 100 k Q
lower of Fig. 2.14 assuming the op amp to be ideal except 2 . 5 9 Figure P2.59 shows a circuit that provides an output
for having a finite gain A. Calculate the value of the closed- voltage v whose value can be varied by turning the wiper of
0

loop gain for A = 1000, 100, and 10. In each case find the the 100-kQ potentiometer. Find the range over which v can a

percentage error in gain magnitude from the nominal value be varied. If the potentiometer is a "20-turn" device, find the
of unity. change in v corresponding to each turn of the pot.
0
FIGURE P 2 . 6 2 FIGURE P 2 . 6 8
 1 3 2
V«*> CHAPTER 2 OPERATIONAL AMPLIFIERS PROBLEMS 1 33

* * 2 . 6 9 To obtain a high-gain, high-input-resistance differ- the first stage of this instrumentation amplifier and hence the shown in Fig. 1.13), what is the largest sine wave output that
0 * 2 . 7 1 The circuit shown in Fig. P2.71 is a representation
ence amplifier the circuit in Fig. P2.69 employs positive feed- of a versatile, commercially available IC, the INA105, manu- can be accommodated? Specify both its peak-to-peak and rms
back, in addition to the negative feedback provided by the CMRR-
factured by Burr-Brown and known as a differential amplifier values.
resistor R connected from the output to the negative input of (b) Repeat for the circuit in Fig. 2.20(b), and comment on the
module. It consists of an op amp and precision, laser-
the op amp. Specifically, a voltage divider (R , R ) connected difference between the two circuits.
s 6
trimmed, metal-film resistors. The circuit can be configured
across the output feeds a fraction ¡3 of the output, that is, a for a variety of applications by the appropriate connection of * * 2 . 7 5 For an instrumentation amplifier of the type shown in
voltage j3v , back to the positive-input terminal of the op
0
terminals A, B, C, D, and O. Fig. 2.20(b), a designer proposes to make R = R = R = 100 kQ,
2 3 ±

amp through a resistor R. Assume that R and R are much 5 6 and 2Ri = 10 kQ. For ideal components, what difference-mode
smaller than R so that the current through R is much lower 25 k Q gain, common-mode gain, and CMRR result? Reevaluate the
than the current in the voltage divider, with the result that AO WV worst-case values for these for the situation in which all resis-
P~ R \(R + R ). Show that the differential gain is given by
6 5 6 tors are specified as ± 1 % units. Repeat the latter analysis for
the case in which 27?] is reduced to 1 kQ. What do you con-
A - v
° - 1
clude about the importance of the relative difference gains of
AO-
the first and second stages?
Design the circuit to obtain a differential gain of 10 V/V and 0 2 . 7 6 Design the instrumentation-amplifier circuit of
differential input resistance of 2 MQ. Select values for R, R , 5 B o- - w v WV -OD Fig. 2.20(b) to realize a differential gain, variable in the range
mdR such that (R + R )
6 <R/100.
s 6 25 k Q 25 kQ 1 to 100, utilizing a 100-kQ pot as variable resistor. (Hint:
FIGURE P2.71 Design the second stage for a gain of 0.5.)

(a) Show how the circuit can be used to implement a differ- * 2 . 7 7 The circuit shown in Fig. P2.77 is intended to supply
ence amplifier of unity gain. a voltage to floating loads (those for which both terminals are
(b) Show how the circuit can be used to implement single- ungrounded) while making greatest possible use of the avail-
FIGURE P2.77
ended amplifiers with gains: able power supply.
O v n
* 2 . 7 8 The two circuits in Fig. P2.78 are intended to func-
(i) - 1 V/V (a) Assuming ideal op amps, sketch the voltage waveforms at
(ii) +1 V/V nodes B and C for a 1 -V peak-to-peak sine wave applied at A. tion as voltage-to-current converters; that is, they supply the
(iii) +2 V/V Also sketch v . load impedance Z with a current proportional to v and inde-
L {
0

O ß V o (iv) +1/2 V/V (b) What is the voltage gain v /vp. pendent of the value of Z . Show that this is indeed the case,
L
0

(c) Assuming that the op amps operate from ±15-V power and find for each circuit i as a function of v,. Comment on
0

FIGURE P2.69
* 2 . 7 0 Figure P2.70 shows a modified version of the differ-
ence amplifier. The modified circuit includes a resistor R ,
which can be used to vary the gain. Show that the differential
voltage gain is given by
Avoid leaving a terminal open-circuited, for such a terminal supplies and that their output saturates at ±14 V (in the manner the differences between the two circuits.
may act as an "antenna," picking up interference and noise
through capacitive coupling. Rather, find a convenient node to
connect such a terminal in a redundant way. When more than
one circuit implementation is possible, comment on the rela-
tive merits of each, taking into account such considerations as
G
dependence on component matching and input resistance.
2 . 7 2 Consider the instrumentation amplifier of Fig. 2.20(b)
with a common-mode input voltage of +3 V (dc) and a differ-
ential input signal of 80-mV peak sine wave. Let 2R = 1 kO, X

«2 = _ ^ R I + ^2
*1
(Hint: The virtual short circuit at the op amp input causes the
current through thei?j resistors to be v /2R )
R = 50 k Q , R3 = R4 = 10 kQ. Find the voltage at every node in
2
the circuit.
ld v 2 . 7 3 (a) Consider the instrumentation amplifier circuit of
Fig. 2.20(a). If the op amps are ideal except that their outputs
saturate at ±14 V, in the manner shown in Fig. 1.13, find the
maximum allowed input common-mode signal for the case
/?! = 1 k Q a n d i ? = 100 kQ.
2

(b) Repeat (a) for the circuit in Fig. 2.20(b), and comment on
the difference between the two circuits.

2 . 7 4 (a) Expressing % and v in terms of differential and

n

common-mode components, find v and v in the circuit

01 02

in Fig. 2.20(a) and hence find their differential component (a) (b)
v ar
02 ~ voi >d their common-mode component ~(v + v ). ol 02

FIGURE P2.70 Now find the differential gain and the common-mode gain of FIGURE P 2 . 7 8
 134 i ...
c CHAPTER 2 OPERATIONAL AMPLIFIERS
PROBLEMS ^JV 135

SECTION 2 . 5 : EFFECT OF FINITE OPEN-LOOP 2 . 8 6 A noninverting op-amp circuit with a gain of 100 V/V » 2 . 9 2 Consider an inverting, summer with two inputs V X This problem illustrates the point by considering the use of an
GAIN AND BANDWIDTH ON CIRCUIT is found to have a 3-dB frequency of 8 kHz. For a particular and V and with V = -(Vj + V ). Find the 3-dB frequency of
2 0 2 op amp w i t h / = 2 MHz, SR = 1 V//is, and V = 10 V in the
omax

PERFORMANCE system application, a bandwidth of 20 kHz is required. What each of the gain functions V /V*i and V / V in terms of the
D 0 2 design of a noninverting amplifier with a nominal gain of 10.
is the highest gain available under these conditions? op a m p / - (Hint: In each case, the other input to the summer Assume a sine-wave input with peak amplitude V .
2 . 7 9 The data in the following table apply to internally t

can be set to zero—an application of superposition.)

compensated op amps. Fill in the blank entries. 2 . 8 7 Consider a unity-gain follower utilizing an internally (a) If V, = 0.5 V, what is the maximum frequency before the
compensated op amp w i t h / = 1 MHz. What is the 3-dB fre­ output distorts?
4 (Hz) quency of the follower? At what frequency is the gain of the SECTION 2 . 6 : LARGE-SIGNAL OPERATION
(b) I f / = 20 kHz. what is the maximum value of Vj before the
5
10 2 follower 1% below its low-frequency magnitude? If the input OF OP AMPS output distorts?
10
10 6
10 6 to the follower is a 1-V step, find the 10% to 90% rise time of 2 . 9 3 A particular op amp using +15-V supplies operates (c) If Vj = 50 mV, what is the useful frequency range of
10 3
10 8
the output voltage. (Note: The step response of STC low-pass linearly for outputs in the range - 1 2 V to +12 V. If used in an operation?
10" 1
10 6
networks is discussed in Appendix D.) inverting amplifier configuration of gain -100, what is the (d) I f / = 5 kHz, what is the useful input voltage range?
5
2xl0 10 rms value of the largest possible sine wave that can be
D * 2 . 8 8 It is required to design a noninverting amplifier
applied at the input without output clipping? SECTION 2 . 7 : DC IMPERFECTIONS
with a dc gain of 10. When a step voltage of 100 mV is
2 . 8 0 A measurement of the open-loop gain of an internally
applied at the input, it is required that the output be within 1% 2 . 9 4 Consider an op amp connected in the inverting config­ 2 . 1 0 0 An op amp wired in the inverting configuration with
compensated op amp at very low frequencies shows it to be
of its final value of 1 V in at most 100 ns. What must t h e / of uration to realize a closed-loop gain of - 1 0 0 V/V utilizing the input grounded, having R = 100 k Q and R = 1 kQ, has
86 dB; at 100 kHz, this shows it is 40 dB. Estimate values for 2 x

the op amp be? (Note: The step response of STC low-pass resistors of 1 kQ and 100 kQ. A load resistance R is con­ an output dc voltage of -0.3 V. If the input bias current is
AoJb, and/,. L

networks is discussed in Appendix D.) nected from the output to ground, and a low-frequency sine- known to be very small, find the input offset voltage.
2 . 8 1 Measurements of the open-loop gain of a compensated wave signal of peak amplitude V is applied to the input. Let
D * 2 . 8 9 This problem illustrates the use of cascaded closed- p

2 . 1 0 1 A noninverting amplifier with a gain of 200 uses an

op amp intended for high-frequency operation indicate that the
3 3
gain is 5.1 x 10 at 100 kHz and 8.3 x 10 at 10 kHz. Estimate
its 3-dB frequency, its unity-gain frequency, and its dc gain.
the op amp be ideal except that its output voltage saturates at
loop amplifiers to obtain an overall bandwidth greater than op amp having an input offset voltage of ±2 mV. Find the
+10 V and its output current is limited to the range +20 mA.
can be achieved using a single-stage amplifier with the same output when the input is 0.01 sin cot, volts.
overall gain.
(a) For R = 1 kQ, what is the maximum possible value of V
L p

2 . 8 2 Measurements made on the internally compensated 2 . 1 02 A noninverting amplifier with a closed-loop gain of
(a) Show that cascading two identical amplifier stages, each while an undistorted output sinusoid is obtained?
amplifiers listed below provide the dc gain and the frequency 1000 is designed using an op amp having an input offset volt­
having a low-pass STC frequency response with a 3-dB (b) Repeat (a) for R = 100 Q.
L
at which the gain has dropped by 20 dB. For each, what are age of 3 mV and output saturation levels of +13 V. What is
f r e q u e n c y / , results in an overall amplifier with a 3-dB fre­ (c) If it is desired to obtain an output sinusoid of 10-V peak
the 3 dB and unity-gain frequencies? the maximum amplitude of the sine wave that can be applied
quency given by amplitude, what minimum value of R is allowed?
L

5 2
at the input without the output clipping? If the amplifier is
(a) 3 x 10 V/V and 6 x 10 Hz,
5
/3dB = JJ2 - 1 /j 2 . 9 5 An op amp having a slew rate of 20 V//is is to be used capacitively coupled in the manner indicated in Fig. 2.36,
(b) 50 x l O V/V and 10 Hz
in the unity-gain follower configuration, with input pulses what would the maximum possible amplitude be?
(c) 1500 V/V and 0.1 MHz (b) It is required to design a noninverting amplifier with a
that rise from 0 to 3 V. What is the shortest pulse that can be
(d) 100 V/V and 0.1 GHz dc gain of 40 dB utilizing a single internally-compensated 2 . 1 03 An op amp connected in a closed-loop inverting
used while ensuring full-amplitude output? For such a pulse,
(e) 25 V/mV and 25 kHz op amp with / = 1 MHz. What is the 3-dB frequency configuration having a gain of 1000 V/V and using relatively
describe the output resulting.
obtained? small-valued resistors is measured with input grounded to
2 . 8 3 An inverting amplifier with nominal gain of - 2 0 V/V
4 (c) Redesign the amplifier of (b) by cascading two identical * 2 . 9 6 For operation with 10-V output pulses with the have a dc output voltage of - 1 . 4 V. What is its input offset
employs an op amp having a dc gain of 10 and a unity-gain
6 noninverting amplifiers each with a dc gain of 20 dB. What is requirement that the sum of the rise and fall times should rep­ voltage? Prepare an offset-voltage-source sketch resembling
frequency of 10 Hz. What is the 3-dB frequency/ of the 3dB
the 3-dB frequency of the overall amplifier? Compare this to resent only 20% of the pulse width (at half amplitude), what that in Fig. 2.28. Be careful of polarities.
closed-loop amplifier? What is its gain at 0 . 1 / and at 1 0 / ? 3 d B 3dB
the value obtained in (b) above.
is the slew-rate requirement for an op amp to handle pulses
2 . 8 4 A particular op amp, characterized by a gain-bandwidth 2 . 1 0 4 A particular inverting amplifier with nominal gain
D * * 2 . 9 0 A designer, wanting to achieve a stable gain of 2 ^s wide? (Note: The rise and fall times of a pulse signal are
product of 20 MHz, is operated with a closed-loop gain of of - 1 0 0 V/V uses an imperfect op amp in conjunction with
100 V/V at 5 MHz, considers her choice of amplifier topologies. usually measured between the 10%- and 90%-height points.)
+100 V/V. What 3-dB bandwidth results? At what frequency 100-kQ and 10-MQ resistors. The output voltage is found to
does the closed-loop amplifier exhibit a - 6 ° phase shift? A What unity-gain frequency would a single operational ampli­
2 . 9 7 What is the highest frequency of a triangle wave of 20-V be +9.31 V when measured with the input open and +9.09 V
- 8 4 ° phase shift? fier require to satisfy her need? Unfortunately, the best avail­
peak-to-peak amplitude that can be reproduced by an op amp with the input grounded.
able amplifier has a n / of 40 MHz. How many such amplifiers
whose slew rate is 10 V/,us? For a sine wave of the same fre­
2 . 8 5 Find t h e / required for internally compensated op amps connected in a cascade of identical noninverting stages would (a) What is the bias current of this amplifier? In what direc­
quency, what is the maximum amplitude of output signal that
to be used in the implementation of closed-loop amplifiers she need to achieve her goal? What is the 3-dB frequency of tion does it flow?
remains undistorted?
with the following nominal dc gains and 3-dB bandwidths: each stage she can use? What is the overall 3-dB frequency? (b) Estimate the value of the input offset voltage.
(a) - 1 0 0 V/V; 100 kHz 2 . 9 8 For an amplifier having a slew rate of 60 V/^us, what is (c) A 10-MQ resistor is connected between the positive-
2 . 9 1 Consider the use of an op amp with a unity-gain fre­
(b) +100 V/V; 100 kHz the highest frequency at which a 20-V peak-to-peak sine input terminal and ground. With the input left floating (dis­
q u e n c y / in the realization of
(c) +2 V/V; 10 MHz wave can be produced at the output? connected), the output dc voltage is measured to be - 0 . 8 V.
(d) - 2 V/V; 10 MHz (a) an inverting amplifier with dc gain of magnitude K. Estimate the input offset current.
(b) a noninverting amplifier with a dc gain of K. D * 2 . 9 9 In designing with op amps one has to check the
(e) - 1 0 0 0 V/V; 20 kHz 0 * 2 . 1 0 5 A noninverting amplifier with a gain of+10 V/V
limitations on the voltage and frequency ranges of operation
(f) +1 V/V; 1 MHz In each case find the 3-dB frequency and the gain-bandwidth using 100 kQ as the feedback resistor operates from a 5-kQ
of the closed-loop amplifier, imposed by the op amp finite
(g) - 1 V/V; 1 MHz product (GBP = |Gain| x / ) . Comment on the results. source. For an amplifier offset voltage of 0 mV, but with a
3 d B bandwidth ( / ) , slew rate (SR), and output saturation ( V ) .
omax
 13 - .J 1
CHAPTER 2 OPERATIONAL AMPLIFIERS
bias current of 1 piA and an offset current of 0.1 LtA, what
range of outputs would you expect? Indicate where you
would add an additional resistor to compensate for the bias
currents. What does the range of possible outputs then
become? A designer wishes to use this amplifier with a 15-kQ
source. In order to compensate for the bias current in this
case, what resistor would you use? And where?
0 2 . 1 0 6 The circuit of Fig. 2.36 is used to create an ac-
coupled noninverting amplifier with a gain of 200 V/V using
resistors no larger than 100 kQ. What values ofR R , and R x>
should be used? For a break frequency due to C, at 100 Hz,
and that due to C at 10 Hz, what values of C and C are
2 x
needed?
*2.107 Consider the difference amplifier circuit in Fig. 2.16.
Let R =R X = 10 k Q and R = R =l
3 M Q . If the op amp has
2 4
V = 4 mV, I = 0.3 fjA, and I = 50 nA, find the worst-case
os B os
(largest) dc offset voltage at the output.
* 2 . 1 0 8 The circuit shown in Fig. P2.108 uses an op amp
having a ±4-mV offset. What is its output offset voltage?
What does the output offset become with the input ac cou­
pled through a capacitor C? If, instead, the 1-kQ resistor is
capacitively coupled to ground, what does the output offset
become?
1 MQ 1 MQ
1 MQ
o WV
FIGURE P 2 . 1 0 8
2 . 1 0 9 Using offset-nulling facilities provided for the op
amp, a closed-loop amplifier with gain of+1000 is adjusted
at 25°C to produce zero output with the input grounded. If the
input offset-voltage drift of the op amp is specified to be
0
10 ,uV/ C, what output would you expect at 0°C and at 75°C?
While nothing can be said separately about the polarity of the
output offset at either 0 or 75°C, what would you expect their
relative polarities to be?
2 . 1 1 0 An op amp is connected in a closed loop with gain of
+100 utilizing a feedback resistor of 1 MQ.
(a) If the input bias current is 100 nA, what output voltage
results with the input grounded?
(b) If the input offset voltage is ±1 mV and the input bias
current as in (a), what is the largest possible output that can
be observed with the input grounded?
(c) If bias-current compensation is used, what is the value of
the required resistor? If the offset current is no more than
one-tenth the bias current, what is the resulting output offset
voltage (due to offset current alone)?
(d) With bias-current compensation as in (c) in place what is
the largest dc voltage at the output due to the combined effect
of offset voltage and offset current?
2 3
* 2 . 1 1 1 An op amp intended for operation with a closed-
2 loop gain of - 1 0 0 V/V uses feedback resistors of 10 kQ and
1 M Q with a bias-current-compensation resistor R . What3
should the value of R be? With input grounded, the output
3 input levels are ±2 V, with the time constant the same (1 ms)
offset voltage is found to be +0.21 V. Estimate the input offset
current assuming zero input offset voltage. If the input offset
voltage can be as large as 1 mV of unknown polarity, what
range of offset current is possible? What current injected into,
or extracted from, the nongrounded end of R would reduce
3
the op amp output voltage to zero? For available ±15-V sup­
plies, what resistor and supply voltage would you use?
SECTION 2 . 8 : INTEGRATORS A N 0
DIFFERENTIATORS
2 . 1 1 2 A Miller integrator incorporates an ideal op amp, a
resistor R of 100 kQ, and a capacitor C of 10 nF. A sine-wave
signal is applied to its input.
(a) At what frequency (in Hz) are the input and output sig­
nals equal in amplitude?
(b) At that frequency how does the phase of the output sine
wave relate to that of the input?
(c) If the frequency is lowered by a factor of 10 from that
found in (a), by what factor does the output voltage change,
and in what direction (smaller or larger)?
(d) What is the phase relation between the input and output
in situation (c)?
D 2 . 1 1 3 Design a Miller integrator with a time constant of
one second and an input resistance of 100 kQ. For a dc voltage
of - 1 volt applied at the input at time 0, at which moment
v = - 1 0 V, how long does it take the output to reach 0 V?+10 V?
0
2 . 1 1 4 An op-amp-based inverting integrator is measured at
1 kHz to have a voltage gain o f - 1 0 0 V/V. At what frequency
is its gain reduced to - 1 V/V? What is the integrator time
constant?
0 2 . 1 1 5 Design a Miller integrator that has a unity-gain fre­
quency of 1 krad/s and an input resistance of 100 kQ. Sketch
the output you would expect for the situation in which, with
output initially at 0 V, a 2-V 2-ms pulse is applied to the
input. Characterize the output that results when a sine wave
2 sin 1000? is applied to the input?
0 2 . 1 1 6 Design a Miller integrator whose input resistance
is 20 kQ and unity-gain frequency is 10 kHz. What compo­
nents are needed? For long-term stability, a feedback resistor
is introduced across the capacitor, which limits the dc gain to
40 dB. What is its value? What is the associated lower 3-dB
frequency? Sketch and label the output which results with a
0.1-ms, 1-V positive-input pulse (initially at 0 V) with (a) no
dc stabilization (but with the output initially at 0 V) and
(b) the feedback resistor connected.
# 2 . 1 1 7 A Miller integrator whose input and output volt-
aces are initially zero and whose time constant is 1 ms is
driven by the signal shown in Fig. P2.117. Sketch and label
the output waveform that results. Indicate what happens if the
and with the time constant raised to 2 ms.
Ü/(V)A
+1
_
0.5
-1
FIGURE P 2 . 1 1 7
2 . 1 1 8 Consider a Miller integrator having a time constant
of 1 ms, and whose output is initially zero, when fed with a
string of pulses of 10-//s duration and 1-V amplitude rising
fromO V (see Fig. P2.118). Sketch and label the output wave­
form resulting. How many pulses are required for an output
voltage change of 1 V?
f/(V)l
10 ,US
n nn n
FIGURE P 2 . 1 1 8
D2.119 Figure P2.119 shows a circuit that performs a low-
pass STC function. Such a circuit is known as a first-order
low-pass active filter. Derive the transfer function and
show that the dc gain is (-R /R )
2 xand the 3-dB frequency
PROBLEMS 137
C0q = 1/CR . Design the circuit to obtain an input resistance
2
of 1 kQ, a dc gain of 20 dB, and a 3-dB frequency of 4 kHz.
At what frequency does the magnitude of the transfer func­
tion reduce to unity?
V; O
FIGURE P 2 . 1 1 9
2 . 1 2 0 A Miller integrator with R = 10 kQ and C = 10 nF is
implemented using an op amp with V = 3 mV, I = 0.1 fiA,
os B
and I = 10 nA. To provide a finite dc gain, a 1-MQ resistor
os
is connected across the capacitor.
(a) To compensate for the effect of I , a resistor is connected
B
in series with the positive-input terminal of the op amp. What
should its value be?
(b) With the resistor of (a) in place, find the worst-case dc
output voltage of the integrator when the input is grounded.
2 . 1 2 1 A differentiator utilizes an ideal op amp, a 10-kQ
resistor, and a 0.01-/iF capacitor. What is the frequency f 0
(in Hz) at which its input and output sine-wave signals have
equal magnitude? What is the output signal for a 1-V peak-to-
peak sine-wave input with frequency equal to 10/ ?
0
2 . 1 2 2 An op-amp differentiator with 1-ms time constant is
driven by the rate-controlled step shown in Fig. P2.122. Assum­
ing v to be zero initially, sketch and label its waveform.
0
0 0.5 ms
FIGURE P 2 . 1 2 2
* 2 . 1 2 3 An op-amp differentiator, employing the circuit
shown in Fig. 2.44(a), has R = 10 kQ and C = 0.1 fjF. When a
triangle wave of +1-V peak amplitude at 1 kHz is applied to
the input, what form of output results? What is its frequency?
What is its peak amplitude? What is its average value? What
value of R is needed to cause the output to have a 10-V peak
amplitude? When a 1-V peak sine wave at 1 kHz is applied to
 138 ^_ CHAPTER 2 OPERATIONAL AMPLIFIERS

the (original) circuit, what output waveform is produced? 0**2.126 Derive the transfer function of the circuit in
What is its peak amplitude? Calculate this three ways: First, Fig. P2.126 (for an ideal op amp) and show that it can be
use the second formula in Fig. 2.44(a) directly; second, use written in the form
the third formula in Fig. 2.44(a); third, use the maximum 1 v
slope of the input sine wave. In each case, establish a value
V [l + ico/jcomi +j(co/ co )]
Î tjr--;- -^- z> v^ **'> ^ 4*"** «A*-^ - •
for the peak output voltage and its location. t 2
^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^
where co = 1 / C j i ^ and co = \/C R .
x 2 Assuming that
2 2

2 . 1 2 4 Using an ideal op amp, design a differentiation cir­ the circuit is designed such that > (% find approximate
3
cuit for which the time constant is 1CT s using a 10-nF expressions for the transfer function in the following fre­
capacitor. What are the gains and phase shifts found for this quency regions:
circuit at one-tenth and 10 times the unity-gain frequency? A
series input resistor is added to limit the gain magnitude at (a) co < u)]
high frequencies to 100 V/V. What is the associated 3-dB fre­ (b) co < co< co
x 2

quency? What gain and phase shift result at 10 times the

unity-gain frequency?
(c) co > co 2

C
2
Diodes
D 2 . 1 I S Figure P2.125 shows a circuit that performs the
high-pass single-time-constant function. Such a circuit is II
known as a first-order high-pass active filter. Derive the trans­
"WV
fer function and show that the high-frequency gain is
(-Rj/R^ and the 3-dB frequency co = \/CR . Design the
1

Introduction 139 3.6 Limiting and Ca l mpn ig

0 x

circuit to obtain a high-frequency input resistance of 10 kQ, a Circuits 184

high-frequency gain of 40 dB, and a 3-dB frequency of 1000 Hz. 3.1 The Ideal Do i de 140 3.7 Physical Operation of
At what frequency does the magnitude of the transfer func­ 3.2 Termn i al Characteristics of Doi des 190
tion reduce to unity? Junction Do i des 147 3.8 Special Do i de Types 209
3.3 Modeling the Do i de Forward
FIGURE P 2 . 1 2 6
Characteristic 153 3.9 The SPICE Do i de Model and
R->
WV Use these approximations to sketch a Bode plot for the mag­ 3.4 Operation in the Reverse Simulation Exampe l s 212
nitude response. Observe that the circuit performs as an
Breakdown Rego i n—Zener Summary 217
amplifier whose gain rolls off at the low-frequency end in
the manner of a high-pass STC network, and at the high-
Do i des 167 Probe l ms 218
frequency end in the manner of a low-pass STC network.
Design the circuit to provide a gain of 60 dB in the "middle
3.5 Rectifier Circuits 171
frequency range," a low-frequency 3-dB point at 100 Hz, a
high-frequency 3-dB point at 10 kHz, and an input resistance
FIGURE P 2 . 1 2 5 (at co > C0i) of 1 kfl.
INTRODUCTION
I n the p r e v i o u s chapter w e dealt almost entirely with linear circuits; any nonlinearity, such
as that i n t r o d u c e d b y amplifier output saturation, w a s considered a p r o b l e m t o b e solved b y
the circuit designer. H o w e v e r , there are m a n y other signal-processing functions that can be
i m p l e m e n t e d only b y nonlinear circuits. E x a m p l e s include the g e n e r a t i o n of dc voltages
from t h e a c p o w e r s u p p l y a n d t h e generation of signals of various w a v e f o r m s (e.g., sinuso­
ids, square w a v e s , p u l s e s , etc.). A l s o , digital logic and m e m o r y circuits constitute a special
class of n o n l i n e a r circuits.
T h e simplest and m o s t f u n d a m e n t a l nonlinear circuit e l e m e n t is t h e d i o d e . Just like a
resistor, the diode has t w o terminals; b u t unlike the resistor, which has a linear (straight-line)
relationship b e t w e e n t h e current flowing t h r o u g h it and t h e voltage appearing across it, the
d i o d e h a s a nonlinear i-v characteristic.
T h i s c h a p t e r is c o n c e r n e d w i t h t h e study of d i o d e s . In order t o u n d e r s t a n d t h e e s s e n c e of
the d i o d e function, w e b e g i n w i t h a fictitious element, the ideal diode. W e then introduce the
silicon j u n c t i o n d i o d e , explain its terminal characteristics, and p r o v i d e techniques for t h e
analysis o f d i o d e circuits. T h e latter task i n v o l v e s the i m p o r t a n t subject of device m o d e l i n g .