SC4525A

28V 3A Step-Down Switching Regulator

POWER MANAGEMENT
Features Description
 Wide input range: 8V to 28V The SC4525A is a constant frequency peak current-mode
 3A Output Current step-down switching regulator capable of producing 3A
 200kHz to 2MHz Programmable Frequency output current from an input ranging from 8V to 28V. The
 Precision 1V Feedback Voltage switching frequency of the SC4525A is programmable
 Peak Current-Mode Control up to 2MHz, allowing the use of small inductors and
 Cycle-by-Cycle Current Limiting ceramic capacitors for miniaturization, and high input/
 Hiccup Overload Protection with Frequency Foldback output conversion ratio. The SC4525A is suitable for
 Soft-Start and Enable next generation XDSL modems, high-definition TVs and
 Thermal Shutdown various point of load applications.
 Thermally Enhanced 8-pin SOIC Package
 Fully RoHS and WEEE compliant Peak current-mode PWM control employed in the
SC4525A achieves fast transient response with simple loop
compensation. Cycle-by-cycle current limiting and hiccup
overload protection reduces power dissipation during
Applications output overload. Soft-start function reduces input start-
up current and prevents the output from overshooting
 XDSL and Cable Modems
during power-up.
 Set Top Boxes
 Point of Load Applications
The SC4525A is available in SOIC-8 EDP package.
 CPE Equipment
 DSP Power Supplies
 LCD and Plasma TVs

SC4525A

Typical Application Circuit

Efficiency
90
D1
V 10V – 28V
IN
1N4148
C4 C1 80
4.7mF
BST 0.1mF VIN = 24V
IN
L1 OUT
VIN = 12V
Efficiency (%)

SW
5.2mH 5V/3A 70
R4
SS/EN SC4525A 33.2k

FB
60
COMP ROSC GND

D2 R6 C2
C7 R7 R5
20BQ030 8.25k 10mFX3
50
10nF C8 24.3k 18.2k
10pF
C5
1nF
40
0.0 0.5 1.0 1.5 2.0 2.5 3.0
L1: Coiltronics CD1-5R2 C2: Murata GRM31CR60J106K
C4: Murata GRM32ER71H475K
Load Current (A)

Figure 1. 1MHz 10V -28V to 5V/3A Step-down Converter

November 8, 2007 
Efficiency of the 1MHz 10V-28V to 5V/3A Step-Down Conve
 SC4525A

Pin Configuration Ordering Information

Device Package
SC4525ASETRT(1)(2) SOIC-8 EDP
SW 1 8 BST
SC4525AEVB Evaluation Board
IN 2 7 FB
9 Notes:
ROSC 3 6 COMP (1) Available in tape and reel only. A reel contains 2,500 devices.
GND 4 5 SS/EN
(2) Available in lead-free package only. Device is fully WEEE and RoHS
compliant.

(8 - Pin SOIC - EDP)

Marking Information

yyww=Date code (Example: 0752)

xxxxx=Semtech Lot No. (Example: E9010)


 SC4525A

Absolute Maximum Ratings Thermal Information

VIN Supply Voltage ……………………………… -0.3 to 32V Junction to Ambient (1) ……………………………… 36°C/W
BST Voltage ……………………………………………… 42V Junction to Case (1) ………………………………… 5.5°C/W

BST Voltage above SW …………………………………… 34V Maximum Junction Temperature……………………… 150°C

Storage Temperature ………………………… -65 to +150°C
SS Voltage ……………………………………………-0.3 to 3V
Lead Temperature (Soldering) 10 sec ………………… 300°C
FB Voltage …………………………………………… -0.3 to VIN
SW Voltage ………………………………………… -0.6 to VIN
Recommended Operating Conditions
SW Transient Spikes (10ns Duration)……… -2.5V to VIN +1.5V
Peak IR Reflow Temperature …………………………. 260°C Input Voltage Range ……………………………… 8V to 28V

ESD Protection Level(2) ………………………………… 2000V Maximum Output Current ……………………………… 3A

Exceeding the above specifications may result in permanent damage to the device or device malfunction. Operation outside of the parameters specified in the
Electrical Characteristics section is not recommended.
NOTES-
(1) Calculated from package in still air, mounted to 3” x 4.5”, 4 layer FR4 PCB with thermal vias under the exposed pad per JESD51 standards.
(2) Tested according to JEDEC standard JESD22-A114-B.

Electrical Characteristics
Unless otherwise noted, VIN = 12V, VBST = 15V, VSS = 2.2V, -40°C < TA = TJ < 125°C, ROSC = 12.1kΩ.

Parameter Conditions Min Typ Max Units

Input Supply
Input Voltage Range 8 28 V

VIN Start Voltage VIN Rising 2.70 2.82 2.95 V

VIN Start Hysteresis 225 mV

VIN Quiescent Current VCOMP = 0 (Not Switching) 2 2.6 mA

VIN Quiescent Current in Shutdown VSS/EN = 0, VIN = 12V 40 50 µA

Error Amplifier
Feedback Voltage 0.980 1.000 1.020 V
Feedback Voltage Line Regulation VIN = 8V to 28V 0.005 %/V
FB Pin Input Bias Current VFB = 1V, VCOMP = 0.8V -170 -340 nA
Error Amplifier Transconductance 280 µΩ-1
Error Amplifier Open-loop Gain 60 dB
COMP Pin to Switch Current Gain 12 A/V
COMP Maximum Voltage VFB = 0.9V 2.35 V

COMP Source Current VFB = 0.8V, VCOMP = 0.8V 17

µA
COMP Sink Current VFB = 1.2V, VCOMP = 0.8V 25

Internal Power Switch

Switch Current Limit (Note 1) 3.9 5.1 6.6 A

Switch Saturation Voltage ISW = -3.9A 380 600 mV


 SC4525A

Electrical Characteristics (Cont.)

Unless otherwise noted, VIN = 12V, VBST = 15V, VSS = 2.2V, -40°C < TA = TJ < 125°C, ROSC = 12.1kΩ.

Parameter Conditions Min Typ Max Units

Minimum Switch On-time 150 ns

Minimum Switch Off-time 100 150 ns

Switch Leakage Current 10 µA

Minimum Bootstrap Voltage ISW = -3.9A 1.8 2.3 V

BST Pin Current ISW = -3.9A 100 150 mA

Oscillator
ROSC = 12.1kΩ 1.04 1.3 1.56 MHz
Switching Frequency
ROSC = 93.1kΩ 240 300 360 kHz

ROSC = 12.1kΩ, VFB = 0 110 230 350

Foldback Frequency kHz
ROSC = 93.1kΩ, VFB = 0 50 110 170

Soft Start and Overload Protection

SS/EN Shutdown Threshold 0.2 0.3 0.4 V

SS/EN Switching Threshold VFB = 0 V 1.0 1.13 1.3 V

VSS/EN = 0 V 1.7
Soft-start Charging Current µA
VSS/EN = 1.5 V 1.2 2.0 2.8

Soft-start Discharging Current 1.5 µA

Hiccup Arming SS/EN Voltage VSS/EN Rising 2.15 V

Hiccup SS/EN Overload Threshold VSS/EN Falling 1.9 V

Hiccup Retry SS/EN Voltage VSS/EN Falling 0.6 1.0 1.2 V

Over Temperature Protection

Thermal Shutdown Temperature 165 °C
Thermal Shutdown Hysteresis 10 °C

Note 1: Switch current limit does not vary with duty cycle.


 SC4525A

Pin Descriptions
SO-8 Pin Name Pin Function

Emitter of the internal NPN power transistor. Connect this pin to the inductor, the freewheeling diode and the
1 SW
bootstrap capacitor.

Power supply to the regulator. It is also the collector of the internal NPN power transistor. It must be closely by-
2 IN
passed to the ground plane.

3 ROSC An external resistor from this pin to ground sets the oscillator frequency.

4 GND Ground pin

Soft-start and regulator enable pin. A capacitor from this pin to ground provides soft-start and overload hiccup
functions. Hiccup can be disabled by overcoming the internal soft-start discharging current with an external pull-
5 SS/EN
up resistor connected between the SS/EN and the IN pins. Pulling the SS/EN pin below 0.2V completely shuts off
the regulator to low current state.

The output of the internal error amplifier. The voltage at this pin controls the peak switch current. A RC compensa-
6 COMP
tion network at this pin stabilizes the regulator.

The inverting input of the error amplifier. If VFB falls below 0.8V, then the switching frequency will be reduced to
7 FB
improve short-circuit robustness (see Applications Information for details).

Supply pin to the power transistor driver. Tie to an external diode-capacitor bootstrap circuit to generate drive
8 BST
voltage higher than VIN in order to fully enhance the internal NPN power transistor.

The exposed pad serves as a thermal contact to the circuit board. It is to be soldered to the ground plane of the
9 Exposed Pad
PC board.


 SC4525A

Block Diagram
IN
2
SLOPE
COMP COMP + +
6 S ISEN
+ -

FB 4.1mW
7 - +
OC 20mV
+ EA ILIM
+ -

BST
V1 8

+
S
PWM
- Q POWER
R TRANSISTOR
FREQUENCY
FOLDBACK
CLK
ROSC OSCILLATOR
3

1.23V
1
+
A1 SW
- OVERLOAD
PWM

R
1
SS/EN
5 SOFT-START
GND
1V 1.9V AND
OVERLOAD 4
REFERENCE HICCUP
FAULT CONTROL
& THERMAL
SHUTDOWN

Figure 2. SC4525A Block Diagram

1.9V -
B4
IC + S
2mA B1 Q OVERLOAD
SS/EN
R

1V/2.15V B2

FAULT S OC
ID _
3.5mA Q
R PWM
B3

Figure 3. Soft-start and Overload Hiccup Control Circuit


ff (2) 24Vin Eff SC4525A
(3)

Typical Characteristics
SC4525A SC4525A SS270 REV 6-7

Efficiency Efficiency Feedback Voltage vs Temperature

90 90 1.02
VO=5V
85 85 V IN =12V
VO=3.3V V O=5V
80 80 1.01
VO=2.5V V O=3.3V
75 75

Efficiency (%)
Efficiency (%)

V O=2.5V
70 70 1.00

VFB (V)
65 65
V O=1.5V
60 60 0.99
55 55
VIN=24V
(5) (6)
VIN=12V
50 50 1MHz 0.98
1MHz
45 45
40 40 0.97
0 0.5 1 1.5 2 2.5 3 0 0.5 1 1.5 2 2.5 3 -50 -25 0 25 50 75 100 125
Load Current (A) Load Current (A) Temperature ( C)
o

SS270 REV 6-7 SS270 REV 6-7

Frequency Setting Resistor

vs Frequency Frequency vs Temperature Foldback Frequency vs VFB
1000 1.2 1.25
V IN =12V
R OSC=93.1k
1

Normalized Frequency
Normalized Frequency

1.1
ROSC=93.1k
100
0.75
ROSC (k)

1.0
0.5
10
R OSC=12.1k

(8) OCP current

0.9
(9) BST Pin current 0.25
R OSC=12.1k
TA =25oC

1 0.8 0
0 0.5 1 1.5 2 2.5 -50 -25 0 25 50 75 100 125 0.0 0.2 0.4 0.6 0.8 1.0
Frequency (MHz) Temperature (o C) VFB (V)

SS270 REV 6-7 SS270 REV 6-7

Switch Saturation Voltage

Switch Current Limit vs Temperature BST Pin Current vs Switch Current
vs Switch Current
500 5.0 100.0
VIN =12V
450
V BST-SW =5V
400 125oC 4.8
75.0
BST Pin Current (mA)
Current Limit (A)

350
V CESAT (mV)

4.6
300
o
-40 C 50.0 -40oC
250
4.4
200 125oC
150 25.0
4.2
25oC
100

50 4.0 0.0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 -50 -25 0 25 50 75 100 125 0 0.5 1 1.5 2 2.5 3 3.5 4
Switch Current (A) o
Temperature ( C) Switch Current (A)


 SC4525A
(11) Vin Shut down current

Typical Characteristics (Cont.)

SS270 REV 6-7 SS270 REV 6-7
SS270 REV 6-7

VIN Supply Current

VIN Thresholds vs Temperature vs Soft-Start Voltage VIN Shutdown Current vs VIN
3.0 2.5 100

VSS = 0
125oC
2.9 Start
80
2.0

-40oC
VIN Threshold (V)

2.8

Current (mA)

Current (uA)
1.5 60
2.7 -40oC
1.0 40 125oC
2.6

(14)
UVLO
0.5 20
2.5
nt (15)
2.4 0.0 0
-50 -25 0 25 50 75 100 125 0 0.5 1 1.5 2 0 5 10 15 20 25 30
Temperature (o C) V SS (V) V IN (V)

SS270 REV 6-7 SS270 REV 6-7 SS270 REV 6-7

SS Shutdown Threshold Soft-Start Charging Current

VIN Quiescent Current vs VIN vs Temperature vs Soft-Start Voltage
2.5 0.40 0.0
125oC
-0.5
2.0
-40 Co 0.35
SS Threshold (V)

-1.0
Current (uA) 125oC
Current (mA)

1.5 -40oC
0.30 -1.5
1.0
-2.0
0.25
0.5 -2.5
V COMP = 0

0.0 0.20 -3.0

0 5 10 15 20 25 30 -50 -25 0 25 50 75 100 125 0 0.5 1 1.5 2
o V SS (V)
VIN (V) Temperature ( C)


 SC4525A

Applications Information
Operation When the SS/EN pin is released, the soft-start capacitor
is charged with an internal 1.6µA current source (not
The SC4525A is a constant-frequency, peak current- shown in Figure 3). As the SS/EN voltage exceeds 0.4V,
mode, step-down switching regulator with an integrated the internal bias circuit of the SC4525A turns on and the
28V, 3.6A power NPN transistor. Programmable switching SC4525A draws 2mA from VIN. The 1.6µA charging current
frequency makes the regulator design more flexible. With turns off and the 2µA current source IC in Figure 3 slowly
the peak current-mode control, the double reactive poles charges the soft-start capacitor.
of the output LC filter are reduced to a single real pole by
the inner current loop. This simplifies loop compensation The error amplifier EA in Figure 2 has two non-inverting
and achieves fast transient response with a simple Type-2 inputs. The non-inverting input with the lower voltage
compensation network. predominates. One of the non-inverting inputs is biased
to a precision 1V reference and the other non-inverting
As shown in Figure 2, the switch collector current is input is tied to the output of the amplifier A1. Amplifier A1
sensed with an integrated 4.1mW sense resistor. The produces an output V1 = 2(VSS/EN -1.23V). V1 is zero and COMP
sensed current is summed with a slope-compensating is forced low when VSS/EN is below 1.23V. During start up,
ramp before it is compared with the transconductance the effective non-inverting input of EA stays at zero until
error amplifier (EA) output. The PWM comparator trip the soft-start capacitor is charged above 1.23V. Once VSS/EN
point determines the switch turn-on pulse width. The exceeds 1.23V, COMP is released. The regulator starts to
current-limit comparator ILIM turns off the power switch switch when VCOMP rises above 0.4V. If the soft-start interval
when the sensed signal exceeds the 20mV current-limit is made sufficiently long, then the FB voltage (hence the
threshold. output voltage) will track V1 during start up. VSS/EN must be
at least 1.83V for the output to achieve regulation. Proper
Driving the base of the power transistor above the soft-start prevents output overshoot. Current drawn from
input power supply rail minimizes the power transistor the input supply is also well controlled.
saturation voltage and maximizes efficiency. An external
bootstrap circuit (formed by the capacitor C1 and the Overload / Short-Circuit Protection
diode D1 in Figure 1) generates such a voltage at the BST
pin for driving the power transistor. Table 2 lists various fault conditions and their
corresponding protection schemes in the SC4525A.
Shutdown and Soft-Start
Condition Fault Protective Action
Table 2: Fault conditions and protections
Cycle-by-cycle limit at
The SS/EN pin is a multiple-function pin. An external IL>ILimit, VFB>0.8V Over current
Condition Fault Protective Action frequency
programmed
capacitor (4.7nF to 22nF) connected from the SS pin to Cycle-by-cycle limit at limit with
Cycle-by-cycle
IL>ILimit,IL>ILimit,
VFB>0.8V Over current
VFB<0.8V Over current
ground sets the soft-start and overload shutoff times of programmed frequency
frequency foldback
Cycle-by-cycle limit with
the regulator (Figure 3). The effect of VSS/EN on the SC4525A VSS/EN Falling
IL>ILimit, VFB<0.8V
Persistent over current
Over current
Shutdown, then retry

is summarized in Table 1. SS/EN<1.9V or short circuit frequency foldback

(Hiccup)
VSS/EN Falling Persistent over current Shutdown, then retry
Tj>160C Over temperature Shutdown
SS/EN<1.9V or short circuit (Hiccup)
Table 1: SS/EN operation modes
Tj>160C Over temperature Shutdown
SS/EN Mode Supply Current
<0.2V Shutdown 18uA @ 5Vin
SS/EN
0.4V to 1.23V ModeNot switching Supply Current
2mA As summarized in Table 1, overload shutdown is disabled
<0.2V
1.23V to 2.1V Shutdown& hiccup disabled
Switching 18uA @ 5Vin
Load dependent
during soft-start (VSS/EN<2.1V). In Figure 3, the reset input of
0.4V to 1.23V
>2.1V Not switching
Switching & hiccup armed 2mA the overload latch B2 will remain high if the SS/EN voltage
1.23V to 2.1V Switching & hiccup disabled
Load dependent is below 2.1V. Once the soft-start capacitor is charged
>2.1V Switching & hiccup armed
Pulling the SS/EN pin below 0.2V shuts off the regulator above 2.1V, the output of the Schmitt trigger B1 goes high,
and reduces the input supply current to 18µA (VIN = 5V). the reset input of B2 goes low and hiccup becomes armed.


 SC4525A

AC =
Applications Information (Cont.)
 V 
R4 = R6  O − 1 
As the load draws more current from the regulator, the down switching
 1.0 Vregulator
 in continuous-conduction
current-limit comparator ILIM (Figure 2) will eventually mode (CCM) is given by AC =
limit the switch current on a cycle-by-cycle basis. The VO + VD
over-current signal OC goes high, setting the latch B3. The D=
(2)
VIN + VD − VCESAT
soft-start capacitor is discharged with (ID - IC) (Figure 3). If
the inductor current falls below the current limit and the where VIN is the input voltage, VCESAT is the switch saturation R7 =
PWM comparator instead turns off the switch, then latch voltage, and VD is voltage drop across the rectifying
B3 will be reset and IC will recharge the soft-start capacitor. diode. DI = ( VO + VD ) ⋅ (1 − D) C5 =
L
If over-current condition persists or OC becomes asserted FSW ⋅ L 1
more often than PWM over a period of time, then the In peak current-mode control, the PWM modulating
soft-start capacitor will be discharged below 1.9V. At this ramp is the( Vsensed
+ VD ) ⋅ current
(1 − D) ramp of the power switch. C8 =
L1 = O
juncture, comparator B4 sets the overload latch B2. The This current ramp
20% ⋅ IO ⋅absent
is FSW unless the switch is turned
soft-start capacitor will be continuously discharged with on. The intersection of this ramp with the output of the
(ID - IC). The COMP pin is immediately pulled to ground. The voltage feedback error amplifier determines the switch Vo
switching regulator is shut off until the soft-start capacitor pulse Iwidth. The propagation delay time required to =
RMS _ CIN = I O ⋅ D ⋅ (1 − D) Vc
is discharged below 1.0V. At this moment, the overload immediately turn off the switch after it is turned on is the
latch is reset. The soft-start capacitor is recharged and minimum controllable switch on time (TON(MIN)).
the converter again undergoes soft-start. The regulator
 1  that the SC4525A GPWM
Fig. 4
will go through soft-start, overload shutdown and restartClosed-loop
DVO = Dmeasurement
IL ⋅  ESR + shows
8 ⋅ F130ns

until it is no longer overloaded. minimum on time  is about SW ⋅ C Oat room temperature
(Figure 4). If the required switch on time is shorter than
If the FB voltage falls below 0.8V because of output the minimum on time, the regulator will either skip cycles R7 =
overload, then the switching frequency will be reduced. or it will jitter.
SS270 REV 6-7
Frequency foldback helps to limit the inductor current IO
C IN > C5 =
when the output is hard shorted to ground. 4 ⋅ DVIN ⋅ FSW
Minimum On Time vs Temperature
200
During normal operation, the soft-start capacitor is 190 V O =1.5V
C8 =
charged to 2.4V. 180 1MHz
170
Setting the Output Voltage
TON(MIN) (ns)

160
150
The regulator output voltage, VO, is set with an external 140
resistive divider (Figure 1) with its center tap tied to the FB  1
130
1 V 
pin. For a given R6 value, R4 can be found by ⋅ log
A C = − 20120 ⋅ ⋅ FB 
G R 2πFC C O VO 
110  CA S
V
R4 = R6  O − 1 
(1) 100
 1.0 V  -50 -25 01 25 50 1
75 100 125 1.0 
A C = − 20 ⋅ log Temperature
−3
⋅ (o C) 3 −6
⋅  = 15
 28 ⋅ 6.1 ⋅ 10 2π ⋅ 80 ⋅ 10 ⋅ 22 ⋅ 10 3 .3 
SettingDthe VO + VD Frequency
= Switching
VIN + VD − VCESAT Figure
15.9 4. Variation of Minimum On Time
10 20
The switching frequency of the SC4525A is set with an R7 = =with
22.3Ambient
k Temperature
external resistor from the ROSC pin to ground. 0.28 ⋅ 10 −3
( VO + VD ) ⋅ (1 − D) To allow for transient
1 headroom, the minimum operating
DIL =On Time C5 = = 0.45nF
Minimum FSWConsideration
⋅ L1 switch2π ⋅ 16 ⋅ 10 ⋅ 22.1be⋅ 10
on time should
3 at 3least 20% to 30% higher than
the worst-case minimum on time.
The operating duty cycle of a non-synchronous step- 1
( V + VD ) ⋅ (1 − D) C8 = = 12pF
L1 = O 2 π⋅ 600 ⋅ 10 3 ⋅ 22.1 ⋅ 10 3
20% ⋅ IO ⋅ FSW 10
 L1 = O D
20% ⋅ IO ⋅ FSW
SC4525A Vo
=
IRMS _ CIN = IO ⋅ D ⋅ (1 − D) Vc

Applications Information (Cont.)

 1  GPWM
Minimum Off Time Limitation The input = DIL ⋅  ESRmust
DVOcapacitance + 
also be high enough to keep
 8 ⋅ FSW ⋅ C O 
input ripple voltage within specification. This is important
The PWM latch in Figure 2 is reset every cycle by the in reducing the conductive EMI from the regulator. The
R7 =
clock. The clock also turns off the power transistor to input capacitance can be estimated from AC =
refresh the bootstrap capacitor. This minimum off time
V IO
limits the attainable duty cycle of the regulator at a given RC4IN=>R6  O − 1  (6) C5 =
4⋅1D.V 0INV ⋅ FSW
switching frequency. The measured minimum off time is AC =
 1inputVripple 
100ns typically. If the required duty cycle is higher than Awhere DV is the 1
C = − 20 ⋅INlog 
allowable⋅ ⋅ FB  voltage.
the attainable maximum, then the output voltage will not V GOCA+RVSD 2πFC C O VO  C8 =
 VOits set value in continuous-conduction D=
be able
R4 to
= Rreach
6 −1 Multi-layerVceramic IN + VD − VCESAT
capacitors, which have very low ESR
mode.  1.0 V  (a few mW) and can easily 1 handle high RMS1 ripple current, 1.0 
A C = − 20 ⋅ log −3
⋅ 3 −6
⋅ R=715
=
are the ideal choice 28 ⋅ 6.1for ⋅ 10input2πfiltering.
⋅ 80 ⋅ 10 A ⋅ single
22 ⋅ 10 4.7µF 3.3 
VO + VD
Inductor Selection X5R ceramic( Vcapacitor is adequate for 500kHz or higher
D= O + VD ) ⋅ (1 − D)
VIN + VD − VCESAT switching DIL =frequency applications, and 10µF is adequate C 5 =
15.9 FSW ⋅ L 1
The inductor ripple current for a non-synchronous step- for 200kHz 10 20 to  = 500kHz switching V frequency.
 For high
R7 = 122.3k 1
down converter in continuous-conduction mode is C =0
Avoltage −.28 log−3
⋅⋅ 10
20applications, a⋅ small ceramic ⋅ FB (1µF or 2.2µF) can be
( VO G +CA R 2πDF)C C O VO  C8 =
placedLin parallel D )S⋅ (1a−low
Vwith ESR electrolytic capacitor to
(V V + V ) ⋅ (1 − D) = 1
RD4IL==R6 O O D − 1 
1
(3) 5 =
Csatisfy both the 203ESR% ⋅ IOand ⋅ FSWbulk = 0.45nF
3 capacitance requirements.
 1.0 V ⋅ L 1
FSW 2π ⋅ 16 ⋅ 10 ⋅ 22 .11 ⋅ 10 1 1.0 
A C = − 20 ⋅ log ⋅ ⋅  = 15
where FSW is the switching frequency and L1 is the Output Capacitor  128 ⋅ 6 . 1 ⋅ 10 −3
2 π ⋅ 80 ⋅ 10 3
⋅ 22 ⋅ 10 −6
3.3  Vo
C8 = I =
inductance. ( V V+ V+ )V⋅ (1 − D) 2 πRMS
⋅ 600 _ CIN⋅ 10= IO3 ⋅⋅ 22 D.⋅1(1⋅ 10− D3) = 12pF Vc
LD1== O O D D
VIN 20 + V%D ⋅−IOV⋅CESAT
FSW The output15.9ripple voltage DVO of a buck converter can be
An inductor ripple current between 20% to 50% of the 10 20as
Rexpressed
7 = = 22.3k
− 3 (1 + sR
maximum load current, IO, gives a good compromise Vo 0.28 ⋅ 10 GPWM ESR C O ) GPWM
=  21 2 
amongIRMS ( VO= I+O Vcost
efficiency,
_ CIN ⋅ )D⋅ (and
⋅1(1−−DD) ) Re-arranging Equation (3)
size. V
c ( 1 D
+ VsO / =ω D )I(1
p L1  ⋅ + ESR
s / ω +n Q + s
8 ⋅3FSW
/ ω n )  (7)
DI = D C5 = 3 
= 0⋅.C 45 O nF

and assuming
L 35% FSWinductor
⋅ L1 ripple current, the inductor is 2π ⋅ 16 ⋅ 10 ⋅ 22.1 ⋅ 10
given by where CO is the output capacitance.
R 1 1V  1 R7 =
( V + V D ) ⋅ (1 − D) 1  G
CAPWM8 =−
= ≈ 20 ⋅ log, 31 ⋅ ωp1≈ 3 =⋅ 12 ,FBpF  ωZ = ,
Since2 πG ⋅CA600 ⋅R S⋅10 ⋅ 22.2 RC O V DI increases
1π⋅ F10Ccurrent R ESRasC OD
C
LD1VO= = DOIL ⋅  ESR +  (4) the  G CAIOR S ripple
inductor O  L
35V% ⋅ IO ⋅ FSW8 ⋅ FSW ⋅ C O  C O
C IN >(Equation (3)), the output ripple voltage is C 5 =
R4 = R6   O
−1  decreases AC
4 ⋅ DVIN ⋅ FSW
 1.0 V varies
If the input voltage  over a wide range, then choose therefore
10 20 the highest 1when VIN is at its maximum. 1 1.0 
RAV7oC = − 20 ⋅ log GPWM  (1 + sRESR C−O3) ⋅ ⋅  = 15
L1 based on the nominal input voltage. Always verify = gm 28 ⋅ 6.1 ⋅ 10 2 2π ⋅280 ⋅ 10 ⋅ 22 ⋅ 10 3 −6
ωp)(1X5R / ωn ) is found adequate C 8 =
IRMS _ CIN = IO ⋅ D ⋅ (1 − D) 3 .3
converter operation VAc 22µF(1 +to s /47µF + s ceramic
/ ωn Q + scapacitor
VO I+ VDat the input voltage extremes. 1
CD => O
Cfor output filtering in most applications. Ripple current
IN V + V − V 5 =
4 ⋅ DVDIN ⋅ FCESAT
IN 2 πFoutput R.97 capacitor is not a concern because the
The peak current limitSWof SC4525A power transistor is at in the
15
Z1 20
10 R 1 1
least 3.6A. The maximum  deliverable  load current for the G 7 = ≈
Rinductor current −,3
= of 22a.3kbuck ωp ≈ converter , ωZ =feeds C ,,
directly
1 PWM
0 . 28 1 ⋅
GCA ⋅ RS10 RC O R ESRC OO
D V = D I ⋅ 
SC4525A is 3.6A minus one
O L ESR + half of the inductor ripple 8 =
Cresulting in very low ripple current. Avoid using Z5U
 8
( V + VD ) ⋅ (1 − D)⋅ FSW ⋅ C O  2 πFP1 R7 1
current.DIL = O Cand5 = Y5V A C ceramic 3
capacitors 3
=
for 0 .45
output nF filtering because
FSW ⋅ L 1 2π
10 ⋅ 16 ⋅of
20 10capacitors⋅ 22.1 ⋅ 10
Rthese
7 = types have high temperature and high
Input Decoupling Capacitor voltage g m coefficients. 1
( V + V ) ⋅ (1 − D) C8 = = 12pF
LC1 => O IOD 2 π⋅ 600 ⋅ 10 3 ⋅ 22.1 ⋅ 10 3
1
The input VIN⋅ IO⋅should
IN capacitor
420
⋅ D% F⋅ FSWSW be chosen to handle the RMS CFreewheeling
5 =
Diode
ripple current of a buck converter. This value is given by 2 πFZ1 R7
VUse of Schottky G (1 + sR diodes C O ) as freewheeling rectifiers
o
== 1 PWM barrierESR
IRMS _ CIN = IO ⋅ D ⋅ (1 − D)
(5) CVreduces
8 (21π+Fsdiode/ ωp )(1reverse + s / ωn Q recovery
+ s 2 / ωn2input) current spikes,
P1 R 7
c
easing high-side current sensing in the SC4525A. These

R 1 1 11
 1  GPWM ≈ , ωp ≈ , ωZ = ,
DV = DI ⋅  ESR +  GCA ⋅ RS RC O R ESRC O
 Fig 5 SC4525A

Applications Information (Cont.) SS270 REV 6-7

diodes should have an average forward current rating Minimum Bootstrap Voltage
at least 3A and a reverse blocking voltage of at least a vs Temperature
2.2
few volts higher than the input voltage. For switching
regulators operating at low duty cycles (i.e. low output 2.1
voltage to input voltage conversion ratios), it is beneficial
2.0
to use freewheeling diodes with somewhat higher

Voltage (V)
average current ratings (thus lower forward voltages). This 1.9
is because the diode conduction interval is much longer
than that of the transistor. Converter efficiency will be 1.8

improved if the voltage drop across the diode is lower. ISW =-3.9A
1.7

The freewheeling diode should be placed close to the 1.6

SW pin of the SC4525A to minimize ringing due to trace -50 -25 0 25 50 75 100 125
Temperature (o C)
inductance. 20BQ030 (International Rectifier), B320A,
B330A (Diodes Inc.), SS33 (Vishay), CMSH3-20MA and Figure 5. Typical Minimum Bootstrap Voltage required
CMSH3-40MA (Central-Semi.) are all suitable. to Saturate Transistor (ISW= -3.9A)
D1 D3

The freewheeling diode should be placed close to the SW

pin of the SC4525A on the PCB to minimize ringing due to BST C1

trace inductance. VIN VOUT VIN

IN SW

Bootstrapping the Power Transistor SC4525A

D
2
GND

The minimum BST-SW voltage required to fully saturate

the power transistor is shown in Figure 4, which is about (a)
1.98V at room temperature.
D1 D3 D1

The BST-SW voltage is supplied by a bootstrap circuit

BST C1 BST C1
powered from either the input or the output of the
converter (Figure 5).
VIN To maximize efficiency, tie the VOUT
SW
VIN
SW
VOUT
IN IN
bootstrap diode to the converter output if VO>2.5V.
SC4525A SC4525A
Since the bootstrap supply currentGND
is proportional
D
2 to the GND
D
2

converter load current (Equation (10), page 14), using a

lower voltage to power the bootstrap circuit reduces
driving loss and improves efficiency. (a) (b)

Figure 6. Methods of Bootstrapping the SC4525A

For the bootstrap circuit, a fast switching PN diode (such
as 1N4148 or 1N914) and a small (0.1µF – 0.47µF) ceramic
capacitor is sufficient for most applications. When
bootstrapping from 2.5V to 3.0V output voltages, use a
low forward drop Schottky diode (BAT-54 or similar) for
D1. When bootstrapping from high input voltages (>20V),
reduce the maximum BST voltage by connecting a Zener
diode (D3) in series with D1.
Loop Compensation
The goal of compensation is to shape the frequency
response of the converter so as to achieve high DC
accuracy and fast transient response while maintaining
loop stability.

12
 SC4525A

Applications Information (Cont.)

CONTROLLER AND SCHOTTKY DIODE

Io Including the voltage divider (R4 and R6), the control to

Rs
feedback transfer function is found and plotted in Figure
CA

REF
8 as the converter gain.
+
Vc PWM
EA
MODULATOR
FB -
Vramp SW
L1 Vo Since the converter gain has only one dominant pole at
low frequency, a simple Type-2 compensation network
COMP

Co
R4
is sufficient for voltage loop compensation. As shown in
C5

C8
Figure 8, the voltage compensator has a low frequency
R7 Resr
R6 integrator pole, a zero at FZ1, and a high frequency pole
at FP1. The integrator is used to boost the gain at low
frequency. The zero is introduced to compensate the
excessive phase lag at the loop gain crossover due to the
Figure 7. Block diagram of control loops integrator pole (-90deg) and the dominant pole (-90deg).
The high frequency pole nulls the ESR zero and attenuates
AC ==diagram
− 20
20 ⋅⋅ log
log  1 1
⋅shows
1
1 VFB 
⋅V FB 
The block
A − in  Figure
 G 7 ⋅ the⋅  loops of a
control high frequency noise.
C G CA R
RS 2 2π πFFC CCO V VO 
buck converter with the SC4525A. The innerloop (current
 CA S C O O

loop) consists of a current sensing resistor (Rs=4.1mW)

1 gain (G =28). The 1 outer 1..0
060
VFB  and a current
AC =
A =− 20 log (CA) with
amplifier
− 20 ⋅⋅ log
1
− 3
⋅ CA
⋅
1
−6
1
⋅⋅ 3.3  =
= 15
15..9
9dB
dB
⋅  loop (voltage loop) consists
C 28 ⋅⋅ 6
 28 1of⋅⋅ 10
6..1 10 2π
an− 3error
2 π amplifier
⋅⋅ 80 10 33 (EA),
80 ⋅⋅ 10 ⋅⋅ 22
22 ⋅⋅ 10
a10 −6 3.3 
O VO 
PWM modulator, and a LC filter. 30 Fz1 Fp1
CO
15.9 MP
EN
1 10 loop1.0 internally closed, the remaining
15
20.9 SA

⋅  −3is=
TO
10
GAIN (dB)

⋅  1Since3 the =current

RG
20
R71= V 15
22.9 3dB
k AIN
2π⋅ 80task
⋅ log
R
⋅ 10⋅for
⋅ 22
7 ⋅ 10
the00loop − 6
⋅ ⋅⋅ 10
..28
28 FB
3.3−3 = 22.3k is to design the voltage
10
compensation
0 Fp
R S 2πFC C O VO 
LO
Fc OP
 G CAcompensator
CO GA
NV IN
ER
(C5, R7, and 1 C8).
1
TER
C5 =
C = 3
=0
= 0..45
45nF nF GA
IN
5 2π
2 π ⋅⋅ 16
16 ⋅⋅ 10
10 3 ⋅⋅ 22 22..1 10 33
1 ⋅⋅ 10 -30
1 1 1.0  F , output
⋅ log For a converter ⋅ with switching frequency
⋅  = 15SW.9dB
Fz Fsw/2
⋅ 6.1 ⋅ 10
 28inductance −3
2, πoutput
⋅ 80 ⋅ 10 13
1 ⋅ 22 ⋅ 10 C =3 −6
3 pF
.12
C =
C 88 = 1 L capacitance
3
and
3O = 12pF
loading R, the
2
2 π
π ⋅
⋅ 600
600 ⋅
⋅ 10
10 3 ⋅
⋅ 22
22 .
.11 ⋅
⋅ 10
10
control (VC) to output (VO) transfer function in Figure 7 is
3 -60
1K 10K 100K 1M 10M
= 0.45nF
15.9 given by: FREQUENCY (Hz)
0 20
= 22.3kV GPWM ((1 1+ + ssRRESR C C O ))
⋅ 10 −3
Voo = G (8) Figure 8. Bode plots for voltage loop design
= 12 pF = PWM ESR O
3 Vc ((1
V 1+ + ss // ωωp ))((1
1+ + ss // ω
ωn Q Q+ + ss22 // ω
ωn22 ))
1 c p n n
= 0.45nF
16 ⋅ 10 3 ⋅This22.1transfer
⋅ 10 3 function has a finite DC gain Therefore, the procedure of the voltage loop design for
R 1 1 the SC4525A can be summarized as:
1 GPWM ≈
G ≈= 12RpF ,, ω ≈ 1 ,,
ωp ≈ = 1 ,,
ωZ =
ω
2
/ω 2 3 PWM
⋅ 22.1 ⋅ 10 3 GGCA ⋅⋅ R
RS p RC
R CO Z R ESRC
R CO
600 n)
⋅ 10 CA S O ESR (1)
O Plot the converter gain, i.e. control to feedback transfer

an ESR zero FZ at AC
AC
function.
10 20
10
20
(2) Select the open loop crossover frequency, FC, between
1GPWM (1 + sRESRR7C=
R =) 1
, ω7Z =O g m , 10% and 20% of the switching frequency. At FC, find the
R/CωOp )(1 + s / ωn Q + sR2gESR
/mωCn2O)
1 required compensator gain, AC. In typical applications with
C5 = 1
= low-frequency
C
a dominant
5 2π πFFZ1 R R7 pole FP at ceramic output capacitors, the ESR zero is neglected and
2
R 1
Z1 7
1 the required compensator gain at FC can be estimated by
, ωp ≈ 11, ωZ = ,
A ⋅ R S C = R C
C 88 = 2 πOF R R ESRC O  1 1 V 
2 πFPP11 R77 A C = − 20 ⋅ log
⋅ ⋅ FB  (9)
and double poles at half the switching frequency.  G CA R S 2πFC C O VO 
V
R4 = R6  O − 1 
 1.0 V  1 1 1.0
A C = − 20 ⋅ log
13
−3
⋅ 3 −6
⋅
 28 ⋅ 6.1 ⋅ 10 2π ⋅ 80 ⋅ 10 ⋅ 22 ⋅ 10 3.
 1
C5 = = 0.45nF
2π ⋅ 16 ⋅ 10 ⋅ 22.1 ⋅ 10 3
3
SC4525A
1
C8 = = 12pF
2 π⋅ 600 ⋅ 10 3 ⋅ 22.1 ⋅ 10 3

Applications Information (Cont.)

Vo GPWM (1 + sRESR C O )
(3) Place =the compensator zero, FZ1,2between 10% and Thermal Considerations
Vc (1 + s / ωp )(1 + s / ωn Q + s / ωn2 )
20% of the crossover frequency, FC.
(4) Use the compensator pole, FP1, to cancel the ESR zero, For the power transistor inside the SC4525A, the
FZ. R 1 1 conduction loss PC, the switching loss PSW, and bootstrap
G ≈ , ω ≈ , ωZ = ,
(5) Then,PWM
the parameters
GCA ⋅ RS of the pcompensation
RC O networkR ESRCcircuit
O
Ploss = Pcan
PBST,
TOTAL C +P
be + PBST + Pas
SWestimated Q follows:
can be calculated by
PQ = VIN ⋅ 2mA
AC
10 20 PC = D ⋅ VCESAT ⋅ IO
R7 =
gm
1
1 PSW = ⋅ t S ⋅ VIN ⋅ I O ⋅ FSW (10)
C5 = 2
2 πFZ1 R7
IO
1 PBST = D ⋅ VBST ⋅
C8 = 40
2 πFP1 R7
where gm=0.28mA/V is the EA gain of the SC4525A. where PVBST=is(1the
− DBST
) ⋅ Vsupply voltage and tS is the equivalent
D D ⋅ IO
switching time of the NPN transistor (see Table 4).
Example: Determine the voltage compensator for an
800kHz, 12V to 3.3V/3A converter with 47uF ceramic PTable
IND = (4.
1.1Typical ⋅ I2O ⋅ R DC time
~ 1.3)switching
output capacitor. Load Current
Input Voltage
1A 2A 3A
Choose a loop gain crossover frequency of 80kHz, and 12V 12.5ns 15.3ns 18ns
24V 22ns 25ns 28ns
place voltage compensator  1 zero 1and pole VFB at FZ1=16kHz 28V 25.3ns 28ns 31ns
A C F= ),− 20 ⋅ log  =600kHz. ⋅ ⋅Equation
(20% of and
1 F  1G RVFB  2πFrom FC C O VO   (9), the
A C = − 20 ⋅ log
C ⋅  CA ⋅ S 
P1
required compensator
 G CA R S 2πFCgain C O Vat O F is
C
PTOTAL = PC + PSW + PBST +InPaddition, the quiescent current loss is
 1  1 1 1.0  1 1Q.0 
A C = −A20C ⋅=
log− 20 ⋅ log  −3 ⋅ 3− 3 ⋅ −6
⋅  = 319dB ⋅  = 19 dB
 28 ⋅ 4.1 ⋅ 10  28 2⋅ π4⋅.1 80⋅⋅10
10 ⋅ 47 2 ⋅ 10
π ⋅ 803.⋅310 ⋅ 47 ⋅ 10 −6 3.3  (11)
PC = D ⋅ VCESAT ⋅ IO PQ = VIN ⋅ 2mA
Then the compensator parameters are
19
10 20

R7 = = 31.198k 1 The total power loss of the SC4525A is therefore

0.28 ⋅ 10 − 3 10 20 PSW = ⋅ t S ⋅ VIN ⋅ I O ⋅ FSW
R7 = 1 = 31 . 8 k 2
C5 = 0.28 ⋅ 10 − 3 = 0.31nF PTOTAL = PC + PSW + PBST + PQ (12)
2π ⋅ 16 ⋅ 10 3 ⋅ 31.4 ⋅ 10 3
1 IO
C8 =
C5 = 1 3 = 8.5pF 3
=P0 .31
BST =nF
D ⋅ VBST ⋅
2 π⋅ 600 2⋅ 10π 3⋅ 16
⋅ 31.⋅410⋅ 10 3 ⋅ 31 .4 ⋅ 10 40 The temperature rise⋅ of
PC = D ⋅ VCESAT IO the SC4525A PisQthe = Vproduct
IN ⋅ 2mA of the
total power dissipation (Equation (12)) and qJA (36oC/W),
1
C 8 =G (1 + sR C )3 = 8.5pF which is the thermal impedance from junction to ambient
Vo
2 π⋅ 600ESR⋅ 10 ⋅ 31 .4 ⋅ 10 3 PD = (1 − D) ⋅ VD ⋅ IO SW =
1
⋅ t S ⋅package.
VIN ⋅ I O ⋅ FSW
for thePSOIC-8
PWM O
=
Vc (1 + s / ωp )(1 + s / ωn Q + s / ωn ) 2 2
2 EDP
Select R7=31.4k, C5=0.33nF, and C8=10pF for the design.
1+ sR C ) PIND 1= (1.1 ~ 1.3) ⋅ IO ⋅ R DC
2
It is not I
GPWM ≈ oV R
, G ωp ≈
PWM (1 , ESR OωZ = , PBSTrecommended
= D ⋅ VBST ⋅ O to operate the SC4525A above
G =⋅ R parameters
Compensator RCfor various typical R ESR2C O applications 125oC junction temperature. 40 In the applications with high
VcCA (S1 + s / ωp )(1 + Os / ωn Q + s 2 / ω n)
are listed in Table 5. A MathCAD program is also available
AC
input voltage and high output current, the switching
10
upon
R 7 = request for detailed calculation of the compensator frequencyPD =may need
) ⋅ VD to
⋅ IObe reduced to meet the thermal
20

gm
(1 − D
parameters. R 1 1 requirement.
GPWM
1
≈ , ωp ≈ , ωZ = ,
C5 = GCA ⋅ RS RC O R ESRC O
2 πFZ 1 R7 PIND = (1.1 ~ 1.3) ⋅ I2O ⋅ R DC
1 AC
C8 =
πFP1=R 710
20
2R
7
gm
14
1
C5 =
 SC4525A

Applications Information (Cont.)

PCB Layout Considerations

In a step-down switching regulator, the input bypass

capacitor, the main power switch and the freewheeling
diode carry pulse current (Figure 9). For jitter-free
operation, the size of the loop formed by these components
should be minimized. Since the power switch is already
integrated within the SC4525A, connecting the anode of
the freewheeling diode close to the negative terminal of
the input bypass capacitor minimizes size of the switched
current loop. The input bypass capacitor should be placed
close to the IN pin. Shortening the traces of the SW and
BST nodes reduces the parasitic trace inductance at these
nodes. This not only reduces EMI but also decreases
switching voltage spikes at these nodes.

The exposed pad should be soldered to a large ground

plane as the ground copper acts as a heat sink for the
device. To ensure proper adhesion to the ground plane,
avoid using vias directly under the device.

V IN

VOUT

ZL

Figure 9. Heavy lines indicate the critical pulse

current loop. The inductance of this
loop should be minimized.

Curre nts in Power Section

Vin

15
 SC4525A

Recommended Component Parameters in Typical Applications

Table 5 lists the recommended inductance (L1) and compensation network (R7, C5, C8) for common input and output
voltages. The inductance is determined by assuming that the ripple current is 35% of load current IO. The compensator
parameters are calculated by assuming a 47mF low ESR ceramic output capacitor and a loop gain crossover frequency
of FSW/10.

Table 5. Recommended inductance (L1) and compensator (R7, C5, C8)

Typical Applications Recommended Parameters
Vin(V) Vo(V) Io(A) Fsw(kHz) C2(uF) L1(uH) R7(k) C5(nF) C8(pF)
1.5 500 3.3 10 2.2
500 4.7 16.2 2.2
2.5
1000 2.2 29.4 0.47
500 6.8 23.2 2.2
3.3
1000 3.3 39.2 0.47
12 3 500 47 6.8 29.4 2.2 10
5
1000 3.3 69.8 0.47
500 6.8 43.2 2.2
7.5
1000 3.3 90.9 0.47
500 3.3 69.8 2.2
10
1000 2.2 133 0.47
1.5 300 6.8 6.81 2.2
500 6.8 12.4 2.2
2.5
1000 2.2 29.4 0.47
500 6.8 23.2 2.2
3.3
1000 3.3 43.2 0.47
24 3 500 47 8.2 29.4 2.2 10
5
1000 4.7 59 0.47
500 10 49.9 2.2
7.5
1000 4.7 100 0.47
500 15 59 2.2
10
1000 6.8 133 0.47

16
 SC4525A

Typical Application Schematics

D3 D1
V 24V
IN
18V Zener 1N4148
C4 C1
4.7mF 0.33mF
IN BST
L1 OUT
SW
6.8mH 1.5V/3A
R4
SS/EN SC4525A 33.2k

FB

COMP ROSC GND

D2 R6 C2
C7 R7 R5
10nF 90.9k B330A 66.5k 47mF
C8 6.81k
22pF
C5
2.2nF

L1: Coiltronics DR74-6R8 C2: Murata GRM31CR60J476M

C4: Murata GRM32ER71H475K

Figure 10. 300kHz 24V to 1.5V/3A Step-down Converter

EVB#d: 300kHz 24V to 1.5V/3A Step-Down Converter

D1
V 10V – 26V
IN
1N4148
C4 C1
4.7mF 0.1mF
IN BST
L1 OUT
SW
3.3mH 3.3V/3A
R4
SS/EN SC4525A 33.2k

FB

COMP ROSC GND

D2 R6 C2
C7 R7 R5
10nF 18.2k B330A 14.3k 47mF
C8 43.2k
10pF
C5
0.47nF

L1: Coiltronics DR74-3R3 C2: Murata GRM31CR60J476M

C4: Murata GRM32ER71H475K

Figure 11. 1MHz 10V-26V to 3.3V/3A Step-down Converter

1MHz 10V-26V to 3.3V/3A Step-Down Converter

17
 SC4525A
SS
Typical Performance Characteristics
(For A 12V to 5V/3A Step-down Converter with 1MHz Switching Frequency)
SS270 REV 6-7

Load Characteristic
6

12V Input (5V/DIV)

Output Voltage (V)

3
5V Output (2V/DIV)
2

1 SS Voltage (1V/DIV)

0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5
10ms/DIV
Load Current (A)

Figure 12(a). Load Characteristic Figure 12(b). VIN Start up Transient (IO=3A)
OCP

5V Output Short (5V/DIV)

5V Output Response (500mV/DIV, AC Coupling)

Inductor Current (1A/DIV)

Retry Inductor Current (2A/DIV)

SS Voltage (2V/DIV)

40us/DIV 20ms/DIV

Figure 12(c). Load Transient Response Figure 12(d). Output Short Circuit (Hiccup)
(IO= 0.3A to 3A)

18
 SC4525A
SO-8 EDP2 Outline
Outline Drawing - SOIC-8 EDP

A
e D DIMENSIONS
N INCHES MILLIMETERS
DIM
MIN NOM MAX MIN NOM MAX
A .053 - .069 1.35 - 1.75
2X E/2
A1 .000 - .005 0.00 - 0.13
A2 .049 - .065 1.25 - 1.65
E1 E
b .012 - .020 0.31 - 0.51
c .007 - .010 0.17 - 0.25
D .189 .193 .197 4.80 4.90 5.00
1 2 E1 .150 .154 .157 3.80 3.90 4.00
ccc C E .236 BSC 6.00 BSC
2X N/2 TIPS e/2 e .050 BSC 1.27 BSC
F .116 .120 .130 2.95 3.05 3.30
B H .085 .095 .099 2.15 2.41 2.51
h .010 - .020 0.25 - 0.50
L .016 .028 .041 0.40 0.72 1.04
D
L1 (.041) (1.05)
aaa C N 8 8
A2 A 01 0° - 8° 0° - 8°
aaa .004 0.10
SEATING
PLANE bbb .010 0.25
C A1 ccc .008 0.20
bxN
bbb C A-B D
h
F

EXPOSED PAD h
H

H c
GAGE
PLANE

0.25 L
01
(L1)

DETAIL A
SEE DETAIL A
SIDE VIEW
NOTES:
1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).

SO-8 EDP2 Landing Pattern

2. DATUMS -A- AND -B- TO BE DETERMINED AT DATUM PLANE -H-

3. DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS

OR GATE BURRS.
4. REFERENCE JEDEC STD MS-012, VARIATION BA.

Land Pattern - SOIC-8 EDP

E SOLDER MASK
D

DIMENSIONS
DIM INCHES MILLIMETERS
C (.205) (5.20)
(C) Z
F G D .134 3.40
E .201 5.10
F .101 2.56
Y G .118 3.00
P .050 1.27
X .024 0.60
THERMAL VIA P
Ø 0.36mm Y .087 2.20
X Z .291 7.40

NOTES:
1. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY.
CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR
COMPANY'S MANUFACTURING GUIDELINES ARE MET.
2. REFERENCE IPC-SM-782A, RLP NO. 300A.
3. THERMAL VIAS IN THE LAND PATTERN OF THE EXPOSED PAD
SHALL BE CONNECTED TO A SYSTEM GROUND PLANE.
FAILURE TO DO SO MAY COMPROMISE THE THERMAL AND/OR
FUNCTIONAL PERFORMANCE OF THE DEVICE.

Contact Information

Semtech Corporation
Power Mangement Products Division
200 Flynn Road, Camarillo, CA 93012
Phone: (805) 498-2111 Fax: (805) 498-3804

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