DI-187 Design Idea

®
TOPSwitch-HX

35 W LCD Monitor

Application Device Power Output Input Voltage Output Voltage Topology

LCD Monitor TOP257EN 35 W 90 – 264 VAC 13 V Flyback

Design Highlights Operation

• Low component count, high efficiency
• Delivers 35 W in 50 °C ambient temperature environments
• EcoSmart® multi-mode technology meets energy efficiency
standards
• 0.55 W output power for <1 W input
• No-load power consumption: <200 mW at 230 VAC
• >82% Full-load efficiency
• Uses new low profile eSIP-7C high-power package that
reduces device height and PCB area
• 132 kHz switching frequency minimizes size and cost of power
magnetics
• Integrated safety and reliability features
• Accurate, auto-recovering hysteretic thermal shutdown
maintains safe PCB temperatures in any condition
• Auto-restart protects against output short circuits and open
feedback loops
• Output overvoltage protection (OVP), configurable for latching
or self-recovery
• Input undervoltage (UV) protection prevents power-up or
power-down output glitches
• Input overvoltage (OV) protection extends line surge limit
• Compliance to EN55022 and CISPR-22 Class B conducted
EMI: >6 dB margin
The design schematic in Figure 1 shows an LCD monitor power
supply utilizing the TOPSwitch-HX TOP257EN (U1) in a flyback
configuration. This supply operates over a wide input range (90 to
264 VAC), delivering a 13 V, 35 W supply to the load.
Y-capacitors C1, C2, and C7 together with inductor L1 provide
common mode filtering. Differential mode filtering is provided by
X-capacitor C3 and by the bulk capacitor C4. The filtered AC goes
to a bridge rectifier. Thermistor RT1 limits the inrush current when
AC is applied.
IC U1 turns on when the current into the V pin exceeds 25 μA.
Resistor R3 sets this input voltage threshold to 100 V DC.
IC U1 regulates the output by adjusting the duty cycle of the PWM
controller which drives the integrated switching MOSFET. The
controller within U1 uses a multi-mode control scheme which
seemlessly transitions between different switching modes to
maximize efficiency at any load.
C7 C12
2.2 nF R10 470 pF
250 VAC 33 7 100 V

T1 C13 C14 C15

L3
EF25 680 MF 680 MF 3.3 MH 330 MF
1 9,10 25 V 25 V 25 V 13 V, 2.69 A

D1 D2 C6
1N4937 1N4007 D7, D8
R2 2.2 nF SB580
100 k7 1 kV
1/2 W
R1
33 7 3
7,8

R4 C5 RTN
D5
FR106
NC 33 7 1 nF
D3 D4 R3 1/8 W 100 V
1N4937 1N4007 3.9 M7 R11
2 1.2 k7
1/2 W
5
L1
9 mH L2 D6 R6 C10
(3.5 × 7.6 mm) BAV20 4.7 7 22 MF R13
C3 4 50 V 42.2 k7
C4
100 nF 100 MF 1%
275 VAC 400 V
U2A
LTV817A
C1, C2
F1 220 pF t
O RT1
3.15 A 250 VAC 10 7 U2B
LTV817A
TOPSwitch-HX R5 VR2
D V U1 20 7 1N5255B R12
L TOP257EN 28 V 10 k7
C11 CONTROL
E 22 pF C
1 kV C16
R8 47 nF
N R9 50 V
100 7 S X F 10 7 U3
C8 1/8 W
90 - 264 100 nF TL431
R7 C9 2%
VAC 15.4 k7 50 V R14
47 MF 10 k7
1% 16 V 1%

PI-5156-060508
Figure 1. Schematic of a 35 W LCD Monitor Using TOP257EN.

www.powerint.com June 2008

A clamp network formed by D5, C6, R1, and R2 limits U1’s drain
voltage at turn-off. Fast-recovery diode D5 recovers some of the
clamp energy; R1 limits reverse diode currents and dampens
high-frequency ringing.
The output of the bias winding is rectified by D6 and filtered by
C10. Zener diode VR2 and resistor R5 form a latching output
overvoltage protection (OVP) circuit. Increased voltage at the
output causes increased voltage across C10. In an overvoltage
• OVP may be configured for latching (as in this design) or for self
recovery (non-latching). For non-latching recovery increase R5
to 5.1 kΩ.
• Resistor R4 and C5 form a snubber network across diode D6.
With ferrite bead L2 they reduce high-frequency conducted and
radiated EMI.
80

PI-5161-052808
condition Zener VR2 breaks down and current flows into the V pin 70
of IC U1, initiating a latching shutdown. The shutdown can be QP
either latching or auto-recovering depending on the value of R5. 60
AV
50
Diodes D7 and D8 rectify the secondary side output. Low-ESR
capacitors (C13, C14) filter the output from D7 and D8. A second- 40

dBMV
order filter made up of L3 and C15 provides additional filtering on the 30
output that switching noise across C13 and C14.
20
Resistors R13 and R14 act as a potential divider to sense the 10
output voltage. U3 drives optocoupler U2 through resistor R11 to
provide feedback information to U1’s C pin. 0

Key Design Points -10

• Fast-recovery diodes D1 and D3 reduce radiated EMI (by -20
eliminating voltage spikes inherent to regular diode high- 0.15 1.0 10.0 100.0
frequency turn-off snap, and by not conducting AC line-induced MHz
noise). Their placement ensures one of the two conducts in Figure 3. Conducted EMI with EN55022 B Limits. Input: 230 VAC, Maximum
each half cycle. Steady-state Load.
• Y-capacitor C7 placed across the transformer (T1) isolation
barrier reduces conducted EMI. The switching frequency is
modulated (jittered) to reduce EMI.
Transformer Parameters
Core Material EF25, gapped for ALG of 220 nH/t²
220 Bobbin EF25 10 pins, Horizontal
PI-5160-052808

First half primary: 29T, #26 AWG

200 Bias/feedback: 8T × 4, #30 AWG
Winding Details Secondary: 7T × 2, #23, TIW
Input Power (mW)

Shield: 9T × 4, #39 AWG

180
Second half primary: 27T, #26 AWG
First half primary (2–3), Bias/feedback (5–4),
160 Winding Order Secondary (9,10–7,8), Shield (NC–1),
Second half primary (3–1)
140 Primary Inductance 690 μH, ±5%
Primary Resonant 1.8 MHz (minimum)
120 Frequency
Leakage
Inductance 13 μH (maximum)
100
90 110 130 150 170 190 210 230 250 270 Table 1. Transformer Parameters. (AWG = American Wire Gauge,
TIW = Triple Insulated Wire, NC = No Connection)
Input Voltage (AC)
Figure 2. No-load Input Power vs Line Voltage.

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A
06/08 DI-187