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  • DLD Lab-5

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    The document describes a lab session to design and implement a BCD adder. The objective is to create a circuit to add two 4-bit BCD numbers. BCD represents each decimal digit using a 4-bit binary number from 0000 to 1001. The BCD adder observes three cases for the output: it is less than 1001, it is 1001, or there is carry out. The document shows test cases for different BCD number inputs and the corresponding outputs from the BCD adder circuit.

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    The document describes a lab session to design and implement a BCD adder. The objective is to create a circuit to add two 4-bit BCD numbers. BCD represents each decimal digit using a 4-bit binary number from 0000 to 1001. The BCD adder observes three cases for the output: it is less than 1001, it is 1001, or there is carry out. The document shows test cases for different BCD number inputs and the corresponding outputs from the BCD adder circuit.

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    15 views7 pages

    DLD Lab-5

    Uploaded by

    mir zohaib
    The document describes a lab session to design and implement a BCD adder. The objective is to create a circuit to add two 4-bit BCD numbers. BCD represents each decimal digit using a 4-bit binary number from 0000 to 1001. The BCD adder observes three cases for the output: it is less than 1001, it is 1001, or there is carry out. The document shows test cases for different BCD number inputs and the corresponding outputs from the BCD adder circuit.

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    © All Rights Reserved
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    of 7

    LAB SESSION # 5

    OBJECTIVE:
    To design and implement BCD adder.

    INTRODUCTION:
     BCD Addition:

    Binary Coded Decimal is a method of using binary digits to represent the decimal digits through
    0 to 9. The valid BCD numbers are (0000 to 1001). Each digit of the decimal number will be
    represented by its four-bit binary equivalent. In BCD addition the following three cases are
    observed.
    1- The resulting BCD number equal to less than (1001).

     BCD Adder:

    OBSERVATION:
    Input data A Input data B Output BCD
    A4 A3 A2 A1 B4 B3 B2 B1 Cout S4 S3 S2 S1
    1 0 0 0 0 0 1 0 0 1 0 1 0
    1 0 0 0 1 0 0 0 1 0 0 0 0
    0 0 1 0 1 0 0 0 0 1 0 1 0
    0 0 0 1 0 1 1 1 0 1 0 0 0
    1 0 1 0 1 0 1 1 1 0 1 0 1
    1 1 1 0 1 1 1 1 1 1 1 0 1
    1 0 1 0 1 1 0 1 1 0 1 1 1

    Circuit Diagram of BCD Adder


    RESULT:

    A4 A3 A2 A1 B4 B3 B2 B1 Cout S4 S3 S2 S1

    1 0 0 0 0 0 1 0 0 1 0 1 0
    A4 A3 A2 A1 B4 B3 B2 B1 Cout S4 S3 S2 S1

    1 0 0 0 1 0 0 0 1 0 0 0 0

    A4 A3 A2 A1 B4 B3 B2 B1 Cout S4 S3 S2 S1

    0 0 1 0 1 0 0 0 0 1 0 1 0
    A4 A3 A2 A1 B4 B3 B2 B1 Cout S4 S3 S2 S1

    0 0 0 1 0 1 1 1 0 1 0 0 0
    A4 A3 A2 A1 B4 B3 B2 B1 Cout S4 S3 S2 S1

    1 0 1 0 1 0 1 1 1 0 1 0 1

    A4 A3 A2 A1 B4 B3 B2 B1 Cout S4 S3 S2 S1

    1 1 1 0 1 1 1 1 1 1 1 0 1
    A4 A3 A2 A1 B4 B3 B2 B1 Cout S4 S3 S2 S1

    1 0 1 0 1 1 0 1 1 0 1 1 1

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