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TLE42754EXUMA1 Infineon
TLE42754EXUMA1 Infineon
1, September 2008
TLE42754
L o w D r o p o u t Li n e a r F i x e d Vo l t a g e R e g u l a t o r
Automotive Power
Low Dropout Linear Fixed Voltage Regulator TLE42754
1 Overview
Features
• Output Voltage 5 V ± 2%
• Ouput Current up to 450 mA
• Very low Current Consumption
• Power-on and Undervoltage Reset with Programmable Delay Time
• Reset Low Down to VQ = 1 V
• Very Low Dropout Voltage
• Output Current Limitation
• Reverse Polarity Protection PG-TO252-5
• Overtemperature Protection
• Suitable for Use in Automotive Electronics
• Wide Temperature Range from -40 °C up to 150 °C
• Input Voltage Range from -42 V to 45 V
• Green Product (RoHS compliant)
• AEC Qualified
Description
The TLE42754 is a monolithic integrated low-dropout voltage
regulator in a 5-pin TO-package, especially designed for automotive
applications. An input voltage up to 42 V is regulated to an output
voltage of 5.0 V. The component is able to drive loads up to PG-TO263-5
450 mA. It is short-circuit proof by the implemented current limitation
and has an integrated overtemperature shutdown. A reset signal is
generated for an output voltage VQ,rt of typically 4.65 V. The power-on
reset delay time can be programmed by the external delay capacitor.
Overview
Circuit Description
The control amplifier compares a reference voltage to a voltage that is proportional to the output voltage and drives
the base of the series transistor via a buffer. Saturation control as a function of the load current prevents any
oversaturation of the power element. The component also has a number of internal circuits for protection against:
• Overload
• Overtemperature
• Reverse polarity
Block Diagram
2 Block Diagram
TLE42754
I Q
Reset
Protection Bandgap Generator RO
Circuits Reference
GND D
Pin Configuration
3 Pin Configuration
GND
1 5
Ι RO D Q Ι GND Q
RO D
AEP02580 IEP02528
3.2 Pin Definitions and Functions TLE42754D (PG-TO252-5) and TLE42754G (PG-
TO263-5)
Pin Configuration
QF QF
52 ,
QF QF
*1' QF
QF QF
' 4
QF QF
3,1&21),*B662369*
Note: Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Note: Integrated protection functions are designed to prevent IC destruction under fault conditions described in the
data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are
not designed for continuous repetitive operation.
Note: Within the functional range the IC operates as described in the circuit description. The electrical
characteristics are specified within the conditions given in the related electrical characteristics table.
Regulated
Supply II I Q
IQ Output Voltage
Saturation Control
Current Limitation
}
C
CQ LOAD
CI ESR
Bandgap
Temperature Reference
Shutdown
GND
BlockDiagram_VoltageRegulator.vsd
900 T j = 25 °C
5,10
800
T j = 150 °C
700
5,00
600
IQ,max [mA]
V Q [V]
4,90 500
V I = 13.5 V
I Q = 50 mA 400
4,80
300
200
4,70
100
4,60 0
-40 0 40 80 120 160 0 10 20 30 40 50
T j [°C] V I [V]
Power Supply Ripple Rejection PSRR versus Line Regulation ∆VQ,line versus
ripple frequency fr) Input Voltage Change ∆VI)
03_PSRR_FR.VSD 04_DVQ_DVI.VSD
100 9
T j = -40 °C T j = 150 °C
90 8
T j = 25 °C
80
T j = 150 °C 7
70
6
PSRR [dB]
60
∆V Q [mV]
5
50 T j = 25 °C
4
40
I Q = 10 mA 3
30
C Q = 22 µF T j = -40 °C
ceramic 2
20
V I = 13.5 V
10 V ripple = 0.5 Vpp 1
0 0
0,01 0,1 1 10 100 1000 0 10 20 30 40
f [kHz] V I [V]
Load Regulation ∆VQ,load versus Output Capacitor Series Resistor ESR(CQ) versus
Output Current Change ∆IQ Output Current IQ
05_DVQ_DIQ.VSD 06_ESR_IQ.VSD
0 1000
VI = 8 V C Q = 22 µF
-5 T j = -40..150 °C
100
V I = 6..28 V
T j = -40 °C Unstable
ESR(C Q) [Ω ]
-10 T j = 25 °C Region
∆V Q [mV]
10
T j = 150 °C
-15 1
Stable
-20 0,1 Region
-25 0,01
0 100 200 300 400 500 0 100 200 300 400 500
I Q [mA] I Q [mA]
Dropout Voltage Vdr versus
Junction Temperature Tj
07_VDR_TJ.VSD
500
450
I Q = 400 mA
400
350 I Q = 300 mA
300
V DR[mV]
250
200
I Q = 100 mA
150
100
50 I Q = 10 mA
0
-40 0 40 80 120 160
T j [°C]
6 T j = 150 °C T j = 150 °C
25
5
20
I q [mA]
I q [mA]
15 T j = 25 °C
3 T j = 25 °C
10
2
5
1
0 0
0 50 100 150 200 0 100 200 300 400 500
I Q [mA] I Q [mA]
Current Consumption Iq versus
Input Voltage VI
10_IQ_VI.VSD
60
50
40
I q [mA]
30
R LOAD = 12.5 Ω
20
10
R LOAD = 500 Ω
0
0 10 20 30 40
V I [V]
with
• CD: capacitance of the delay capacitor to be chosen
• trd,new: desired power-on reset delay time
• trd: power-on reset delay time specified in this datasheet
For a precise calculation also take the delay capacitor’s tolerance into consideration.
with
• trr: reset reaction time
• trr,int: internal reset reaction time
• trr,d: reset discharge
5kΩ
R RO = ----------- × V IO
VQ
Supply I Q
VDD
Int. CQ RRO
Supply
Control RO
ID,ch Reset
I RO
VDST
VRT
Micro-
Controller
IDR,dsch
GND D
BlockDiagram_Reset.vsd
GND
CD
VI
t
t < trr,total
VQ
VRT
1V
VD t rd
V DU
V DRL
t
t rd trr,total trd t rr,total t rd t rr,total
VRO
1V
V RO,low
t
Undervoltage Reset Switching Threshold Power On Reset Delay Time trd versus
VRT versus Tj Junction Temperature Tj
12_TRD_TJ.VSD
11_VRT_TJ.VSD
5 20
C D = 47 nF
18
4,9
16
14
4,8
12
t rd [ms]
V RT [V]
4,7 10
8
4,6
6
4
4,5
2
4,4 0
-40 0 40 80 120 160 -40 0 40 80 120 160
T j [°C] T j [°C]
Power On Reset DelayTime trd versus Internal Reset Reaction Time trr,int versus Junction
Capacitance CD Temperature Tj
14_T RRINT_TJ.VSD
13_TRD_CD.VSD
90 3,5
80
3
T j = -40 °C
70 T j = 25 °C
2,5
T j = 150 °C
60
2
t rr,int [µs]
t rd [ms]
50
40 1,5
30
1
20
0,5
10
0 0
0 50 100 150 200 250 -40 0 40 80 120 160
C D [nF] T j [°C]
0,5
0,4
t rr,d [µs]
0,3
0,2
0,1
0
-40 0 40 80 120 160
T j [°C]
Package Outlines
6 Package Outlines
6.5 +0.15
-0.05
A
5.7 MAX.
1) 2.3 +0.05
-0.10
0.9 +0.20
-0.01
0.8 ±0.15
6.22 -0.2
9.98 ±0.5
0...0.15
0.51 MIN.
0.15 MAX.
per side 5 x 0.6 ±0.1 0.5 +0.08
-0.04
1.14
0.1 B
4.56
0.25 M A B
Figure 7 PG-TO252-5
Package Outlines
4.4
10 ±0.2
1.27 ±0.1
0...0.3
A B
8.5 1)
0.05
1±0.3
2.4
7.55 1)
9.25 ±0.2
0.1
(15)
2.7 ±0.3
4.7 ±0.5
0...0.15
5 x 0.8 ±0.1 0.5 ±0.1
4 x 1.7
8˚ MAX.
0.25 M A B 0.1 B
1) Typical
Metal surface min. X = 7.25, Y = 6.9
All metal surfaces tin plated, except area of cut. GPT09113
Figure 8 PG-TO263-5
Package Outlines
0.35 x 45˚
3.9 ±0.11) 0.1 C D
Stand Off
1.7 MAX.
0 ... 0.1
0.19 +0.06
(1.45)
8˚ MAX.
C 0.08 C
0.65 0.64 ±0.25
Bottom View
3 ±0.2
A
2.65 ±0.2
14 8 1 7
1 7 Exposed 14 8
B
Diepad
0.1 C A-B 2x
4.9 ±0.11)
Index Marking
1) Does not include plastic or metal protrusion of 0.15 max. per side
2) Does not include dambar protrusion
PG-SSOP-14-1,-2,-3-PO V02
You can find all of our packages, sorts of packing and others in our
Infineon Internet Page “Products”: http://www.infineon.com/products. Dimensions in mm
Revision History
7 Revision History
Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties
and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights
of any third party.
Information
For further information on technology, delivery terms and conditions and prices, please contact the nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements, components may contain dangerous substances. For information on the types in
question, please contact the nearest Infineon Technologies Office.
Infineon Technologies components may be used in life-support devices or systems only with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
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