Lab No.

11

Digital Filter Design And Analysis

(MatLab)

Designed by : Dawar Awan

Oct 2012 – Feb 2013
CECOS College of Engineering and IT dawar@cecos.edu.pk
Filter Design and Analysis Tool
 An easy way of designing filter in MatLab is using the Filter Design
and Analysis tool
 Write ‘fdatool’ on the command line and press enter

 A window will appear in which you can fill in the filter parameters
according to your need

CECOS College of Engineering and IT dawar@cecos.edu.pk

Filter Design and Analysis Tool

CECOS College of Engineering and IT dawar@cecos.edu.pk

Filter Design and Analysis Tool

Press the
‘Design Filter’
Button after
filling in the
specifications

CECOS College of Engineering and IT dawar@cecos.edu.pk

Filter Design and Analysis Tool

CECOS College of Engineering and IT dawar@cecos.edu.pk

M-file for the filter design

CECOS College of Engineering and IT dawar@cecos.edu.pk

M-file for the filter design

CECOS College of Engineering and IT dawar@cecos.edu.pk

M-file for the filter design

CECOS College of Engineering and IT dawar@cecos.edu.pk

M-file for the filter design
 The resulting M-files contains all those instructions which would
have been otherwise written to design the filter which has been
designed using the fdatool
 In the M-file the variables ‘b’ and ‘a’ are the forward and reverse
coefficients of the filter
 ‘filter’ function and the filter coefficients can be used to
implement the filtering operation
 Y=filter(b,a,x)
 ‘Y’ is the output signal
 ‘b’ and ‘a’ are filter coefficients
 ‘x’ is the input signal
CECOS College of Engineering and IT dawar@cecos.edu.pk
M-file for the filter design
 Note: In case of a FIR filter a=1

CECOS College of Engineering and IT dawar@cecos.edu.pk

Example

CECOS College of Engineering and IT dawar@cecos.edu.pk

Example

CECOS College of Engineering and IT dawar@cecos.edu.pk

Task
 Generate a composite signal containing 10, 20, 30 and 40 Hz
frequency signals. Pass the signal through a filter so that,
i. Only 10 Hz signal appears at the output
ii. 20 and 30 Hz signal should appear on the output
iii. 20 and 30 Hz signal should be eliminated

CECOS College of Engineering and IT dawar@cecos.edu.pk