TOPIC: Dataflow Design Style and Test

Moudles
COURSE: VLSI design using Verilog
CHAPTER: - Four

PPT SL.NO.: - 01

VERSION: - 01 LAST UPDATED ON: 07/09/2020

Presentation By: Pragya Sharma

 Design Vs Test Modules
Design Module Test Module(Stimulus/TestBench)

Structure Structure
module <module_name>(<ports>); module <test_module_name>;
<declarations> <data types>
<contructs> <test module>
endmodule <stimulus>
endmodule

 Module name-identify the module by name  Data types- declare inputs as registers and
 Ports-input, output, inout ports of the outputs as wires.
module  Test module- call the module to be tested
 Declarations- Registers, Functions and tasks  Stimulus-stimulating the signals in the test
 Constructs – Assignment Blocks module
And Gate
module and_gate(
input a,b,
output y);
assign y = a & b;
endmodule
 And Gate Testbench
module tb_and_gate;
reg A,B;
wire Y;
and_gate a1(.a(A), .b(B), .y(Y));
initial begin
A=1'B0;
B=1'B0;
end
always #6 A=~A;
always #3 B=~B;
always@(Y)
$display("time=%0t\tINPUT VALUES:\t output value Y=%B",$time,A,B,Y);
endmodule
OR Gate
module or_gate(
input a,b,
output y);
assign y = a | b;
endmodule
Or Gate Testbench
module tb_or_gate;
reg A,B;
wire Y;
or_gate a1(.a(A),.b(B), .y(Y));
initial begin
A=1'b0;
B=1'b0;
#45 $finish;
end
always #6 A=~A;
always #3 B=~B;
always @(Y)
$display("time=0t\tINPUT VALUE:\tA=%bB=%b\t output value
Y=%b",$time,A,B,Y);
endmodule
Xor Gate
module xor_gate(
input a,b,
output y);
assign y = a ^ b;
endmodule
Xor Gate Testbench
module tb_xor_gate;
reg A,B;
wire Y;
xor_gate a1(.a(A),.b(B), .y(Y));
initial begin
A=1'b0;
B=1'b0;
#45 $finish;
end
always #6 A=~A;
always #3 B=~B;
always @(Y)
$display("time=0t\tINPUT VALUE:\tA=%bB=%b\t output value
Y=%b",$time,A,B,Y);
endmodule
Half Adder in Digital Logic:
The addition of 2bits is called Half adder the input
variebles are augent and addent bits and output
variebles are sum&carry bits. A and B are the two
input bits.
Half Adder
Half Adder Truth Table, Schematic and Realization using gates
Half Adder
module half_adder(
input a,b,
output sum,carry);

assign sum = a^b;

assign carry = a & b;

endmodule
Half Adder TestBench
module tb_HALF_ADDER;
reg A,B;
wire SUM,CARRY;
half_adder HA(.a(A),.b(B),.sum(SUM),.carry(CARRY));
initial begin
A=1'b0;
B=1'b0;
#100 $finish;
end
always #6 A=~A;
always #3 B=~B;
always @(SUM,CARRY)
$display("time=0t\tINPUT VALUE:\tA=%bB=%b\t output value SUM=%b
CARRY=%b",$time,A,B,SUM,CARRY);
endmodule
Thank you!

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