11199a020 - Coa Lab Record

SRI CHANDRASEKHARENDRA SARASWATHI
VISWA MAHAVIDYALAYA
(UNIVERSITY ESTABLISHED UNDER SECTION 3 OF UGC ACT 1956)
ENATHUR, KANCHIPURAM – 631 561
Department of Computer Science and Engineering
COMPUTER ARCHITECTURE LABORATORY

RECORD
Name: A S H PRANAV
Reg. No : 11199A020
Class : II BE (CSE)
Subject : CS3P8 – COMPUTER ARCHITECTURE Lab
1
SRI CHANDRASEKHARENDRA SARASWATHI
VISWA MAHAVIDYALAYA
(UNIVERSITY ESTABLISHED UNDER SECTION 3 OF UGC ACT 1956)
ENATHUR, KANCHIPURAM – 631 561
BONAFIDE CERTIFICATE
This is to certify that this is the bonafide record of work done by Mr./Ms.
A S H PRANAV , with Reg. No11199A020 _ of II BE (CSE) in the Computer
Architecture Laboratory CS3P8 during the year 2020- 2021.
Staff-in-charge Head of the Department
Submitted for the Practical Examination held on
Examiner 1 Examiner 2
2
INDEX
Exp. Page No. Staff
Date Title
No Sign.
02/01/2021 IMPLEMENTATION OF LOGIC GATES 4-17
1 A. AND GATE
B. OR GATE
C. NOT GATE
D. NAND GATE
E. NOR GATE
F. XOR GATE
G. XNOR GATE
02/01/2021 18-21
2 IMPLEMENTATION OF ENCODER
A.USING IF ELSE STATEMENT
B. USING CASE STATEMENT
23/01/2021 22-25
3 IMPLEMENTATION OF DECODER
A.USING IF ELSE STATEMENT
23/01/2021 26-29
4 A.IMPLEMENTATION OF HALF ADDER
B. IMPLEMENTATION OF FULL ADDER
13/02/2021 30-33
5 IMPLEMENTATION OF MULTIPLEXER
A. USING IF ELSE STATEMENT
13/02/2021 34-38
6 IMPLEMENTATION OF DEMULTIPLEXER
A. USING IF ELSE STATEMENT
27/03/2021 39-44
7 IMPLEMENTATION OF COMPARATOR
A. ONE BIT COMPARATOR
B. FOUR BIT COMPARATOR
27/03/2021 45-48
8 A. ONE'S COMPLEMENT
B. TWO'S COMPLEMENT
10/04/2021 49-52
9 A. NINE'S COMPLEMENT
B. TEN'S COMPLEMENT
3
EX-01 DATE:2/1/21
IMPLEMENTATION OF LOGIC GATES
A) AND GATE:
AIM:
To simulate an AND logic gate using model sim Simulator with Verilog code.
DESCRIPTION:
The AND gate is a basic digital logic gate that implements logical multiplication. The output of the
logic gate is based on the two inputs that it receives, it is high (1) when both the inputs are high (1).
VERILOG CODE:
module andgate(a,b,c);
input a,b;
output c;
assign c = a &
b; endmodule
TESTBENCH CODE:
module andgate_tb( );
reg a, b;
wire c;
andgate DUT(a,b,c);
initial begin
//$monitor (a,b,c);
$dumpfile (“test.vcd”);
$dumpvars(1);
a = 1’b0;
b = 1’b0;
#5 //$display (“a=%b, b=%b, c=%b”,a,b,c);
a = 1’b0;
b = 1’b1;
a = 1’b1;
b = 1’b0;
a = 1’b1;
b = 1’b1;
//$display (“a=%b, b=%b, c=%b”,a,b,c);
end
endmodule
LOGIC GATE,TRUTH TABLE:
WAVE:
RESULT:
Thus, the logic gate was simulated and the truth table was verified.
EXP-01 DATE:2/1/21
B) OR GATE
AIM:
To simulate an OR logic gate using Model Sim Simulator with Verilog code.
DESCRIPTION:
An OR gate is a basic addition logic gate that generally requires two inputs, based on which the
output generated is either high (1) if both the inputs are high (1), or the output is generated as low
(0).
VERILOG CODE:
module orgate(a,b,c);
input a,b;
output c;
assign c = a | b;
endmodule
TEST BENCH CODE:

module orgate_tb( );
reg a, b;
wire c;
orgate DUT(a,b,c);
initial begin
//$monitor (a,b,c);
$dumpvars(1);
a = 1’b0;
b = 1’b0;
a = 1’b0;
b = 1’b1;
a = 1’b1;
b = 1’b0;
a = 1’b1;
b = 1’b1;
//$display (“a=%b, b=%b, c=%b”,a,b,c);
end
endmodule
TRUTHTABLE AND LOGIC GATE:
WAVE:
RESULT:
EXP-01 DATE:2/1/21
C) NOT GATE:
AIM:
To simulate a NOT logic gate using Model Sim Simulator with Verilog code.
DESCRIPTION:
A not gate, also known as an inverter is a logic complementor where one input is fed to the logic
gate to yield the inverse of that signal. A high (1) input shall output a low (0) signal, and vice versa.
VERILOG CODE:
module notgate(a,b);
input a;
output b;
assign b = ~a;
endmodule
TESTBENCH CODE:
module notgate_tb( );
reg a;
wire b;
notgate DUT(a,b);
initial begin
//$monitor (a,b);
$dumpvars(1);
a = 1’b0;
#5 //$display (“a=%b, b=%b ”,a,b);
a = 1’b1;
//$display (“a=%b, b=%b ”,a,b);
end
endmodule
WAVE:
RESULT:
EXP-01 DATE:2/1/21
D) NAND GATE
AIM:
To simulate a NAND logic gate using Model Sim Simulator with Verilog code.
DESCRIPTION:
Known as universal gate, the NAND gate typically has two inputs, and the outputs are high for
combinations that involve at least one low (0) input signal, then the outputs are high. This can be
also referred to as the complement of an AND gate.
VERILOG CODE:
module nandgate(a,b,c);
input a,b;
output c;
assign c = ~( a & b );
endmodule
TESTBENCH CODE:
module nandgate_tb( );
reg a, b;
wire c;
nandgate DUT(a,b,c);
initial begin
//$monitor (a,b,c);
$dumpvars(1);
a = 1’b0;
b = 1’b0;
#5 //$display (“a=%b b=%b c=%b”,a,b,c);
a = 1’b0;
b = 1’b1;
a = 1’b1;
b = 1’b0;
a = 1’b1;
b = 1’b1;
//$display (“a=%b b=%b c=%b”,a,b,c);
end
endmodule
TRUTH TABLE AND LOGIC GATE:
WAVE:
RESULT:
EXP-01 DATE:2/1/21
E) NOR GATE
AIM:
To simulate a NOR logic gate using Model Sim Simulator with Verilog code.
DESCRIPTION:
The output of a NOR gate is high (1) whenever it receives at least two low (0) signal input. Which
means, the input of one, or two high (1) signals yield a low (0) output, otherwise a high (1) output
for all other combinations.
VERILOG CODE:
module norgate(x,y,z);
input x,y;
output z;
assign z =~( x | y );
endmodule
TESTBENCH CODE:
module norgate_tb( );
reg x, y;
wire z;
norgate DUT(x,y,z);
initial begin
//$monitor (x,y,z);
$dumpvars(1);
x = 1’b0;
y = 1’b0;
#5 //$display (“x=%b y=%b z=%b”,x,y,z);
x = 1’b0;
y = 1’b1;
x = 1’b1;
y = 1’b0;
x = 1’b1;
y = 1’b1;
//$display (“x=%b y=%b z=%b”,x,y,z);
end
endmodule
WAVE:
RESULT:
EXP-01 DATE:2/1/21
F) XOR GATE
AIM:
To simulate an XOR logic gate using Model Sim Simulator with Verilog code.
DESCRIPTION:
A typical two input XOR gate does an operation based on the two input it receives, i.e.,
whenever the two inputs match, are of the same combination, the output generated is low (0), for
dissimilar input signals, the output is always high (1).
VERILOG CODE:
module xorgate(a ,b, c);
input a, b;
output c;
assign c = a ^
b; endmodule
TESTBENCH CODE:
module xorgate_tb( );
reg a, b;
wire c;
xorgate DUT(a,b,c);
initial begin
//$monitor (a,b,c);
$dumpvars(1);
a = 1’b0;
b = 1’b0;
a = 1’b0;
b = 1’b1;
a = 1’b1;
b = 1’b0;
a = 1’b1;
b = 1’b1;
//$display (“a=%b b=%b c=%b”,a,b,c);
end
endmodule
WAVE:
RESULT:
EXP-01 DATE:2/1/21
G) XNOR
AIM:
To simulate an XNOR logic gate using Model Sim Simulator with Verilog code.
DESCRIPTION:
The XNOR gate is a digital logic gate whose function is the logical complement of the Exclusive
OR gate. The two-input version implements logical equality, behaving according to the truth table to
the right, and hence the gate is sometimes called an "equivalence gate".
VERILOG CODE:
module xnorgate(c,a,b);
input a,b;
output c;
assign c=~(a^b);
endmodule
TESTBENCH CODE:
module xnor_test;
reg a,b;
wire c;
xnor_gate xnor_test(c,a,b);
initial
begin
#000 a=0;b=0;
#100 a=0;b=1;
#100 a=1;b=0;
#100 a=1;b=1;
end
initial
begin
$monitor($time,"a=%b,b=%b,c=%b",a,b,c);
end
endmodule
WAVE:
RESULT: Thus, the logic gate was simulated and the truth table was verified.
EXP-02 DATE:2/1/21
IMPLEMENTATION OF ENCODER
A) USING IF-ELSE STATEMENT
AIM:
To simulate an encoder using model sim simulator with a Verilog code that supports conditional
statements.
THEORY:
An encoder perform operation similar to that of a multiplexer, scales the Down sampling of 2n
inputs and n outputs thereby taking four inputs y0 y1 y2 y3, and two outputs viz. a0 and a1.
VERILOG CODE:
module enc-if_else(a, y);
input [3:0]a;
output reg[1:0]y;
always @ (a)
begin
if(a==4'b1000)
y=2'b00;
else if(a==4'b0100)
y=2'b01;
else if(a==4'b0010)
y=2'b10;
else if(a==4'b0001)
y=2'b11;
else
y=2'bzz;
end
endmodule
TESTBENCH CODE:
module encoder_tb();
reg [3:0]a;
wire [1:0]b;
encoder DUT(a,b);
initial begin
//$monitor ([3:0]a,[1:0]b);
$dumpfile("test.vcd");
$dumpvars(1);
a=0;
a= 4'b0001;
#5 //$display("a=%b b=%b,[3:0]a,[1:0]b);
a= 4'b0010;
#5 //$display("a=%b b=%b,[3:0]a,[1:0]b);
a= 4'b0100;
#5 //$display("a=%b b=%b,[3:0]a,[1:0]b);
a= 4'b1000;
//$display("a=%b b=%b,[3:0]a,[1:0]b);
end
endmodule
WAVE:
RESULT:
Thus, the Verilog code simulation for an Encoder (4:2) using if else has been carried out
successfully.
EXP-02 DATE:2/1/21
IMPLEMENTATION OF AN ENCODER
B) USING CASE STATEMENT
AIM:
To simulate an encoder using model sim simulator with a Verilog code that supports conditional
statements.
THEORY:
An encoder performs operation similar to that of a multiplexer, scales the Down sampling of 2n
inputs and n outputs thereby taking four inputs y0 y1 y2 y3, and two outputs viz. a0 and a1.
VERILOG CODE:
module enc_case(a, y);
input [3:0]a;
output reg[1:0]y;
always @ (a)
case (a)
4'b1000: y=2'b00;
4'b0100: y=2'b01;
4'b0010: y=2'b10;
4'b0001: y=2'b11;
endcase
endmodule
TESTBENCH CODE:
module encoder_tb();
reg [3:0]a;
wire [1:0]b;
encoder DUT(a,b);
initial begin
//$monitor ([3:0]a,[1:0]b);
$dumpvars(1);
a=0;
a= 4'b0001;
#5 //$display("a=%b b=%b,[3:0]a,[1:0]b);
a= 4'b0010;
#5 //$display("a=%b b=%b,[3:0]a,[1:0]b);
a= 4'b0100;
#5 //$display("a=%b b=%b,[3:0]a,[1:0]b);
a= 4'b1000;
//$display("a=%b b=%b,[3:0]a,[1:0]b);
end
endmodule
WAVE:
RESULT:
Thus, the Verilog code simulation for an Encoder using case (4:2) has been carried out
successfully.
EXP-03 DATE:23/1/21
IMPLEMENTATION OF DECODERS
A) USING IF ELSE STATEMENTS
AIM:
To simulate a decoder using Verilog code on the model sim simulator based on conditional
statements.
THEORY:
A decoder performs demultiplexing operations based on two inputs to yield required outputs on
upscaled forms, such as a two input to four output applications etc.
VERILOG CODE:
module decod1(a, y);
input [1:0]a;
output [3:0]y;
reg[3:0]y;
always @ (a)
begin
if (a==2'b00)
y=4'b1000;
else if (a==2'b01)
y=4'b0100;
else if (a==2'b10)
y=4'b0010;
else if (a==2'b11)
y=4'b0001;
else
y=4'b0000;
end
endmodule
TESTBENCH CODE:
module decoder_tb();
reg [1:0]a;
wire [3:0]b;
decoder DUT(a,b);
initial begin
//$monitor ([1:0]a,[3:0]b);
$dumpvars(1);
a=0;
a= 2'b00;
#5 //$display("a=%b b=%b,[1:0]a,[3:0]b);
a= 2'b01;
#5
a=2'b10;
#5
a= 2'b11;
end
endmodule
WAVE:
RESULT:
The simulation of a decoder using if else has been successfully carried out and the truth tables
were verified.
EXP-03 DATE:23/1/21
IMPLEMENTATION OF DECODERS
B) USING CASE
AIM:
To simulate a decoder using Verilog code on the model sim simulator based on conditional
statements.
THEORY:
A decoder performs demultiplexing operations based on two inputs to yield required outputs on
upscaled forms, such as a two input to four output applications etc.
VERILOG CODE:
module decod2(a, y);
input [1:0]a;
output reg [3:0]y;
always @ (a)
case (a)
2'b00: y=4'b1000;
2'b01: y=4'b0100;
2'b10: y=4'b0010;
2'b11: y=4'b0001;
endcase
endmodule
TESTBENCH CODE:
module decoder_tb();
reg [1:0]a;
wire [3:0]b;
decoder DUT(a,b);
initial begin
//$monitor ([1:0]a,[3:0]b);
$dumpvars(1);
a=0;
a= 2'b00;
#5 //$display("a=%b b=%b,[1:0]a,[3:0]b);
a= 2'b01;
#5
a=2'b10;
#5
a= 2'b11;
end
endmodule
WAVE:
RESULT:
The simulation of a decoder has been successfully carried out and the truth tables were verified.
EXP-04 DATE:23/1/21
A) IMPLEMENTATION OF HALF ADDER
AIM:
To simulate a half adder using model sim simulator and verify its output using the truth tables
provided.
THEORY:
Half Adder:
A half adder has two inputs and two outputs, namely SUM (S) and CARRY (C). It is a combination
of an XOR Gate and an AND gate to yield the two outputs, respectively.
VERILOG CODE:
module halfadder(a ,b ,s ,c);
input a, b;
output s, c;
assign s=a^ b;
assign c=a& b;
endmodule
TESTBENCH CODE:
module halfadder_tb();
reg a,b;
wire s,c;
halfadder DUT(a,b,s,c);
initial begin
//$monitor (a,b,s,c);
$dumpvars(1);
a= 1'b0;
b= 1'b0;
#5 //$display("a=%b, b=%b, s=%b, c=%b",a,b,s,c);
a= 1'b0;
b= 1'b1;
a= 1'b1;
b= 1'b0;
a= 1'b1;
b= 1'b1;
//$display("a=%b, b=%b, s=%b, c=%b",a,b,s,c);
end
endmodule
WAVE:
RESULT:
Thus, the simulation for a half adder using Verilog code was successfully carried out.
EXP-04 DATE:23/1/21
B) IMPLEMENTATION OF FULL ADDER
AIM:
To simulate a full adder using the model sim Simulator on Verilog Code and verify its truth tables
respectively.
THEORY:
Full Adder:
A full adder is a combinational circuit, that forms arithmetic sums of the inputs provided. It contains
three input terminals and two output. The two output terminals are SUM (S) and CARRY (C)
respectively. It is notable that two half adders and an OR Gate constitute a full adder.
VERILOG CODE:
module fulladder(x,y,z,s,c);
input x,y,z;
output s,c;
assign s=x^y^z;
assign c=((x&y) | (y&z) | (z&x));
endmodule
TESTBENCH CODE:
module fulladder_tb();
reg x,y,z;
wire s,c;
fulladder DUT(x,y,z,s,c);
initial begin
//$monitor (x,y,z,s,c);
$dumpvars(1);
x= 1'b0;
y= 1'b0;
z= 1'b0;
#5 //$display("x=%b y=%b z=%b s=%b c=
%b",a,b,z,s,c); x= 1'b0;
y= 1'b0;
z= 1'b1;
#5
x= 1'b0;
y= 1'b1;
z= 1'b0;
#5
x= 1'b0;
y= 1'b1;
z= 1'b1;
#5
x= 1'b1;
y= 1'b0;
z= 1'b0;
#5
x= 1'b1;
y= 1'b0;
z= 1'b1;
#5
x= 1'b1;
y= 1'b1;
z= 1'b0;
#5
x= 1'b1;
y= 1'b1;
z= 1'b1;
end
endmodule
WAVE:
RESULT:
Thus, the module was compiled and the simulation was carried out successfully.
EXP-05 DATE:13/2/21
IMPLEMENTATION OF MULTIPLEXER
A) USING IF ELSE STATEMENT
AIM:
To simulate a 4x1 multiplexer using if else statement on the model sim Simulator using Verilog
code.
THEORY:
Multiplexer is a combinational circuit that selects binary information from one of many input lines
and directs it to a single output line. The selection of a particular input line depends on a set of
selection lines, out of 2N input lines, there exist N selection lines.
VERILOG CODE:
module mux(I,s,y);
input [1:0]s;
input [3:0]I;
output reg y;
always @ (I,s)
if(s==2'b00)
begin y=I[0];
end
else if(s==2'b01)
begin y=I[1];
end
else if(s==2'b10)
begin y=I[2];
end
else if(s==2'b11)
begin y=I[3];
end
else
y=1'bz;
endmodule
TESTBENCH CODE:
module multiplexer_tb();
reg [3:0]I,S;
wire y;
multiplexer DUT(I,S,y);
initial begin
//$monitor (I,S,y);
$dumpvars(1);
S= 2'b00;
I= 4'b1000;
#5 //$display("I=%b S=%b y=%b",I,S,y);
S= 2'b01;
I= 4'b0100;
#5
S= 2'b10;
I= 4'b0010;
#5
S= 2'b11;
I= 4'b0001;
end
endmodule
WAVE:
RESULT:
Thus, the code was simulated and the output was verified.
EXP-05: DATE:23/1/21
IMPLEMENTATION OF MULTIPLEXER
B) USING CASE STATEMENTS
AIM:
To simulate a 4x1 multiplexer using case statement on the model sim Simulator using Verilog code.
THEORY:
Multiplexer is a combinational circuit that selects binary information from one of many input lines
and directs it to a single output line. The selection of a particular input line depends on a set of
selection lines, out of 2N input lines, there exist N selection lines.
VERILOG CODE:
module multiplexer(I,S,y);
input wire [3:0]I;
input wire [1:0]S;
output reg y;
always @ (I[0] or I[1] or I[2] or I[3] or S[0],S[1])
begin
case (S[0] | S[1])
2'b00 : y <= I[0];
2'b01 : y <= I[1];
2'b10 : y <= I[2];
2'b11 : y <= I[3];
endcase
end
endmodule
TESTBENCH CODE:
module multiplexer_tb();
reg [3:0]I,S;
wire y;
multiplexer DUT(I,S,y);
initial begin
//$monitor (I,S,y);
$dumpvars(1);
S= 2'b00;
I= 4'b1000;
S= 2'b01;
I= 4'b0100;
#5
S= 2'b10;
I= 4'b0010;
#5
S= 2'b11;
I= 4'b0001;
end
endmodule
WAVE:
RESULT:
Thus, the code was simulated and the output was verified.
EXP-06 DATE:13/2/21
IMPLEMENTATION OF DEMULTIPLEXER
A) USING IF ELSE STATEMENT
AIM:
To simulate a 1x4 Demultiplexer using if else statement on the model sim Simulator using Verilog
code and verify its output with the truth tables enclosed.
THEORY:
Commonly known as demultiplexer, the demultiplexer converts 2bit single line input to 2^n number
of output lines, where n stands for the number of input lines according to the selection line
combinations.
VERILOG CODE:
module demux(I,s,y);
input I;
input [1:0]s;
output reg[3:0]y;
always @ (I,s)
if(s==2'b00)
begin
y[0]=I; y[1]=1'b0;
y[2]=1'b0; y[3]=1'b0;
end
else if(s==2'b01)
begin
y[0]=1'b0; y[1]=I;
y[2]=1'b0; y[3]=1'b0;
end
else if(s==2'b10)
begin
y[0]=1'b0; y[1]=1'b0;
y[2]=I; y[3]=1'b0;
end
else if(s==2'b11)
begin
y[0]=1'b0; y[1]=1'b0;
y[2]=1'b0; y[3]=I;
end
endmodule
TESTBENCH CODE:
module demultiplexer_tb();
reg I;
reg [1:0]S;
wire [3:0]y;
demultiplexer DUT(I,S,y);
initial begin
//$monitor (I,S,y);
$dumpvars(1);
S= 2'b00;
I= 1'b0;
S= 2'b01;
I= 1'b0;
#5
S= 2'b10;
I= 1'b1;
#5
S= 2'b11;
I= 1'b1;
end
endmodule
WAVE:
RESULT:
Thus, the code was simulated and the outputs were successfully verified.
EXP-06 DATE:13/2/21
IMPLEMENTATION OF DEMULTIPLEXER
B) USING CASE STATEMENT
AIM:
To simulate a 1x4 Demultiplexer using if else statement on the model sim Simulator using Verilog
code and verify its output with the truth tables enclosed.
THEORY:
Commonly known as demultiplexer, the demultiplexer converts 2bit single line input to 2^n number
of output lines, where n stands for the number of input lines according to the selection line
combinations.
VERILOG CODE:
module demultiplexer(I,S,y);
input I;
input [1:0]S;
output reg [3:0]y;
always @ (y,S)
begin
case (S)
2'b00 : begin y[0] = I; y[3:1] = 0;
end 2'b01 : begin y[1] = I; y[0] = 0;
end 2'b10 : begin y[2] = I; y[1:0] =
0; end 2'b11 : begin y[3] = I; y[2:0]
= 0; end
endcase
end
endmodule
TESTBENCH CODE:
module demultiplexer_tb();
reg I;
reg [1:0]S;
wire [3:0]y;
demultiplexer DUT(I,S,y);
initial begin
//$monitor (I,S,y);
$dumpvars(1);
S= 2'b00;
I= 1'b0;
S= 2'b01;
I= 1'b0;
#5
S= 2'b10;
I= 1'b1;
#5
S= 2'b11;
I= 1'b1;
end
endmodule
WAVE:
RESULT:
Thus, the code was simulated and the outputs were successfully verified.
EXP-07 DATE:27/3/21
A) ONE-BIT COMPARATOR
AIM:
To simulate a 1-bit comparator using Verilog Code on the model sim Simulator.
THEORY:
A digital comparator is an electronic logic tester, that takes two numbers as input in their binary
form, and checks for the greater one among them. The results are either greater than, less than or
equal to, with one side of the equation presumed.
VERILOG CODE:
module comp1(a, x);
input [1:0] a;
output reg [2:0]x;
always @ (a)
begin
if(a[1]> a[0])
begin
x[0]=1'b1;x[1]=1'b0;x[2]=1'b0;
end
else if(a[0]>a[1])
begin
x[0]=1'b0;x[1]=1'b0;x[2]=1'b1;
end
else if(a[0]==a[1])
begin
x[0]=1'b0;x[1]=1'b1;x[2]=1'b0;
end
else
begin
x[0]=1'bz;x[1]=1'bz;x[2]=1'bz;
end
end
endmodule
TESTBENCH CODE:
module bitcomparator_tb();
reg [1:0]a;
reg [1:0]z;
wire [2:0]x;
bitcomparator DUT(a,z,x);
initial begin
//$monitor (a,z,x);
$dumpvars(1);
a= 2'b00;
z= 2'b00;
#5 //$display("a=%b x=%b",a,x);
a= 2'b00;
z= 2'b01;
#5
a= 2'b00;
z= 2'b10;
#5
a= 2'b00;
z= 2'b11;
#5
a= 2'b01;
z= 2'b00;
#5
a= 2'b01;
z= 2'b01;
#5
a= 2'b01;
z= 2'b10;
#5
a= 2'b01;
z= 2'b11;
#5
a= 2'b10;
z= 2'b00;
#5
a= 2'b10;
z= 2'b01;
#5
a= 2'b10;
z= 2'b10;
#5
a= 2'b10;
z= 2'b11;
#5
a= 2'b11;
z= 2'b00;
#5
a= 2'b11;
z= 2'b10;
#5
a= 2'b11;
z= 2'b01;
#5
a= 2'b11;
z= 2'b11;
end
endmodule
WAVE:
RESULT:
Thus, the code for a one-bit comparator was executed and the results were verified.
EXP-07 DATE:27/3/21
B) FOUR-BIT COMPARATOR
AIM:
To simulate a 4-bit comparator using Verilog Code on the model sim Simulator
THEORY:
A digital comparator is an electronic logic tester, that takes two numbers as input in their binary
form, and checks for the greater one among them. The results are either greater than, less than or
equal to, with one side of the equation presumed. A four-bit comparator deals with two 4bit values.
VERILOG CODE:
module comp4(a,b,g,l,e);
input [3:0]a;
input [3:0]b;
output reg g,l,e;
always @ (a,b)
begin
if(a>b)
begin
g=1'b1; l=1'b0; e=1'b0;
end
else
if(a<b)
begin
g=1'b0; l=1'b1; e=1'b0;
end
else
if(a==b)
begin
g=1'b0; l=1'b0; e=1'b1;
end
else
begin
g=1'b0; l=1'b0; e=1'b0;
end
end
endmodule
TESTBENCH CODE:
module bitComparator_4_tb();
reg [1:0]a;
reg [1:0]b;
wire g,l,e;
bitComparator_4 DUT(a,b,g,l,e);
initial begin
//$monitor (a,b,g,l,e);
$dumpvars(1);
a= 2'b00;
b= 2'b00;
#5 //$display("a=%b b=%b g=%b l=%b e=%b",a,b,g,l,e);
a= 2'b00;
b= 2'b01;
#5
a= 2'b00;
b= 2'b10;
#5
a= 2'b00;
b= 2'b11;
#5
a= 2'b01;
b= 2'b00;
#5
a= 2'b01;
b= 2'b01;
#5
a= 2'b01;
b= 2'b10;
#5
a= 2'b01;
b= 2'b11;
#5
a= 2'b10;
b= 2'b00;
#5
a= 2'b10;
b= 2'b01;
#5
a= 2'b10;
b= 2'b10;
#5
a= 2'b10;
b= 2'b11;
#5
a= 2'b11;
b= 2'b00;
#5
a= 2'b11;
b= 2'b10;
#5
a= 2'b11;
b= 2'b01;
#5
a= 2'b11;
b= 2'b11;
end
endmodule
WAVE:
RESULT:
Thus, the code for a four bit comparator was executed and the results were verified.
EXP-08 DATE:27/3/21
A) ONES COMPLEMENT
AIM:
To simulate a one’s complement using Verilog code on the model sim Simulator.
THEORY:
The One’s Complement of an input is otherwise known as the negation or the inversion operation
that yields the inverse of the input.
VERILOG CODE:
module onescomplement(a,b);
input [3:0]a;
output reg [3:0]b;
always @ (a)
b = ~a ;
endmodule
TESTBENCH CODE:
module onescomplement_tb();
reg [3:0]a;
wire [3:0]b;
onescomplement DUT(a,b);
initial begin
//$monitor (a,b);
$dumpvars(1);
a= 4'b0000;
#5 //$display("a=%b b=%b",a,b);
a= 4'b0001;
#5
a= 4'b0010;
#5
a= 4'b0011;
#5
a= 4'b0100;
#5
a= 4'b0101;
#5
a= 4'b0110;
#5
a= 4'b0111;
#5
a= 4'b1000;
#5
a= 4'b1001;
#5
a= 4'b1010;
#5
a= 4'b1011;
#5
a= 4'b1100;
#5
a= 4'b1101;
#5
a= 4'b1110;
#5
a= 4'b1111;
end
endmodule
WAVE:
RESULT:
Thus, the required simulation for a ones complement has been successfully done.
EXP-08 DATE:27/3/21
B) TWO’S COMPLEMENT
AIM:
To simulate a Two’s complement using Verilog code on the model sim Simulator.
THEORY:
The Two’s Complement of an input is generated by the negation or the inversion operation of the
input, incremented once (+1’b1) as the output.
VERILOG CODE:
module twocomp(a,b);
input [3:0]a;
output reg[3:0]b;
always @ (a)
b=(~a) + 1'b1;
endmodule
TESTBENCH CODE:
module twoscomplement_tb();
reg [3:0]a;
wire [3:0]b;
twoscomplement DUT(a,b);
initial begin
//$monitor (a,b);
$dumpvars(1);
a= 4'b0000;
a= 4'b0001;
#5
a= 4'b0010;
#5
a= 4'b0011;
#5
a= 4'b0100;
#5
a= 4'b0101;
#5
a= 4'b0110;
#5
a= 4'b0111;
#5
a= 4'b1000;
#5
a= 4'b1001;
#5
a= 4'b1010;
#5
a= 4'b1011;
#5
a= 4'b1100;
#5
a= 4'b1101;
#5
a= 4'b1110;
#5
a= 4'b1111;
end
endmodule
WAVE:
RESULT:
Thus, the required simulation for a two’s complement has been successfully done.
EXP-09 DATE:10/4/21
A) NINE’S COMPLEMENT
AIM:
To simulate a Nine’s complement using Verilog code on the model sim Simulator.
THEORY:
Much similar to a one’s and two’s complement, the Nine’s Complement generates the
difference between 4’b1001 and the given input value.
VERILOG CODE:
module ninescomp(a,b);
input [3:0]a;
output reg[3:0]b;
always @ (a)
b=4'b1001 - a;
endmodule
TESTBENCH CODE:
module ninescomplement_tb();
reg [3:0]a;
wire [3:0]b;
ninescomplement DUT(a,b);
initial begin
//$monitor (a,b);
$dumpvars(1);
a= 4'b0000;
a= 4'b0001;
#5
a= 4'b0010;
#5
a= 4'b0011;
#5
a= 4'b0100;
#5
a= 4'b0101;
#5
a= 4'b0110;
#5
a= 4'b0111;
#5
a= 4'b1000;
#5
a= 4'b1001;
#5
a= 4'b1010;
#5
a= 4'b1011;
#5
a= 4'b1100;
#5
a= 4'b1101;
#5
a= 4'b1110;
#5
a= 4'b1111;
end
endmodule
WAVE:
RESULT:
Thus, the required simulation for a Nine’s complement has been successfully done.
EXP-09 DATE:10/4/21
B) TEN’S COMPLEMNET
AIM:
To simulate a Ten’s complement using Verilog code on the model sim Simulator.
THEORY:
Parallel to the working of the Nines complement, the Ten’s complement generates the difference
between 4’b1001 and the given input value with an increment (+ 1’b1).
VERILOG CODE:
module tenscomp(a,b);
input [3:0]a;
output reg[3:0]b;
always @ (a)
b=(4'b1001-a) + 1'b1
endmodule
TESTBENCH CODE:
module tenscomplement_tb();
reg [3:0]a;
wire [3:0]b;
tenscomplement DUT(a,b);
initial begin
//$monitor (a,b);
$dumpvars(1);
a= 4'b0000;
a= 4'b0001;
#5
a= 4'b0010;
#5
a= 4'b0011;
#5
a= 4'b0100;
#5
a= 4'b0101;
#5
a= 4'b0110;
#5
a= 4'b0111;
#5
a= 4'b1000;
#5
a= 4'b1001;
#5
a= 4'b1010;
#5
a= 4'b1011;
#5
a= 4'b1100;
#5
a= 4'b1101;
#5
a= 4'b1110;
#5
a= 4'b1111;
end
endmodule
WAVE:
RESULT:
Thus, the required simulation for a Ten’s complement has been successfully done.
THE END

11199a020 - Coa Lab Record

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SRI CHANDRASEKHARENDRA SARASWATHI

Department of Computer Science and Engineering

COMPUTER ARCHITECTURE LABORATORY

Subject : CS3P8 – COMPUTER ARCHITECTURE Lab

A S H PRANAV , with Reg. No11199A020 _ of II BE (CSE) in the Computer

Architecture Laboratory CS3P8 during the year 2020- 2021.

Staff-in-charge Head of the Department

Submitted for the Practical Examination held on

TEST BENCH CODE:

LOGIC GATE,TRUTH TABLE:

LOGIC GATE,TRUTH TABLE:

LOGIC GATE,TRUTH TABLE:

LOGIC GATE,TRUTH TABLE:

LOGIC GATE,TRUTH TABLE:

LOGIC GATE,TRUTH TABLE:

LOGIC GATE,TRUTH TABLE:

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