Berkeley Switch Cap Filters

EE247
Lecture 9
• Switched-Capacitor Filters
– “Analog” sampled-data filters:
• Continuous amplitude
• Quantized time
– Applications:
• First commercial product: Intel 2912 voice-band
CODEC chip, 1979
• Oversampled A/D and D/A converters
• Stand-alone filters
E.g. National Semiconductor LMF100
EECS 247 Lecture 9: Switched-Capacitor Filters © 2005 H.K. Page 1
Switched-Capacitor Filters
Today
• Emulating resistor via switched-capacitor
network
• 1st order switched-capacitor filter
• Switch-capacitor filter considerations:
– Issue of aliasing and how to avoid it
– Tradeoffs in choosing sampling rate
– Effect of sample and hold
– Switched-capacitor filter electronic noise
– Switched-capacitor integrator topologies
Switched-Capacitor Resistor
φ1 φ2
• Capacitor C is the “switched
capacitor” vIN vOUT
S1 S2
• Non-overlapping clocks φ1 and φ2
control switches S1 and S2, C
respectively
• vIN is sampled at the falling edge of
φ1
– Sampling frequency fS
φ1
• Next, φ2 rises and the voltage across
C is transferred to vOUT φ2
• Why does this behave as a resistor?
T=1/fs
Switched-Capacitor Resistors
• Charge transferred from vIN to φ1 φ2
vOUT during each clock cycle is:
vIN vOUT
S1 S2
Q = C(vIN – vOUT)
C
• Average current flowing from
vIN to vOUT is:
i=Q/t = Q . fs φ1
Substituting for Q: φ2
i =fS C(vIN – vOUT) T=1/fs

Switched-Capacitor Resistors
i = fS C(vIN – vOUT) φ1 φ2
With the current through the switched- vIN vOUT

capacitor resistor proportional to the S1 S2
voltage across it, the equivalent
“switched capacitor resistance” is: C
Req = 1
f sC
Example: φ1
f s = 1MHz ,C = 1pF φ2
→ Req = 1Mega Ω T=1/fs
Switched-Capacitor Filter
REQ
• Let’s build a “switched- capacitor vIN vOUT
” filter …
• Start with a simple RC LPF C2

• Replace the physical resistor by
an equivalent switched-
capacitor resistor
φ1 φ2
• 3-dB bandwidth: vIN vOUT

C S1 S2
ω− 3dB = 1 = f s × 1
ReqC2 C2 C1 C2
C
f − 3d B = 1 f s × 1
2π C2

Switched-Capacitor Filters Advantage versus
Continuous-Time Filters
φ1 φ2 Req
Vin Vout
Vin Vout
S1 S2
C1 C2 C2
1 1
f −3dB = ×
f − 3dB = 1 f s × C1 2π ReqC2
2π C2
• Corner freq. proportional to: • Corner freq. proportional to:
System clock (accurate to few ppm) Absolute value of Rs & Cs
C ratio accurate à < 0.1% Poor accuracy à 20 to 50%
Ñ Main advantage of SC filtersà inherent corner frequency accuracy

Typical Sampling Process

Continuous-Time(CT) ⇒ Sampled Data (SD)
Continuous- time
Time Signal
Sampled Data
Sampled Data
+ ZOH
Clock

Uniform Sampling
Amplitude
Nomenclature:
x(kT) ≡ x(k)
Continuous time signal x(t) x(t)
Sampling interval T
Sampling frequency fs = 1/T
Sampled signal x(kT) = x(k)
• Problem: Multiple continuous time

signals can yield exactly the same
discrete time signal
T
• Let’s look at samples taken at 1µs
intervals of several sinusoidal
waveforms … time
Sampling Sine Waves

T = 1µs
fs = 1/T = 1MHz
fin = 101kHz
voltage
time
y(nT)
v(t) = sin [2π(101000)t]

Sampling Sine Waves
T = 1µs
fs = 1MHz
fin = 899kHz
voltage
time
v(t) = - sin [2π(899000)t]

Sampling Sine Waves

T = 1µs
fs = 1MHz
fin = 1101kHz
voltage
time
v(t) = sin [2π(1101000)t]

Sampling Sine Waves
Problem:
Identical samples for:
v(t) = sin [2π fint ]

v(t) = sin [2π( fin+fs )t ]
v(t) = sin [2π( fin-fs )t ]
àMultiple continuous time signals can yield

exactly the same discrete time signal
Sampling Sine Waves

Frequency Spectrum
Time domain
Voltage
fs = 1/T
y(nT)
time
Frequency domain
Before Sampling After Sampling
Amplitude
Amplitude
fs - fin fs + fin
899kHz 1101kHz
fin fs 2fs … f fin fs 2fs … f

1MHz 101kHz 1MHz
101kHz

Frequency Domain Interpretation
Amplitude
Frequency domain
Signal scenario
before sampling
fin fs /2 fs 2fs …….. f
Amplitude
Frequency domain
Signal scenario
after sampling &
filtering
fin fs /2 fs 2fs f
Key point: Signals @ nfS ± fmax__signal fold back into band of interest
àAliasing
Aliasing
• Multiple continuous time signals can

produce identical series of samples
• The folding back of signals from nfS±fsig
down to ffin is called aliasing
– Sampling theorem: fs > 2fmax_Signal
• If aliasing occurs, no signal processing
operation downstream of the sampling
process can recover the original
continuous time signal

How to Avoid Aliasing?
• Must obey sampling theorem:

fmax_Signal < fs/2
• Two possibilities:
1. Sample fast enough to cover all spectral
components, including "parasitic" ones
outside band of interest
2. Limit fmax_Signal through filtering
How to Avoid Aliasing?

1- Push
Amplitude
Frequency domain
sampling
frequency to x2
of the highest
freq. fin
à In most cases fs_old 2fs_old …….. fs_new f
not practical
2- Pre-filter
Amplitude
signal to Frequency domain

eliminate
signals above
fs/2 then sample fin fs /2 fs 2fs f

Anti-Aliasing Filter Considerations
Desired
Signal Brickwall
Band Anti-Aliasing Realistic
Pre-Filter Anti-Aliasing
Amplitude
Pre-Filter
Anti-Aliasing Switched-Capacitor
Filter Filter
0 fs/2 fs 2fs ... f

Case1- B= fmax _Signal = fs /2
• Non-practical since an extremely high order anti-aliasing filter (close to
an ideal brickwall filter) is required
• Practical anti-aliasing filter àNonzero filter "transition band"
• In order to make this work, we need to sample much faster than 2x the
signal bandwidth
à"Oversampling"
Practical Anti-Aliasing Filter

Desired
Signal Parasitic
Band Tone
Anti-Aliasing Switched-Capacitor
Filter Filter Attenuation
Case2 - B= fmax_Signal << fs/2 0 B fs/2 fs-B fs ... f

• More practical anti-aliasing filter
• Preferable to have an anti-
aliasing filter with:
àThe lowest order possible
0 B ... f
àNo frequency tuning required
(if frequency tuning is
required then why use
switched-capacitor filter, just
use the prefilter!?)

Tradeoff
Oversampling Ratio versus Anti-Aliasing Filter Order
Maximum
Aliasing
Dynamic
Range
Filter Order
fs /fin-max
* Assumptionà anti-aliasing filter is Butterworth type (not a necessary requirement)

àTradeoff: Sampling speed versus anti-aliasing filter order
Ref: R. v. d. Plassche, CMOS Integrated Analog-to-Digital and Digital-to-Analog Converters, 2nd
ed., Kluwer publishing, 2003, p.41]
Effect of Sample & Hold
... ... ... ...

Sample &
Hold
Ts Tp
Ts
•Using the Fourier transform of a rectangular impulse:
Tp sin(πfTp )
H( f ) =
Ts πfTp

Effect of Sample & Hold on
Frequency Response
1
0.9
T p sin(πfTp )
0.8 | H ( f ) |=
0.7
Tp=Ts Ts πfTp
More practical
abs(H(f))
0.6
0.5
Tp=0.5Ts
0.4
0.3
0.2
0.1
0
0 0.5 1 1.5 2 2.5 3
f / fs
Sample & Hold Effect

(Reconstruction of Analog Signals)
Time domain
Tp=Ts
voltage
Tp=Ts
time
ZOH
sin(π fTs )
Amplitude
Magnitude Frequency domain

H( f ) =
droop due π fTs
to sinx/x
effect fin 2fs …….. f
fs

Magnitude droop
due to sinx/x
effect: Time domain
Voltage
Case 1) fsig=fs /4 time
Amplitude
-1dB Frequency domain
Droop= -1dB
fin fs f

Time domain
Magnitude droop due 1
to sinx/x effect: 0.8
0.6
0.4
Case 2) 0.2
Amplitude
fsig=fs /32 -0.2
-0.4
-0.6
-0.8
sampled data
after ZOH
-1
0 0.5 1 1.5 2 2.5 3 3.5
Time -5
x 10
Amplitude
-0.0035dB
Droop= -0.0035dB Frequency domain
à High
oversampling ratio fin fs f
desirable

Sampling Process Including S/H
H(Z)
Sampler S/H
e.g. (S.C.F)
Vi
Time
Domain
t
Freq.
Domain
fin f fs 2fs fs 2fs fs 2fs
Freq.
Domain
General
Signal fB fs 2fs fs 2fs fs 2fs
1st Order Filter

Transient Analysis
SC response:
extra delay and steps with
Impractical finite rise time.
exaggerated
No problem

1st Order Filter
Transient Analysis
ZOH
• ZOH: Emulates an ideal S/Hà pick

signal after settling
(usually at end of clock phase)
• Adds delay and sin(x)/x distortion
• When in doubt, use a ZOH in
periodic ac simulations
Periodic AC Analysis

Magnitude Response
Sinc due to ZOH
RC filter
1. RC filter output
output 2. SC output after ZOH
3. Input after ZOH
4. Corrected output
Corrected output • (2) over (3)
no ZOH
• Repeats filter shape
around nfs
SC output • Identical to RC for
after ZOH
f <<fs/2
fs 2fs 3fs
Periodic AC Analysis
• SPICE frequency analysis
– ac linear, time-invariant circuits
– pac linear, time-variant circuits
• SpectreRF statements
V1 ( Vi 0 ) vsource type=dc dc=0 mag=1 pacmag=1
PSS1 pss period=1u errpreset=conservative
PAC1 pac start=1 stop=1M lin=1001
• Output
– Divide results by sinc(f/fs) to correct for ZOH distortion

Spectre Circuit File
rc_pac
simulator lang=spectre
ahdl_include "zoh.def"
S1 ( Vi c1 phi1 0 ) relay ropen=100G rclosed=1 vt1=-500m vt2=500m

S2 ( c1 Vo_sc phi2 0 ) relay ropen=100G rclosed=1 vt1=-500m vt2=500m
C1 ( c1 0 ) capacitor c=314.159f
C2 ( Vo_sc 0 ) capacitor c=1p
R1 ( Vi Vo_rc ) resistor r=3.1831M
C2rc ( Vo_rc 0 ) capacitor c=1p
CLK1_Vphi1 ( phi1 0 ) vsource type=pulse val0=-1 val1=1 period=1u
width=450n delay=50n rise=10n fall=10n
CLK1_Vphi2 ( phi2 0 ) vsource type=pulse val0=-1 val1=1 period=1u
width=450n delay=550n rise=10n fall=10n
V1 ( Vi 0 ) vsource type=dc dc=0 mag=1 pacmag=1
PSS1 pss period=1u errpreset=conservative
PAC1 pac start=1 stop=3.1M log=1001
ZOH1 ( Vo_sc_zoh 0 Vo_sc 0 ) zoh period=1u delay=500n aperture=1n tc=10p
ZOH2 ( Vi_zoh 0 Vi 0 ) zoh period=1u delay=0 aperture=1n tc=10p
ZOH Circuit File

// Copy from the SpectreRF Primer
// Implement switch with effective series
module zoh (Pout, Nout, Pin, Nin) (period, // resistence of 1 Ohm
delay, aperture, tc) if ( ($time() > start) && ($time() <= stop))
I(hold) <- V(hold) - V(Pin, Nin);
node [V,I] Pin, Nin, Pout, Nout; else
parameter real period=1 from (0:inf); I(hold) <- 1.0e-12 * (V(hold) - V(Pin, Nin));
parameter real delay=0 from [0:inf);
parameter real aperture=1/100 from (0:inf);
// Implement capacitor with an effective
parameter real tc=1/500 from (0:inf);
// capacitance of tc
{
integer n; real start, stop; I(hold) <- tc * dot(V(hold));
node [V,I] hold;
analog { // Buffer output
// determine the point when aperture V(Pout, Nout) <- V(hold);
begins
n = ($time() - delay + aperture) / period // Control time step tightly during
+ 0.5;
start = n*period + delay - aperture; // aperture and loosely otherwise
$break_point(start); if (($time() >= start) && ($time() <= stop))
$bound_step(tc);
// determine the time when aperture ends else
n = ($time() - delay) / period + 0.5; $bound_step(period/5);
stop = n*period + delay; }
$break_point(stop); }

First Order S.C. Filter
φ1 φ2
Vin Vout Vo
S1 S2
Vin
time
C1 C2
time
Antialiasing Pre-filter
f-3dB fs 2fs
Output Frequency Spectrum
Switched-Capacitor Filters à problem with aliasing
Sampled-Data Filters
Anti-aliasing Requirements
• Frequency response repeats at fs , 2fs , 3fs…..

• High frequency signals close to fs , 2fs ,….folds
back into passband (aliasing)
• Most cases must pre-filter input to a sampled-data
filter to remove signal at f > fs /2 (nyquist à fmax
< fs /2 )
• Usually, anti-aliasing filter included on-chip as
continuous-time filter with relaxed specs. (no
tuning)

Example : Anti-Aliasing Filter Requirements
f-3dB fs 2fs
• Voice-band SC filter f-3dB =4kHz & fs =256kHz

• Anti-aliasing filter requirements:
– Need 40dB attenuation at clock frequency
– Incur no phase-error from 0 to 4kHz
– Gain error 0 to 4kHz < 0.05dB
– Allow +-30% variation for anti-aliasing corner frequency (no
tuning)
Need to find minimum required filter order
Oversampling Ratio versus Anti-Aliasing Filter Order
Maximum
Aliasing
Dynamic
Range
Filter Order
fs/fin_max
* Assumptionà anti-aliasing filter is Butterworth type
à2nd order Butterworth

àNeed to find minimum corner frequency for mag. droop < 0.05dB

Example : Anti-Aliasing Filter Specifications
• Normalized frequency for
0.05dB droop: need perform
passband simulationà 0.34à
4kHz/0.34=12kHz
• Set anti-aliasing filter corner
frequency for minimum corner
frequency 12kHz à Nominal
Stopband Attenuation dB
corner frequency
12kHz/0.7=17.1kHz
• Check if attenuation requirement
is satisfied for widest filter
bandwidth à
17.1x1.3=22.28kHz
• Normalized filter clock
frequency to max. corner freq.
à256/22.2=11.48à make sure
enough attenuation Νοrmalized ω
• Check phase-error within 4kHz From: Williams and Taylor, p. 2-37
bandwidth: simulation
Example : Anti-Aliasing Filter

f-3dB fs 2fs
• Voice-band SC filter f-3dB =4kHz & fs =256kHz

• Anti-aliasing filter requirements:
– Need 40dB attenuation at clock freq.
– Incur no phase-error from 0 to 4kHz
– Gain error 0 to 4kHz < 0.05dB
– Allow +-30% variation for anti-aliasing corner frequency (no
tuning)
à2-pole Butterworth LPF with nominal corner freq. of 17kHz & no
tuning (12kHz to 22kHz corner frequency )

Summary
• Sampling theorem à fs > 2fmax_Signal
• Signals at frequencies nfS± fsig fold back down to desired signal
band, fsig
à This is called aliasing & usually dictates use of anti-aliasing
pre-filters
• Oversampling helps reduce required order for anti-aliasing filter
• S/H function shapes the frequency response with sinx/x
à Need to pay attention to droop in passband due to sinx/x
• If the above requirements are not met, CT signal can NOT be
recovered from SD or DT without loss of information
Switched-Capacitor Noise
• Resistance of switch S1 φ1 φ2
produces a noise voltage on C
with variance kT/C vIN vOUT
S1 S2
• The corresponding noise charge C
is Q2=C2V2=kTC
• This charge is sampled when S1

opens
φ1
φ2
T=1/fs

φ1 φ2
• Resistance of switch S2
contributes to an
uncorrelated noise charge vIN vOUT
S1 S2
on C at the end of φ2
C
• Mean-squared noise charge
transferred from vIN to vOUT
each sample period is
Q2=2kTC φ1
φ2
T=1/fs
• The mean-squared noise current due to S1 and S2’s kT/C noise is :
i = (Q fs ) = 2kBT C fs
2 2 2
• This noise is approximately white and distributed between 0 and fs/2

(noise spectra à single sided by convention)
The spectral density of the noise is:
2 2
i 2k BT C fs 4k BT 1
= = 4k BT C fs = using RE Q =
∆f fs c
RE Q fsC
2
à S.C. resistor noise equals a physical resistor noise with
same value!

Periodic Noise Analysis
Sampling Noise from SC S/H
Netlist Netlist
ahdl_include "zoh.def" simOptions options reltol=10u vabstol=1n iabstol=1p
Vclk
100ns
Vrc Vrc_hold
100kOhm
R S1
PNOISE Analysis PNOISE1
sweep from 0 to 20.01M (1037 steps)
ZOH1
C
T = 100ns
1pF
SpectreRF PNOISE: check

100kOhm
R1 noisetype=timedomain
Voltage NOISE
noisetimepoints=[…] VNOISE1
C1
1pF as alternative to ZOH.
noiseskipcount=large
might speed up things in this case.
PSS pss period=100n maxacfreq=1.5G errpreset=conservative
PNOISE ( Vrc_hold 0 ) pnoise start=0 stop=20M lin=500 maxsideband=10
Sampled Noise Spectrum
Density of sampled noise Sampled noise normalized

including sinc distortion density corrected for sinc
distortion

Total Noise
Sampled noise in
0 … fs/2: 62.2µV rms
(expect 64µV for 1pF)
Switched-Capacitor Integrator
-
φ1
+
∫
φ2
CI T=1/fs
φ1 φ2
Vin
- for fsignal << fsampling
Cs Vo
f s ×Cs
∫Vin dt
+
→ V0 =
CI
Cs
ω0 = f s × C
I
Main advantage: No tuning needed
à critical frequency function of ratio of caps & clock freq.

CI
φ1 φ2 φ1
Vin
-
φ2
Cs Vo
+ T=1/fs
CI CI
φ1 φ2
Vin Vin
- -
Cs
Cs Vo
+ Vo
+
φ1 High φ2 High
à Cs Charged to Vin àCharge transferred from Cs to CI
Continuous-Time versus Discrete Time Design Flow
Continuous-Time Discrete-Time
• Write differential equation • Write difference equation à relates

output sequence to input sequence
• Laplace transform (F(s))
• Let s=jω à F(j ω) Vo ( n Ts ) = Vi [( n − 1)Ts ] − ..........
• Use delay operator Z -1 to
• Plot |F(jω)|, phase(F(jω) transform the recursive realization
to algebraic equation in Z domain
Vo ( Z ) = Z − 1Vi ( Z ) .......
• Set Z= e jωT
• Plot mag./phase versus frequency

CI
φ1 φ2
Vin Vs
-
Cs Vo
+
φ1 φ2 φ1 φ2 φ1 Clock
Vin
Vs
Vo
(n-3/2)Ts (n-1)Ts (n-1/2)Ts nTs (n+1)Ts
Vin
Vs
Vo
Φ1 à Qs [(n-1)Ts]= Cs Vi [(n-1)Ts] , QI [(n-1)Ts] = QI[(n-3/2)Ts]

Φ2 à Qs [(n-1/2) Ts] = 0 , QI [(n-1/2) Ts] = QI [(n-1) Ts] + Qs [(n-1) Ts]
Φ1 _à Qs [nTs ] = Cs Vi [nTs ] , QI [nTs ] = QI[(n-1) Ts ] + Qs [(n-1) Ts]
Since Vo= - QI /CI & Vi = Qs / Cs à CI Vo(nTs) = CI Vo [(n-1) Ts ] -Cs Vi [(n-1) Ts ]

Discrete Time Design Flow
• Transforming the recursive realization to algebraic

equation in Z domain:
– Use Delay operator Z :
nTs .....................→ 1
( n − 1)Ts  .............→ Z − 1
 
( n − 1/ 2 )Ts  ..........→ Z − 1/ 2
 
( n + 1)Ts  .............→ Z + 1
 
( n + 1/ 2 )Ts  ..........→ Z + 1/ 2
 
CI
φ1 φ2
Vin
- φ1
Cs Vo
+
− CI Vo( n Ts ) = −CI Vo ( n − 1)Ts  + Cs Vin ( n − 1)Ts 

Vo ( n Ts ) =Vo ( n − 1)Ts  − C
Cs V ( n − 1)T 
in  s
I
Vo( Z ) = Z − 1Vo( Z ) − Z − 1 C
Cs V ( Z )
in
I
Vo Cs × Z − 1
( Z )= −C
Vin I 1− Z − 1
DDI (Direct-Transform Discrete Integrator)

z-Plane Characteristics
• Consider variable Z=esT for any s in left-half-plane

(LHP):
S= - a+jb
Z= e-aT . e jbT = e-aT (cosbT + jsin bT)
|Z|= e-aT , angle(Z)= bT
à For values of S in LHP |Z|<1
à For a =0 (imag. axis in s-plane) |Z|=1 (unit circle)
if angle(Z)=π=bT then b=π/T=ω
Then ω=ωs/2
z-Domain Frequency Response

• LHP singularities in s- Z plane imag. axis in
plane map into inside of s domain
unit-circle in Z domain
• RHP singularities in s-
plane map into outside of
unit-circle in Z domain
• The jω axis maps onto the
unit circle
LHP in s domain

(cos(ωT),sin(ωT))
• Particular values:
– f=0 à z=1
– f = fs/2 à z = -1
• The frequency response is
obtained by evaluating f = fs/2
H(z) on the unit circle at f=0
z = ejωT = cos(ωT)+jsin(ωT)
• Once z=1 (fs/2) is reached,
the frequency response
repeats, as expected

(cos(ωT),sin(ωT))
• The angle to the pole
is equal to 360° (or
2π radians) times the
ratio of the pole
frequency to the 2πf
f = fs/2 fS
sampling frequency
f=0

DDI Integrator
Pole-Zero Map in z-Plane
Z-1=0 à Z=1
f z-plane
on unit circle
Pole from fà0

in s-plane mapped to f1
z=+1 increasing
(Z-1)
As frequency f = fs/2
increases z domain 1
pole moves on unit
circle (CCW)
Once pole gets to (Z=-

1 ),(f=fs /2), frequency
response repeats
DDI Switched-Capacitor Integrator

CI
φ1 φ2
- φ1
Vin Vo
Cs ( ω ) = − Cs × 1
CI 
+
Vo Vin ( jωT )2 + ( jωT )3 + .... −1
1+ jωT + 
2! 3!
 
Vo C −1 C
= − s × 1
(Z)= − s × Z
CI 1 − Z − 1 CI
jωT −
(ωT )2 + (ωT )3 + ....
Vin 2! 3!
for ωT < < 1
( Z ) = − s × 1 , Z = e jωT
Vo C
CI Z − 1 Vo
( ω ) = − Cs × 1
Vin CI jωT
Vin
C
=− s × 1 = S i n c e T = 1 / fs
CI e jωT − 1
Vo f
(ω ) = − s × s = − 1
C
S e r i e s e x p a n s i o n f o r ex CI s CI Re q s
2 3 4 Vin
e x = 1 + x + x + x + x ..... → ideal integrator
2! 3! 4!

CI
φ1 φ2
Vin
- φ1
Cs Vo
+
Vo ( Z ) = − Cs × Z − 1 , Z = e jωT
CI 1− Z − 1
Vin
Cs Cs − jωT / 2
= C × 1 = C × − jωeT / 2 jωT / 2
I 1− e jωT I e −e
Cs
= − jC × e− jωT / 2 × 1
I 2sin (ωT / 2 )
Cs 1
= −C × ωT / 2 × e− jωT / 2
I jωT sin (ωT / 2 )
Error
Ideal Integrator) Magnitude Error Phase

CI
φ1 φ2
Vin
- φ1
Cs Vo
+
Vo ( Z ) = − Cs 1 × ωT / 2 × e− jωT / 2
CI jωT s i n (ωT / 2 )
Vin
Error
Ideal Integrator) Magnitude Error Phase
Example: Mag. & phase error for:

1- f / fs=1/12 à Mag. Error = 1% or 0.1dB
Phase error=15 degree
Qintg = -3.8
DDI Integrator
2- f / fs=1/32 à Mag. Error=0.16% or 0.014dB
à magnitude error no problem
Phase error=5.6 degree
phase error major problem
Qintg = -10.2

Switched Capacitor Filter
Build with DDI Integrator
jω
jω
ωs
s-plane s-plane
Coarse View Fine View
σ σ
Example: 5th Order

Elliptic Filter
Singularities pushed Pole
-ωs towards RHP due to Zero
integrator excess phase
Switched Capacitor Filter

Build with DDI Integrator
H ( jω ) Passband
Peaking
SC DDI based
Filter
Zeros lost!
fs / 2 fs
Frequency (Hz) 2fs f
Continuous-Time
Prototype

Modified Switched-Capacitor Integrator
CI CI
φ1 φ2 φ1 φ2
Vin
- φ1 Vin
- φ2
Cs Vo Cs Vo
+ +
DDI Integrator LDI Integrator
Sample output ½ clock cycle earlier

à Sample output on φ2
(n-3/2)Ts (n-1)Ts (n-1/2)Ts nTs (n+1)Ts
Vin
Vs
Vo
Φ1 à Qs [(n-1)Ts]= Cs Vi [(n-1)Ts] , QI [(n-1)Ts] = QI[(n-3/2)Ts]

Φ2 à Qs [(n-1/2) Ts] = 0 , QI [(n-1/2) Ts] = QI [(n-3/2) Ts] + Qs [(n-1) Ts]
Φ1 _à Qs [nTs ] = Cs Vi [nTs ] , QI [nTs ] = QI[(n-1) Ts ] + Qs [(n-1) Ts]
Φ2 à Qs [(n+1/2) Ts] = 0 , QI [(n+1/2) Ts] = QI [(n-1/2) Ts] + Qs [n Ts]

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EE247

EECS 247 Lecture 9: Switched-Capacitor Filters © 2005 H.K. Page 1

EECS 247 Lecture 9: Switched-Capacitor Filters © 2005 H.K. Page 3

EECS 247 Lecture 9: Switched-Capacitor Filters © 2005 H.K. Page 4

With the current through the switched- vIN vOUT

→ Req = 1Mega Ω T=1/fs

EECS 247 Lecture 9: Switched-Capacitor Filters © 2005 H.K. Page 5

• Start with a simple RC LPF C2

• 3-dB bandwidth: vIN vOUT

EECS 247 Lecture 9: Switched-Capacitor Filters © 2005 H.K. Page 6

Ñ Main advantage of SC filtersà inherent corner frequency accuracy

Typical Sampling Process

EECS 247 Lecture 9: Switched-Capacitor Filters © 2005 H.K. Page 8

• Problem: Multiple continuous time

EECS 247 Lecture 9: Switched-Capacitor Filters © 2005 H.K. Page 9

Sampling Sine Waves

v(t) = sin [2π(101000)t]

EECS 247 Lecture 9: Switched-Capacitor Filters © 2005 H.K. Page 10

v(t) = - sin [2π(899000)t]

Sampling Sine Waves

v(t) = sin [2π(1101000)t]

Identical samples for:

v(t) = sin [2π fint ]

àMultiple continuous time signals can yield

EECS 247 Lecture 9: Switched-Capacitor Filters © 2005 H.K. Page 13

Sampling Sine Waves

fin fs 2fs … f fin fs 2fs … f

EECS 247 Lecture 9: Switched-Capacitor Filters © 2005 H.K. Page 14

• Multiple continuous time signals can

EECS 247 Lecture 9: Switched-Capacitor Filters © 2005 H.K. Page 16

• Must obey sampling theorem:

EECS 247 Lecture 9: Switched-Capacitor Filters © 2005 H.K. Page 17

How to Avoid Aliasing?

signal to Frequency domain

EECS 247 Lecture 9: Switched-Capacitor Filters © 2005 H.K. Page 18

0 fs/2 fs 2fs ... f

EECS 247 Lecture 9: Switched-Capacitor Filters © 2005 H.K. Page 19

Practical Anti-Aliasing Filter

Case2 - B= fmax_Signal << fs/2 0 B fs/2 fs-B fs ... f

EECS 247 Lecture 9: Switched-Capacitor Filters © 2005 H.K. Page 20

* Assumptionà anti-aliasing filter is Butterworth type (not a necessary requirement)

EECS 247 Lecture 9: Switched-Capacitor Filters © 2005 H.K. Page 21

Effect of Sample & Hold

... ... ... ...

•Using the Fourier transform of a rectangular impulse:

EECS 247 Lecture 9: Switched-Capacitor Filters © 2005 H.K. Page 22

EECS 247 Lecture 9: Switched-Capacitor Filters © 2005 H.K. Page 23

Sample & Hold Effect

Magnitude Frequency domain

EECS 247 Lecture 9: Switched-Capacitor Filters © 2005 H.K. Page 24

EECS 247 Lecture 9: Switched-Capacitor Filters © 2005 H.K. Page 25

Sample & Hold Effect

to sinx/x effect: 0.8

fsig=fs /32 -0.2

EECS 247 Lecture 9: Switched-Capacitor Filters © 2005 H.K. Page 26

EECS 247 Lecture 9: Switched-Capacitor Filters © 2005 H.K. Page 27

1st Order Filter

EECS 247 Lecture 9: Switched-Capacitor Filters © 2005 H.K. Page 28

• ZOH: Emulates an ideal S/Hà pick

EECS 247 Lecture 9: Switched-Capacitor Filters © 2005 H.K. Page 29

EECS 247 Lecture 9: Switched-Capacitor Filters © 2005 H.K. Page 30

Sinc due to ZOH

EECS 247 Lecture 9: Switched-Capacitor Filters © 2005 H.K. Page 31

EECS 247 Lecture 9: Switched-Capacitor Filters © 2005 H.K. Page 32