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Part I Q 1.1
Block diagrams and expression for feedback factor (β) and transfer gain (A):
Voltage Series
𝑉𝑉𝑓𝑓
𝛽𝛽 =
𝑉𝑉𝑜𝑜
Current series
𝑉𝑉𝑓𝑓
𝛽𝛽 =
𝐼𝐼𝑜𝑜
(0.25 pt)
(0.5 pt) 𝐼𝐼𝑜𝑜
𝐴𝐴 =
𝑉𝑉𝑖𝑖
Current shunt
𝐼𝐼𝑓𝑓
𝛽𝛽 =
𝐼𝐼𝑜𝑜
(0.25 pt)
(0.5 pt) 𝐼𝐼𝑜𝑜
𝐴𝐴 =
𝐼𝐼𝑖𝑖
Voltage shunt
𝐼𝐼𝑓𝑓
𝛽𝛽 =
𝑉𝑉𝑜𝑜
(0.5 pt) (0.25 pt)
𝑉𝑉𝑜𝑜
𝐴𝐴 =
𝐼𝐼𝑖𝑖
Part I Q 1.2
Definition of the most useful characteristics of an ideal op amp
1. Input impedance: Ratio of input voltage to input current
2. Output impedance: Ratio of output voltage to output current
3. Open loop gain: Ratio between the output signal to input signal of op-amp without feedback
4. Bandwidth: the range of frequency within which the op-amp can operate relatively with constant
gain
5. CMMR: the ratio between the differential mode gain and the common mode gain of an op-amp
Transfer characteristics: the relationship of the output voltage to the input voltage
7. Input offset voltage: the dc voltage applied at the two input terminals of an op-amp to balance the
amplifier (Vo=0).
8. Output offset voltage: The dc voltage at the output terminal of the op-amp without input signal.
9. Input offset current: The difference current amount between the two input terminal currents of a
balanced op-amp.
𝐼𝐼𝑖𝑖𝑖𝑖 = 𝐼𝐼𝐵𝐵1 − 𝐼𝐼𝐵𝐵2 |𝑉𝑉𝑜𝑜 =0
10. Input bias current: The average current of the separate dc currents entering the two terminals of a
balanced op-amp.
𝐼𝐼𝐵𝐵1 + 𝐼𝐼𝐵𝐵2
𝐼𝐼𝐵𝐵 = �
2 𝑉𝑉𝑜𝑜 =0
11. Slew rate: The maximum time rate of change of the closed loop op-amp output voltage under the
large signal condition.
∆𝑉𝑉
�𝑆𝑆𝑆𝑆 = �� 𝑖𝑖𝑖𝑖 𝑣𝑣�𝜇𝜇𝜇𝜇
∆𝑡𝑡 𝑚𝑚𝑚𝑚𝑚𝑚
Comparison of ideal op-amp with practical op-amp characteristics:
Characteristics Ideal Op-amp Practical Op-amp
V1
Additional Buffer & Output
Diff-Amp Vo
Gain Amp Level shifter driver
V2
Differential amplifier: serves as the input stage to provide the inverting and non inverting inputs
with high input impedance. (1/4)
Additional gain stage: provides more gain to an op-amp by achieving the low output impedance
through the emitter follower stage. (1/4)
Buffer and level shifter stage: is used to adjust the DC voltage so that the output voltage signals
are referred at ground. (1/4)
Output Driver Stage: Serves as an output stage to develop the output signals to drive the external
load. (1/4)
Part I Q 1.4
High CMRR is required for an op-amp because CMRR is a convenient measure of amplifier’s
performance by accurately ---- or reject signals that are common to both inputs, so that no common
mode components appear at the output. (1pt)
Part II Q-1
(a) Topology:
Setting I o =0 or open circuiting the output terminal causes the feedback current to be
zero. Hence, the sampled signal is current. In addition to this, if one short circuit the
input of the first transistor, all the current coming from the input will flow through
the feedback resistor; consequently, we can realize that the sampled signal is mixed
with the input signal in the form of current (shunt). Therefore, the feedback is
current-shunt. (0.5 pt)
Input Circuit:
Output Circuit:
If we let V i =0 (short circuit the base of the first transistor), causes R f to appear in
parallel with R e2 (see figure 1.1).
Note that we should use current source for the feedback is current-shunt.
The small signal model of the basic amplifier is shown in fig 1.1.
hie2 Io
hfe1Ib1 RC1 hfe2Ib2
R1||R2
Is RS RF hie1
RC2 (0.5 pt)
Re2 RB2
Re2 RF
(0.5 pt) IF
𝑅𝑅 𝑒𝑒2
− 𝐼𝐼
𝑅𝑅 𝑒𝑒2 +𝑅𝑅 𝐹𝐹 0 𝑅𝑅𝑒𝑒2
𝛽𝛽 = = − 𝑅𝑅 (0.25 pt)
𝐼𝐼0 𝑒𝑒2 +𝑅𝑅 𝐹𝐹
2.2
𝛽𝛽 = − 2.2+1.2 = −0.65 (0.25 pt)
−𝑅𝑅𝑐𝑐1 𝑅𝑅𝐵𝐵1
𝐴𝐴 = ℎ𝑓𝑓𝑓𝑓 2 . � � . ℎ𝑓𝑓𝑓𝑓 1 . � �
𝑅𝑅𝑐𝑐1 + 𝑅𝑅𝐵𝐵2 𝑅𝑅𝐵𝐵1 + ℎ𝑖𝑖𝑖𝑖1
Where
(0.25 pt)
𝑅𝑅𝐵𝐵1 = 𝑅𝑅𝑆𝑆 ||(𝑅𝑅𝐹𝐹 + 𝑅𝑅𝑒𝑒2 )||𝑅𝑅1 ||𝑅𝑅2 and
Thus,
1.2∗2.2
𝑅𝑅𝐵𝐵2 = 12 ∗ 120 + 120 �1.2+2.2 𝑘𝑘� = 94.62𝑘𝑘𝛺𝛺 (0.25 pt)
3 0.48
𝐴𝐴 = 120 ∗ �− 3+94.62 � ∗ 120 ∗ �0.48+1.44 � = −108 (0.5 pt)
Desensitivity factor
io
R1=22kΩ
Q3 + +12 V
0.7 v
-
R3 = 2.2kΩ i R2 = 2.7kΩ
-12 V
The current due to the constant current source circuit shown above is calculated as follows:
𝑅𝑅2 2.7𝑘𝑘
𝑉𝑉𝑅𝑅2 = ∗ 24 = ∗ 24 𝑣𝑣 = 2.62 𝑣𝑣
𝑅𝑅1 + 𝑅𝑅2 22𝑘𝑘 + 2.7𝑘𝑘
25𝑚𝑚𝑚𝑚 25𝑚𝑚𝑚𝑚
𝑟𝑟𝑒𝑒1 = 𝑟𝑟𝑒𝑒2 = = = 57.47Ω
𝑖𝑖𝑜𝑜 ⁄2 0.435𝑚𝑚𝑚𝑚
And
1 1
𝑔𝑔𝑚𝑚 1 = 𝑔𝑔𝑚𝑚 2 =
= = 0.0174 𝑆𝑆
𝑟𝑟𝑒𝑒 57.47
The small signal equivalent circuit of the above figure is as shown below:
RC1 RC2
Vo1 Vo2
+ Vo +
βre1 V1 gm1V1 gm2V2 V2 βre2
V1 - - V2
E
a. From the small signal equivalent circuit the output differential voltage is calculated as:
Hence,
RC1
Vo1
+
βre1 V1 gm1V1
-
Vcm
c. CMRR
𝑉𝑉𝑜𝑜 3.48𝑣𝑣
𝐴𝐴𝑑𝑑 = = = 1740
𝑉𝑉𝑑𝑑 2𝑚𝑚𝑚𝑚
𝐴𝐴𝑐𝑐𝑐𝑐 = 0
Hence,
𝐴𝐴𝑑𝑑 (1 pt)
𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶 = =∞
𝐴𝐴𝑐𝑐𝑐𝑐
Part II Q3
Rf
10 MΩ
Vin1 R1
-
1 mV 10 kΩ
R2 V’2 +
+ VO
-
20 kΩ
R3 30 kΩ
Vin2 4 mV
First, setting 𝑉𝑉2 to be zero we have an inverting amplifier with output given by
𝑅𝑅𝑓𝑓 10𝑀𝑀
𝑉𝑉𝑜𝑜1 = − 𝑅𝑅 𝑉𝑉𝑖𝑖𝑖𝑖 1 = − ∗ 1𝑚𝑚𝑚𝑚 = 1𝑣𝑣 (1 pt)
1 10𝑘𝑘
Next, by setting only 𝑉𝑉1 equal to zero, the circuit now resembles a non inverting amplifier whose
output is given by
𝑅𝑅𝑓𝑓 ′
𝑉𝑉𝑜𝑜2 = �1 + � 𝑉𝑉
𝑅𝑅1 2
Where, 𝑉𝑉2 ′ is the effective voltage at the non inverting input, which is equal to:
𝑅𝑅3 30𝑘𝑘
𝑉𝑉2 ′ = 𝑉𝑉𝑖𝑖𝑖𝑖 2 = ∗ 4𝑚𝑚 = 2.4𝑚𝑚𝑚𝑚
𝑅𝑅2 + 𝑅𝑅3 20𝑘𝑘 + 30𝑘𝑘
10𝑀𝑀
𝑉𝑉𝑜𝑜2 = �1 + �∗ 2.4𝑚𝑚𝑚𝑚 = 2.404𝑣𝑣
10𝑘𝑘 (1 pt)
The resulting output signal from both signal sources simultaneously is the sum of the two.
Therefore:
𝑉𝑉𝑜𝑜 = 𝑉𝑉𝑜𝑜1 + 𝑉𝑉𝑜𝑜2 = 1𝑣𝑣 + 2.404𝑣𝑣 = 3.404𝑣𝑣 (1 pt)