Name: Anuj Engineer SAP ID: 60001170004 Subject: A&M Vlsi Index

Name: ANUJ ENGINEER SAP ID: 60001170004 SUBJECT : A&M VLSI
NAME: ANUJ ENGINEER

SAP ID: 60001170004
SUBJECT: A&M VLSI
INDEX
Page
No. Experiment Date
No.
1 Characteristics Behaviour of VGS in NMOS 5-3-2021 1
Second Order Effects on CS NMOS

2 12-3-2021 8
Configuration
3 Basic and Cascode Current Mirror 19-3-2021 13
4 Voltage Independent Current Biasing 9-4-2021 18
5 CS Amplifier with RD and Diode Load 9-4-2021 23
CS Amplifier with Source Degeneration and

6 9-4-2021 29
Constant Current Source
Seminar: An Experimental Analog VLSI
7 Neural Chip with On-Chip Back-Propagation 27-3-2021 32
Learning
Name: ANUJ ENGINEER SAP ID: 60001170004 SUBJECT: A&M VLSI
EXPERIMENT no.1
Objective: For an NMOS device considering Level–1 SPICE simulation

model,simulate for the characteristic behaviour of drain current Id for various
values of the gate source voltage Vgs. Verify the circuit behaviour in the three
regions of operation.
Observations:
1) Observe the Id relationship in light of the threshold voltage for Level 1
model to be 0.7 volt.
2) Record the observed readings for Id max for at least three distinct values of
Vgs and compare the same with theoretical values.
3) Discuss and describe the various level -1 model spice parameters used
above, along with their variations with Process(P), supply
voltage(V) and temperature(T).
Theory: Derive from first principle the drain current Id relationship and explain
the three regions of operation. Circuit hand-drawn Print: graphs output.
To obtain current drain expression and its relation with voltage we first make two
considerations. First consider a semiconductor bar carrying a current I(Fig.1). if the
charge density along with direction of current is Qd coulombs perimeter and
velocity of charge is v meters per second, then. With a velocity v, all of the charges
enclosed in v meters of the bar must flow through the cross section in one
second(Fig.2)
I = Qdv………...(1.1)
Fig.1 Fig.2
Images from rizavi
1
Second, consider an NFET whose source and drain are connected to gnd(Fig.3).
Since we assume the onset of inversion occurs at Vgs = Vth. the inversion charge
density produced by the gate oxide capacitance is proportional to Vgs-Vth. For
Vgs≥Vth, yields a uniform channel charge density
Qd= WCox(Vgs-Vth).......(1.2)
CoxW ➡ total capacitance per unit length.
Fig.3(Images from rizavi)

As depicted in Fig.4 , the drain voltage is greater than zero. Since the channel
potential varies from zero at source to Vd at the drain, the local voltage difference
between the gate and the channel varies from Vg to Vg-Vd, this the charge density
at a point x along the channel can be written as.
Qd(x)=WCox(Vgs-V(x)-Vth).......(1.3)
V(x)➡ channel potential at x
From this
Id= -WCox(Vgs-V(x)-Vth)v.......(1.3)
v➡ velocity of the electron.
v=μE, where μ is the mobility of charge and E is the electric field.
E(x) = -dV/dx and representing the mobility of electrons μn
∫ Iddx = ∫ -WCox(Vgs-V(x)-Vth)dv…..(1.3.1)
Id= μnCox(W/L)[(Vgs-Vth)Vds-0.5Vds2].....(1.4)
2
Triode region

Fig.5 Plots the parabolas given by (1.4) for different values of Vgs, indicating that
the “Current capability” of the device increases wh=ith Vgs. calculating ∂Id/∂V ds,
the reader can show that the peak of each parabola occurs at V ds= Vgs-Vth and the
peak current is
ID,max=0.5 μnCox(W/L)[Vgs-Vth]2…..(1.5)
We call Vgs-Vth the “overdrive voltage” and W/L the “aspect ratio”. If Vds≤Vgs-
Vth we can the device operates in the triode region.
Equation 1.4 and 1.5 serve as the foundation of analog Cmos design, describing the
dependence of Id upon the constant of the technology, μ nCox, the device
dimensions,W and L, and the gate and drain potentials with respect to the source.
3
Note that the integration in 1.3.1 assumes μ n and Vth are independent of x and the
gate and drain voltages.
In 1.4 Vds<< 2(Vgs-Vth), we have
Id≈ μnCox(W/L)[Vgs-Vth]Vds….(1.6)
Drain current is a linear function of Vds. each parabola can be approximated by a
straight line.
When drain source voltage exceeds Vgs-Vth. In fact, as shown in Fig.6

Id becomes relatively constant and we say the device operates in the saturation
region.
Considering equation 1.3 that the local density of inversion layer charge is
proportional to Vgs-V(x)-Vth. Thus if V(x) approaches Vgs-Vth, then Q d(x) drops
to zero. In other words, as depicted in Fig.7 if Vds is slightly greater than Vgs-Vth,
then the inversion layer stops at x≤L.
4
1.Observation
From the above data in composite.txt we can see the value of Vth(VTO) as 0.7 and
it's relation with ID is given in relation of.
1 W
ID = 2 un COX L ( VGS – VTH )2
In this equation we see that the value of I D is dependent on the value of threshold
voltage and voltage across gate and source.
W/L is the ratio of width and length.
2.Observation.
We are considering 3 values of VGS and VTH as 0.7
From graph.
No. VGS VDS=VGS-VTH ID
1 1V 1 - 0.7 = 0.3 V 61.76 μA
2 2V 2 - 0.7 = 1.3 V 1.2848 mA
3 3V 3 - 0.7 = 2.3 V 4.377 mA
The value of ID is given by

1 W
ID = 2 un COX L ( VGS – VTH )2
5
Where the value of un = 0.035

ε o ε r 8.854 ×10−12 ×3.9
where; COX = T =
−3
−9
=3.8367 ×10
ox 9 ×10
1 1000 u
−3 −3
( )
Hence; ID = 2 ×35 ×10 × 3.8367 ×10 × 100 u ( V GS −0.7 )
2
From theoretical calculation

No. VGS VDS=VGS-VTH ID
1 1V 1 - 0.7 = 0.3 V 60.42 μA
2 2V 2 - 0.7 = 1.3 V 1.134 mA
3 3V 3 - 0.7 = 2.3 V 3.551 mA
3.Observation
Level 1 spice model
parameter unit Description
VTO- zero bias threshold V 1. This voltage is needed to turn the
voltage MOSFET on for operating in linear
and saturation regions.
2. The value of this parameter is
affected due to variation in
temperature only as change in the
process or supply voltage or length
of the channel does not affect it
3. Temperature and VTO are inversely
proportional where if the
temperature increases, then the VTO
decreases which allows a leakage
current to flow through the device
6
which can damage the said device

at higher temperatures.
TOX- gate oxide thickness m 1. Gate Oxide layer is a thin insulating
layer of silicon dioxide formed by
thermal oxidation of silicon of the
channel.
2. It is developed to separate the gate
terminal from drain and source
terminals of MOSFET.
3. The value of this parameter cannot
be altered by the user as it is
determined during the
manufacturing of the device.
COX- oxide capacitance per F/m2 1. Gate oxide layer can be assumed to
unit gate area be a parallel plate capacitor where
the gate oxide capacitance is the
capacitance of the oxide layer per
unit area.
2. Here, the value of capacitance
changes with variation in the gate
voltage applied to the gate.
3. This happens due to band bending
in Si substrate and variation in
charge concentration at Si-SiO2
interface.
4. The capacitance can also be varied
at various temperatures and at
higher and lower frequencies.
U0- channel mobility cm2/V/ 1. Channel mobility describes how

s fast the electron/hole can move
through a conductor or a
semiconductor under the influence
of an electric field.
7
2. It gives the relation between drift

velocity of electrons or holes and an
applied electric field in a solid, is
given by; vd = U0*E.
3. The mobility decreases with
temperature increasing because
more carriers are present and have
more energy at high temperature to
vibrate and collide.
Simulation output and circuit diagram :-

Circuit description :- this spice model level 1 circuit in this circuit we are varying
the value of V1 and V2. to find the relation between Id and Vds
8
Conclusion:-We have calculated the value of ID and the factors on which it

depends by simulating the circuit on LT Spice.
9
Experiment no.2
Objective: For an NMOS device in Common Source configuration, verify the
output characteristics (ID v/s VDS for various values of VGS) in light of second order
effects;
1. Channel Length Modulation
2. Body effect
Thus, considering Level – 1 SPICE simulation model for the device, verify the
quantifying parameters (lambda) for channel length modulation and (gamma) for
body effect.
Theory:Every action has a consequence, and each consequence has another

consequence. These are called Second-Order Effects. Every change you make to a
system will have Second-Order Effects, which may affect the system's
functionality. Be careful when making changes, they may have the opposite effect
of what you aimed for.
Channel Length Modulation: actual length of the inverted channel gradually

decreases as the potential difference between the gate and the drain increases.
In the above equation L’ is in fact a function of V DS . This effect is called channel

length modulation.
Because of channel length modulation we can see that the ID is not constant and it's
gradually varying even in the saturation region.
Body bias effect: what happens if the bulk voltage of an NFET drops below the
source voltage?fig2.2 Since the S and D junctions remain reverse-biased, we
10
surmise that the device continues to operate properly but certain characteristics
may change.
To understand the effect, suppose Vs =Vd = 0 and Vg is somewhat less than Vth
so that the depletion region is formed under the gate but no inversion layer exists.
As Vb becomes more negative, more holes are attracted to the substrate
connection,leaving a larger negative charge behind.fig2.3
fig2.2
Fig 2.3
The depletion region becomes wider, as threshold voltage is a function of the total
charge in the depletion region because the gate charge must mirror Q d before an
inversion layer is formed. Thus , as Vb drops and Qd increases, Vth also increases.
This is called the body effect
Observation:
11
From the above image we can see the value of lambda as 0.1 and gamma as 0.45.
channel length modulation:
The expected value of lambda is 0.1
Now to find the value of lambda, we will use the formula:
∂V DS 1
ro = =
∂ ID λI D
Here, VDS = VGS – VTH = VGS – 0.7
Hence, lambda λ is expressed as:

1
λ=
ro I D
Expected value of lambda asper the level 1 spice model 0.1

Saturation values as follows:
for VDS =0.3 , ID =62.43uA
for VDS =1.3 , ID =1.284mA
for VDS =2.3 , ID =4.377mA
VGS VDS VDS ID ro λ
[saturation]
1V 0.3 V 0.5V 63.54uA 156kΩ 0.102
0.6V 64.18uA
2V 1.3 V 1.5V 1.308mA 10kΩ 0.077
1.6V 1.318mA
3V 2.3 V 2.5V 4.44mA 3.33kΩ 0.0685
2.6V 4.47mA
Body Bias Effect

Now to find the value of gamma practically, we will use the formula:
12
∂ ID γ
gmb = =g m
∂ V BS √ 2 ϕ+V BS
Here, ϕ=0.9
W
√
gm = 2 I D μn C ox (
L
)
Here, μn=0.035, C ox =3.8367× 10−3

gm =√ 2 I D × 0.035× 3.8367 ×10−3 ×10
Expected value of gamma asper the level 1 spice model 0.45

VBS ID gmb gm γ
-3
0 1.3637 mA 0.502 10
× 1.9138 × 10-3 0.3519
0.1 1.4139 mA
0.2 1.4650 mA 0.521× 10-3 1.9836 × 10-3 0.3714
0.3 1.5171 mA
0.4 1.5699 mA 0.539 × 10-3 2.0534 × 10-3 0.3893
0.5 1.6238 mA
Circuit and simulation output.

Channel length modulation
Circuit description :- level 1 spice model where we are calculating the current Id
across the resistor R2 of 1ohm.
We are varying the value of voltage V1 from 0 to 21 in step of 0.1
And varying V2 from 1 to 4 in step of 1.
13
In this simulation we can see that due to channel length modulation that even after
saturation the value of ID is varying
Body bias effect

Circuit description: here in this circuit to simulate the body bias effect we have
attached a voltage source between body and source of the mosfet
Here we are varying
V1 from 0 to 20 in steps of 0.1
V3 from 0 to 0.5 in steps of 0.1
V2 is kept constant at 2
14
Conclusion :- Channel length modulation and body bias effect were studied in
this experiment using LT spice.
15
EXPERIMENT NO. 3:
Objective: For a basic current mirror, verify the current mirroring action and
obtain the constraints on the drain resistor RD of the mirror device for current
mirroring action to persist. Plot the Io v/s RD characteristics to verify for the basic
current mirror as well as the cascode configuration.
Theory: Explain need for current mirroring and establish the relationship for
current mirroring principle in basic current mirror along with the cascode current
mirror.
A current mirror is a circuit designed to copy a current through one active device
by controlling the current in another active device of a circuit, keeping the output
current constant regardless of the loading. The current being copied can be , and
sometimes is, a varying signal current.
It is used whenever constant current is required regardless of source voltage.
Making a constant minimum load for power supply circuits.
16
Basic current mirror:-
Image from electrohub

Basic current mirror can be implemented by using 2 mosfets, as shown in the
figure M1 and M2 both working in active mode in this mode the output current is
equivalent to Iref. the drain current is a function of drain gate voltage and gate
source voltage.
\
Cascode current mirror :-
17
Image from electrohub

A diode connected mosfet being fed by a constant current like M1 and M3 behaves
as a constant DC potential. In analysis of Current mirrors, due to not taking the
channel length modulation in consideration, significant errors arise while current
mirroring. Hence, we used cascode current mirrors which are modified basic
current mirrors. We get.
-
W
I D2 ( ) (1+ λ V
=
L 2 DS 2)
I D1
( ) (1+ λ V
W
L 1
DS 1)
Another MOSFET M4 is added to the basic current mirror and V b is given to the
gate of M4.
Circuit Diagram:
Both the circuit the value of the Iref would be equivalent to I0
Basic current mirror
18
Cascode current mirror
Outputs:
Basic current mirror
19
Basic current mirror variable Rd
Cascode current mirror
Cascode current mirror variable Rd
Observations:
20
Basic Current Mirror

i. Basic Current Mirror with R
K Iref Io (Theoretical) Io (practical)
1 20.6594 uA 20.6594 uA 20.608 uA
ii. Basic Current Mirror with variable R

K Iref Io Io (practical) R
(Theoretical) Upper Lower Upper Lower
limit limit limit limit
1 20.6594 uA 20.6594 uA 250 kΩ 200 kΩ 19.3282 20.6594
uA uA
Cascode Current Mirror

i. Basic Current Mirror with R
K Iref Io (Theoretical) Io (practical)
1 16.4964 uA 16.4964 uA 16.489 uA
ii. Basic Current Mirror with variable R

K Iref Io Io (practical) R
(Theoretical) Upper Lower Upper Lower
limit limit limit limit
1 16.4964 uA 16.4964 uA 250 kΩ 200 kΩ 16.4356 16.4964
uA uA
Conclusion:
We studied as we increase the value of RD the current value drops as seen in
graph.
21
We calculated the values of practical and theory and compared them.
EXPERIMENT NO. 4:
22
Objective: For the voltage independent current biasing circuit configuration,

verify, in the absence of source resistor R s, the relationship Iout = Iref. For source
resistance Rs in M2, obtain and verify Iout for given value of Rs. Compare calculated
values against those observed.
Theory:
Voltage independent current biasing in absence of RS
Images from rizavi

It is important to derive and copy Iref from Iout in order to make it completely
independent of VDD. Here, we can essentially assume that the following equation if
channel length modulation is ignored.
I out =k I ref
Here, the Iout is a kth multiple of Iref as flowing shown in the figure above.
Here, as we know, each diode connected sub-circuit draws current from a current
source, which in turn means that, both Iref and Iout are independent of VDD.
Voltage independent current biasing with RS

As we know, sources of MOSFET M1 and M2 are at different voltages, this can
introduce errors in the calculations due to assumption of VTH1 = VTH2.
23
Images from rizav

This problem can be solved by placing a resistor in the source of M3 while
eliminating body effect by shorting the source and substrate of each PMOS.
The equation for this condition is given by:
2
2 1 1
I out =
W
. 2
RS (
. 1−
√K )
un C OX ( )
L N
Circuits:-
24
Outputs:
25
K=1
K=2
K=3

K=1
K=2
26
K=3
Observations:
K Iref Io (Theoretical) Io (Graphical)
1 -1.4379 mA -1.4379 mA -1.4379 mA
2 -1.4379 mA -2.8758 mA -2.8759 mA
3 -1.4379 mA -4.3137 mA -4.3139 mA

K Iref Io (Theoretical) Io (Graphical)
1 -879.730 uA -879.730 uA - 796.61 uA
2 -614.669 uA -1.2298 mA - 1.0491 mA
3 -460.594 uA -1.3817 mA - 1.1319 mA
27
Conclusion: We have implemented voltage independent current biasing circuit

with and without Rs. In this config. Without Rs the theoretical and graphical values
match closely. While in with Rs values vary by greater extent for lower values of
k.
28
Experiment 5
Objective: For the common source amplifier configuration involving load as –
1. Resistor RD
2. MOS Device in diode connected configuration
Simulate and compare the transfer characteristics, i.e., Vo v/s Vin for each
configuration
Problem Statement:
1. Record range of values of Vin and Vout over which linear amplification
characteristics are observed for RD = 10 kΩ, 5 kΩ, 2.5kΩ.
2. Record range of values of Vin and Vout over which linear amplification
characteristics are observed for diode load with W/L = 10, 100, 1000.
3. Consider W/L – 10 as for the amplifying device. Compare the two
characteristics and comment on the same. Obtain the gain from the
characteristics and compare with the theoretical value.
Theory :In this config the input is connected to the gate terminal and the output at
the drain terminal and grounding the source terminal. The only difference between
the two configurations mentioned below are the change in the type of load used.
Common Source Amplifier with RD

In this config we are using RD as the load for the common source amplifier as
shown in the figure.
the input voltage increases from 0, MOSFET M1 is turned off, so V out = VDD. As
Vin reaches VTH, M1 begins to turn on and draws current from R D and thus, Vout
29
decreases. M1 turns on even in saturation mode irrespective of the values of V DD or

RD.
1 W
V out =V DD −R D u n C OX (V ¿−V TH )2
2 L
With increase in Vin, Vout reduces more and M1 continues to operate in saturation
mode until Vin exceeds Vout by VTH.
The input-output characteristics are given by:
∂V out W
A v= =−R D un C OX ( V ¿ −V TH ) =−gm R D
∂V¿ L
Here we can see the relation for gain as we increase the value of R D the value of
the gain increases. Here gm is the transconductance.
Common Source Amplifier with Diode connected Load
Here instead of RD as load we will be using another mosfet as a diode config and
instead of RD it's value is dependent on the W/L ratio of the mosfet as load.
This diode load acts as a small signal resistor here the mosfet is always in
saturation as it's gain and drain is shorted.
1 −g 1
A v =−gm 1
( )
g m 2 + gmb 2
= m1
gm 2 1+n
W
A v=
√
− 2 un COX (
W
) I
L 1 D1 1
1+ n
√2 un COX ( ) I D 2
L 2
Where; ID1 = ID2,
30
W
A v=
√
− (
W
)
L 1 1
1+ n
√ ( )
L 2
Where, n is given by:

g mb 2 γ
n= =
gm 2 2 √2 ∅ +V BS
Observation:
Gain of CS amplifier with RD is given by.
A v =−gm RD
Where, gm (transconductance) is given by:
( WL )(V −V )
gm =un C OX GS TH
1000 u
g =(0.0350)(3.8367 ×10 ) (
100 u )
−3
m (1.25−0.7)
gm =7.3856× 10− 4
- For practical calculations, the gain can be calculated by using the formula of
straight-line slope, by taking the obtained graphical output into
consideration:
y2 − y1
A v=
x2 −x1
RD Av (Theoretical) Av (Graphical)
2.5 kΩ - 1.8464 - 1.716
5 kΩ - 3.6928 - 3.298
10 kΩ - 7.3856 - 6.026
31
CS Amplifier with diode load, the gain is given by:

W
Where, ‘n’ is given by:

A v= √ (
¿¿
)
L 1
¿
γ 0.45
n= = =0.2372
2 √ 2 ∅+V BS 2 √ 2 ( 0.9 )+ 0
Here, VBS = 0, as the substrate and source are connected in shorted.
For practical calculations, the gain can be calculated by using the formula of
straight-line slope, by taking the obtained graphical outputs into consideration:
y2 − y1
A v=
x2 −x1
W AV (Theoretical) Av (Graphical)
( )
L 2
10 -0.8083 -0.8416
100 -0.2556 -0.3531
1000 -0.0881 -0.1179
Circuit diagram:
Circuit description:- this is a common source configuration with RD as a load. Here
we are varying V2 from 0 to 5 in steps of 0.1
32
RD = 2.5k
RD = 5k
RD = 10k
33
Circuit description:- this is a common source config with diode load. Here we are
varying V2 from 0 to 5 in steps of 0.1
W/L=10
W/L=100
W/L=1000
34
Conclusion: after simulating these two configurations of Common source

amplifier involving load as resistor R D and MOS device connected in diode, we
found that
1. In load RD as we increase the value of RD the slope of the line reduces that is
increased in gain and the - sign represents the 180 phase shift. That is it goes
from -1.716 to -6.026 as we increase the Value of RD from 2.5k to 10k.
2. Similarly for in diode as load config as we increase increase the value of
W/L ratio the -0.803 to -0.0881 here we can see the gain reduce on, as we
increase W/L ratio
35
EXPERIMENT No. 6:
Objective: For CS Amplifier involving resistive load (RD) with source

degeneration (Rs), simulate the characteristic behaviour of Vout v/s Vin
Problem Statement: With RD = 10 kΩ and Rs = 0 Ω and 1 kΩ, record the range of
values of Vin over which linear amplification characteristics is observed, record
the slope(gain) as well.
Theory:
CS Amplifier with Source degeneration and resistive load
(Adapted from Razavi)

In few applications of MOSFET CS amplifiers, the nonlinear dependence of Drain
current upon the overdrive voltage might introduce non-linearity in the circuit. To
avoid this, we can construct a CS Amplifier with source degeneration where a
resistor is placed in series with the source terminal to ensure linearity in the circuit.
Here, as Vin increases, ID also increases and a voltage drop is seen across RS, which
means, a small portion of input voltage appears across RS instead of the gate-
source overdrive, which leads to smooth variation in drain current ID.
The transconductance is given by:

∂ID ∂ f ∂ V GS ∂I ∂f
Gm = =
∂ V ¿ ∂ V GS ∂ V ¿ (
= 1−RS D )
∂ V ¿ ∂V GS
gm
Gm =
1+ gm Rs
36
The small signal voltage gain is given by:

−g m R D
A v =−G m R D =
1+ g m R s
Outputs:
CS Amplifier with Source Degeneration and resistive load
RS = 0 Ω, RD = 10 kΩ
RS = 1kΩ, RD = 10 kΩ
37
Calculations:
CS Amplifier with Source Degeneration and resistive load
Gain is given by
−gm R D
A v=
1+ g m R s
Where, gm that is trans conductance is given by
( WL )(V −V )
gm =un C OX GS TH
1000 u
g =(0.0350)(3.8367 ×10 ) (
100 u )
−3
m (1.25−0.7)
gm =7.3856× 10− 4
For practical calculation we use slope of the line.

y2 − y1
A v=
x2 −x1
Observations:
A. CS Amplifier with Source Degeneration and resistive load
RD RS Av (Theoretical) Av (Graphical)
38
10 kΩ 0 kΩ - 7.3856 - 7.109
10 kΩ 1 kΩ - 4.2481 - 3.83706
Conclusion: As the value of Rs increases gain decreases. As Rs is introduced gain

decreases.
39
Experiment 7
40
41
42
43
44
Summary:
The neural chip implements a building module for a Multi Layer Perceptron
architecture which can be connected as a co-processor to a general purpose host
computer. The host computer manages the I/O operations and acts as the
supervisor during the learning phase. The chip has been fabricated using the
standard ES2 1.5|CMOS process.
Main features of analog NNs are:
1)The information is represented by the relative values of analog signals; .
2)The computation is carried out in an analog way; .
3)Elementary physical phenomena i.e. used as computational primitives.
45
The chip contains a matrix of :

1. 8 x 4 synapses,
2. 4 neurons and a vector of 4 threshold synapses,generating a bias signal in
input to each neuron.
It is organized into 4 slices: each slice contains one neuron, 8 synapses and one
threshold circuit.
During the learning phase, input signals are propagated forward, the actual outputs
are sampled, compared with the desired target outputs and the generated error is
propagated backward to the previous layer.
The neuron module is implemented through a simple amplifier with a circuit for
the calculation of the local error.
Previous attempts have been made to implement digital on-chip Back Propagation
learning, but in our case the implementation of the learning algorithm is fully
analog. The adaptativity (on-chip learning) and locality of analog computations
make feasible the implementation of analog VLSI neural networks.
46

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Name: ANUJ ENGINEER SAP ID: 60001170004 SUBJECT : A&M VLSI

NAME: ANUJ ENGINEER

1 Characteristics Behaviour of VGS in NMOS 5-3-2021 1

Second Order Effects on CS NMOS

3 Basic and Cascode Current Mirror 19-3-2021 13

4 Voltage Independent Current Biasing 9-4-2021 18

5 CS Amplifier with RD and Diode Load 9-4-2021 23

CS Amplifier with Source Degeneration and

Objective: For an NMOS device considering Level–1 SPICE simulation

Fig.3(Images from rizavi)

V(x)➡ channel potential at x

v➡ velocity of the electron.

v=μE, where μ is the mobility of charge and E is the electric field.

E(x) = -dV/dx and representing the mobility of electrons μn

Fig.4(Images from rizavi)

Fig.5(Images from rizavi)

Fig.6(Images from rizavi)

Fig.7(Images from rizavi)

1 1V 1 - 0.7 = 0.3 V 61.76 μA

2 2V 2 - 0.7 = 1.3 V 1.2848 mA

3 3V 3 - 0.7 = 2.3 V 4.377 mA

The value of ID is given by

Where the value of un = 0.035

From theoretical calculation

1 1V 1 - 0.7 = 0.3 V 60.42 μA

2 2V 2 - 0.7 = 1.3 V 1.134 mA

3 3V 3 - 0.7 = 2.3 V 3.551 mA

which can damage the said device

U0- channel mobility cm2/V/ 1. Channel mobility describes how

2. It gives the relation between drift

Simulation output and circuit diagram :-

Conclusion:-We have calculated the value of ID and the factors on which it

Theory:Every action has a consequence, and each consequence has another

Channel Length Modulation: actual length of the inverted channel gradually

In the above equation L’ is in fact a function of V DS . This effect is called channel

Here, VDS = VGS – VTH = VGS – 0.7

Hence, lambda λ is expressed as:

Expected value of lambda asper the level 1 spice model 0.1

Body Bias Effect

Here, μn=0.035, C ox =3.8367× 10−3

Expected value of gamma asper the level 1 spice model 0.45

Circuit and simulation output.

Body bias effect

Basic current mirror:-

Image from electrohub

Cascode current mirror :-

Image from electrohub

Cascode current mirror

Basic current mirror variable Rd

Cascode current mirror

Cascode current mirror variable Rd

Basic Current Mirror

ii. Basic Current Mirror with variable R

Cascode Current Mirror

ii. Basic Current Mirror with variable R

We calculated the values of practical and theory and compared them.

Objective: For the voltage independent current biasing circuit configuration,

Images from rizavi

Voltage independent current biasing with RS

Images from rizav

Voltage independent current biasing with RS

Voltage independent current biasing with RS