Problema 1

entity circ is
port (a,b,CLK,EN: in std_logic;
sel: in std_logic_vector (1 downto 0);
Q: out std_logic);
end circ;
architecture comp of circ is
begin
process (CLK,EN)
begin
if EN=’0’ then
Q<=0;
elsif rising_edge(CLK) then
if Sel=’00’ then
Q<=a or b;
elsif Sel=’01’ then
Q<=a and b;
elsif Sel=’10’ then
Q<=(not a) xor b;
elsif Sel=’11’ then
Q<=(not a) or b;
end if;
end if;
end process;
end comp;

TESTBENCH-UL
entity circuittest is
end circuittest;
architecture testbench of circuittest is
component circuit is
port (a,b,CLK,EN: in std_logic;
Sel: in std_logic_vector (1 downto 0);
Q: out std_logic);
end component;
signal CLK: std_logic;
signal a,b: std_logic;
EN: std_logic;
Q: std_logic;
Sel: std_logic_vector(1 downto 0);
begin
UUT: circ port map (CLK,a,b,EN,Q,Sel);
process
begin CLK<=’0’;
wait 5ns;
CLK<=’1’;
wait 5ns;
end process;
process
begin EN<=’0’;
wait 17ns;
EN<=’1’;
wait 17ns;
end process;
process
begin Sel<=’00’;wait 25ns;
Sel<=’01’;wait 20ns;
Sel<=’10’;wait 20ns;
Sel<=’11’;wait 20ns;
end process;
process
begin a<=’0’;wait 10ns;
a<=’1’;wait 15ns;
end process;
process
begin b<=’0’;wait 18ns;
b<=’1’;wait 15ns;
end process;
end testbench;

Problema 2

entity DFF is
port (D,CLK,R,S: in std_logic;
Q: out std_logic);
end DFF;
architecture beh of DFF is
signal u: std_logic;
begin
process (CLK,R)
begin
if R=’1’ then
u<=’0’;
elsif rising_edge (CLK) then
if S<=’1’ then
u<=’1’;
else
u<=’D’;
end if;
end if;
end process;
Q<=’u’;
end beh;
TESTBENCH
entity DFFtest is;
end DFFtest;
architecture testbench of DFFtest is
component
port (D,CLK,R,S: in std_logic;
Q: out std_logic);
end component;
signal: D,CLK,R,S,Q: std_logic;
begin
UUT: DFF port map (D,CLK,R,S,Q);
process
begin CLK<=’0’;wait for 5ns;
CLK<=’1’wait for 5ns;
end process;
process
begin S<=’0’;wait for 6ns;
S<=’1’wait for 6ns;
end process;
process
begin R<=’1’;wait for 7ns;
R<=’0’;wait ;
end process;
process
begin D<=’0’;wait for 10ns;
D<=’1’wait for 10ns;
end process;
end testbench;
 Problema 3

entity JKFF is
port (CK: in std_logic;
JK: in std_logic_vector(10);
Q: out std_logic);
end JKFF;
architecture comp of JKFF is
signal u: std_logic;
begin
process (CK)
begin
if rising_edge(CK) then
case JK is
when ‘00’ => u<=u;
when ‘01’ => u<=’0’;
when ‘10’ => u<=’1’;
when ‘11’ => u<=’not u’;
when others => u<=’-’;
end case;
end if;
end process;
Q<=u;
end comp;
TESTBENCH JK
entity JKFFtest is
end JKFFtest;
architecture testbench of JKFFtest is
component
port (CK: in std_logic;
JK: in std_logic_vector(10);
 Q: out std_logic);
end component;
signal CK,Q: std_logic;
signal JK: std_logic_vector(10);
begin
UUT: JK port map (CK,JK,Q);
process
begin
CK<=’0’;
wait for 5ns;
CK<=’1’;
wait for 5ns;
end process;
process
begin
JK<=’00’; wait for 7ns;
JK<=’01’; wait for 8ns;
JK<=’10’; wait for 6ns;
JK<=’11’; wait for 7ns;
end process;
end testbench;

entity SRFF is
port (CK: in std_logic;
SR: in std_logic_vector(10);
Q: out std_logic);
end SRFF;
architecture comp of SRFF is
signal u: std_logic;
begin
process (CK)
if rising_edge(CK) then
case SR is
when ‘00’ => u<=u;
when ‘01’ => u<=’0’;
 when ‘10’ => u<=’1’;
when others => u<=’-’;
end case;
end if;
end process;
Q<=u;
end comp;
TESTBENCH SRFF
entity SRFFtest is
end SRFFtest;
architecture testbench of SRFFtest is
component
port (CK: in std_logic;
SR: in std_logic_vector(10);
Q: out std_logic);
end component;
signal CK,Q: std_logic;
signal SR: std_logic_vector(10);
begin
UUT: SR port map (CK,SR,Q);
process
begin
CK<=’0’;
wait for 5ns;
CK<=’1’;
wait for 5ns;
end process;
process
begin
SR<=’00’; wait for 7ns;
SR<=’01’; wait for 8ns;
SR<=’10’; wait for 6ns;
SR<=’11’; wait for 7ns;
end process;
end testbench
 Problema 4
FSM
architecture=>3process
1.process (starecrt, enable)
2.process (CK, reset)
3.process (starecrt)

entity FSM is
port (Res,CK,INIT: in std_logic;
Q: out std_logic_vector(10));
end FSM;
architecture beh of FSM is
type state_type is (S0,S1,S2,S3);
signal starecrt, stareviit: state_type;
begin
process (starecrt, INIT)
begin
case starecrt is
when S0=>if INIT=’0’ then
stareviit<=’S0’;
else stareviit<=’S1’;
end if;
when S1=>if INIT=’1’ then
stareviit<=’S1’;
else stareviit<=’S2’;
end if;
when S2=>if INIT=’0’ then
stareviit<=’S2’;
else stareviit<=’S3’;
 end if;
when S3=>if INIT=’1’ then
stareviit<=’S3’;
else stareviit<=’S0’;
end if;
end case;
end process;
process (CK, Res)
begin
if Res=>’1’ then
starecrt<=S0;
elsif rising_edge (CK) then
starecrt<=stareviit;
end if;
end process;
process (starecrt)
begin
case starecrt is
when S0 => Q<=’00’;
when S1 => Q<=’01’;
when S2 => Q<=’10’;
when S3 => Q<=’11’;
end case;
end process;
end beh;
TESTBENCH
entity FSMtest is
end FSMtest;
architecture testbench of FSMtest is
component FSM is
port (Res,CK,INIT: in std_logic;
Q: out std_logic_vector(10));
end component;
signal starecrt, stareviit: state_type;
begin
UUT: FSM port map (Res,CK,INIT,Q)
process
begin
CK<=’0’; wait for 5ns;
CK<=’1’; wait for 5ns;
end process;
process
begin
Res<=’1’; wait for 12ns;
Res<=’0’; wait;
end process;
process
begin
INIT<=’0’; wait for 8ns;
INIT<=’1’; wait for 8ns;
end process;
end testbench;

Problema 5
Sincron cu CK asincron prioritar fata de ceas.

entity circuit is
generic (n: natural=4)
port (RS: in std_logic_vector (10);
CK: std_logic;
D: in std_logic_vector ((n-1)0);
Q: out std_logic_vector ((n-1)0);
end circuit;
architecture beh of circuit is
begin
process (RS,CK)
begin if RS=’00’
Q<=’0000’
elsif RS=’01’=>Q<=’1111’;
elsif rising_edge(CK) then
Q<=D;
end if;
end process;
end beh;
TESTBENCH
entity circuittest is
end circuittest;
architecture testbench of circuittest is
component circuit is
port (RS: in std_logic_vector (10);
CK: std_logic;
D: in std_logic_vector ((n-1)0);
Q: out std_logic_vector ((n-1)0));
end component;
signal CK :std_logic;
signal D, Q: in std_logic_vector ;
signal RS: in std_logic_vector ;
begin
UUT: circuit port map (CK,D,R,S,Q);
process
begin
CK<=’0’;wait for 5ns;
CK<=’1’;wait for 5ns;
process
begin
RS<=’00’; wait for 7ns;
RS<=’01’; wait for 6ns;
RS<=’11’; wait;
end process;
process
begin
D<=’1001’;
end process;
Problema 6

library IEEE;
use IEEE.std_logic_1164.all;
entity circ is
port (CLK,EN,R: in std_logic;
Q: out std_logic);
end circ;
architecture s_circ of circ is
begin
process (CLK,R)
variable D: std_logic;
variable Q1: std_logic:=’1’;
begin
D: =not(EN and Q1);
if R=’0’ then
Q1:=’0’;
elsif R=’1’ then
if CLK’event and CLK=’1’ then
Q1:=D;
else
null;
end if;
end if;
Q<=Q1;
end process;
end;
TESTBENCH
library IEEE;
use IEEE.std_logic_1164.all;
entity tc is
end;
architecture test of tc is
component circ is
port(CLK,EN,R: in std_logic;
Q: out std_logic);
end component;
signal CLK: std_logic:=’0’;
signal EN: std_logic:=’0’;
signal R: std_logic;
signal Q: std_logic;
begin
UUT: circ port map (CLK,EN,R,Q);
CLK<=not CLK after 10ns;
EN<=not EN after 15ns;
R<=’1’;
end test;
Problema 7

library IEEE;
use IEEE.std_logic_1164.all;
entity circuit is
port (CLK,EN1,EN2,R: in std_logic;
Q: out std_logic);
end circuit;
architecture fcircuit of circuit is
begin
process (R,CLK)
variable temp1,temp2: std_logic;
begin
if R=’0’ then
Q<=’1’;
elsif R=’1’ then
if CLK’event and CLK=’1’
then
temp1:=EN1 nand temp2;
temp2:=temp1;
Q<=EN2 nand temp2;
else
null;
end if;
end if;
end process;
end;
TESTBENCH
library IEEE;
use IEEE,std_logic_1164.all;
entity tc is
end;
architecture driver of tc is
component circuit
port (CLK,EN1,EN2,R: in std_logic;
Q: out std_logic);
end component;
signal CLK: std_logic:=’0’;
signal EN1,EN2,R: std_logic:=’0’;
signal Q: std_logic;
begin
UUT: circuit port map (CLK,EN1,EN2,Q,R);
CLK<=not CLK after 5ns;
 EN1<=not EN1after 7ns;
EN2<=not EN2 after 12ns;
R<=’1’ after 8ns;
End

Problema 8

entity circuit is
port (Di,CK,SHIFT: in std_logic;
Q: out std_logic_vector (70));
end circuit;
architecture comp of circuit is
begin
process (CK)
begin
if rising_edge (CK) then
if SHIFT=’0’ then
Q<= Di&(7 downto 1);
else
Q<=(6 downto 0)&Di;
end if;
end if;
end process;
end comp;
TESTBENCH
entity circuittest is
end circuittest;
architecture testbench of circuittest is
component circuit is
port (Di,CK,SHIFT: in std_logic;
Q: out std_logic_vector (70));
 end component;
signal Di,CK,SHIFT: std_logic;
signal Q: std_logic_vector (70);
begin
UUT: circuit port map (Di,CK,SHIFT,Q);
process
begin
CK<=’0’; wait for 3ns;
CK<=’1’; wait for 3ns;
end process;
process
begin
Di<=’0’; wait for 5ns;
Di<=’1’; wait for 5ns;
end process;
process
begin
SHIFT<=’0’; wait for 20ns;
SHIFT<=’1’; wait for 20 ns;
end process;
end testbench;