3.

2 CMOS Technologies 109

Polysilicon

Gate Oxide

p-well p-well

Substrate

(a) (b)

Implantation

p-well p-well

(c) (d)

Poly Gate

Shallow n-Source/Drain Shallow n-Source/Drain

p-well

(e)

FIGURE 3.9 Gate and shallow source/drain definition

capacitance but high resistance. This reduces device performance somewhat because of the
resistance in series with the transistor. Consequently, deeper, more heavily doped source/
drain implants are needed in conjunction with the LDD implants to provide devices that
combine hot electron suppression with low source/drain resistance. A silicon nitride
(Si3N4) spacer along the edge of the gate serves as a mask to define the deeper diffusion
regions, as shown in Figure 3.10(a). For in-depth coverage of various LDD structures, see
[Ziegler02].
As mentioned, the polysilicon gate and source/drain diffusion have high resistance
due to the resistivity of silicon and their extremely small dimensions. Modern processes
form a surface layer of a refractory metal on the silicon to reduce the resistance. A refrac-
tory metal is one with a high melting point that will not be damaged during subsequent
processing. Tantalum, nickel, molybdenum, titanium, or cobalt are commonly used. The
metal is deposited on the silicon (specifically on the gate polysilicon and/or source/drain
regions). A layer of silicide is formed when the two substances react at elevated tempera-
tures. In a polycide process, only the gate polysilicon is silicided. In a silicide process (usu-
ally implemented as a self-aligned silicidization––from whence comes the synonymous