PC-EE-504-Module 5

Power Electronics

Inverters

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 Inverters-Basic Concepts
• Inverters are DC to AC converters, where the input voltage is dc and the output
is an alternating voltage with no average value. The output maybe a sinusoidal
voltage (single spectral frequency or fundamental only) or any alternating
voltage waveform (square wave etc.) which may have multiple spectral
frequencies (harmonics).
• Inverters are classified by the number of output phases; single phase or three
phases. Single phase inverters are again classified as Half-bridge and Full-
bridge inverters.
• Inverters are classified by the source; voltage source inverter (VSI) or current
source inverter (CSI). The VSI has low source impedance (Capacitor in parallel)
and the CSI has high source impedance (Inductor in series).
• Inverters are also classified by the method of control. Inverters may be
uncontrolled, maybe Single Pulse Width Modulation (PWM) controlled or maybe
Multiple Pulse Width Modulation Control. Among Multiple PWM control, the
most preferred is the Sinusoidal Pulse Width Modulation (SPWM) control which
is widely used for industrial applications as in Un-interrupted Power Supply
(UPS) systems. Such Inverters have harmonics greatly reduced in output.
• Finally, inverters may have a variable frequency output. Usually, these inverters
have variable frequency and variable voltage output together maintaining V/f
constant for constant torque output to three phase squirrel cage induction
motors. Such inverters find wide application in drives for transportation as
electric cars and locomotives.
• The domestic inverters frequently used in our homes are Single Phase full-
bridge, constant frequency VSI with Single PWM to regulate the output voltage
with changes in the dc battery voltage and output load. These inverters have 2
considerable harmonics in the output.
 Single Phase Half-Bridge Inverter-I

The schematic circuit, the waveforms and the switching sequence of a Single
Phase half-Bridge Inverter are shown in Figs. 1 and 2. S1 and S2 are two level
controlled semiconductor switches (BJT/MOSFET/IGBT) with anti-parallel
diodes to conduct current for inductive load. The inverter has square wave
voltage output as shown in Fig. 2 with frequency f. For the inverter to function
as shown, the Capacitor value C must be large enough to maintain half the dc
supply voltage at the junction point as shown in Fig. 1. For an average load
current Io during a half-cycle, the change in Capacitor charge is given by:
DQC=Io*(1/2*f) ---(1)
The steady charge in the Capacitor is given as: QS=C*VS/2 ----(2)
For steady operation, QS>>DQC and hence from (1) and (2) : C>>Io/(f*VS) ----(3)
The value of Capacitor must be chosen keeping condition (3) in consideration.
 Single Phase Half-Bridge Inverter-II
The waveforms in Fig. 2 are quite self-explanatory. The switches S1 and S2 are
on for half the total time period (1/2f) complimentarily; that is when S1 is ON
then S2 remains OFF and vice-versa. As a result an alternating square wave
voltage VS/2 appears across the load. For a pure resistive load, the current
waveform shall be a scalar multiple of the voltage and the diodes are not active.
As the load becomes inductive, the current waveform becomes exponential and
for highly inductive load (f*L>>R) the current becomes triangular with the
diodes conducting as shown in Fig. 2. (Note that these are all steady state
waveforms). The peak inductive current Ipk is given from:
L*DI/Dt=L*(2*Ipk)/(1/2*f)=VS/2 ----(4) and from (4) Ipk=VS/(8*f*L) -----(5)
The RMS output voltage is given as VRMS= VS/2 -----(6)
The Fourier series of the output voltage:
vo(t)=(2*VS/p)*Sn=1,3,5.. sin(n*w*t)/n----(7) w=2*p*f
From (7), the RMS of the fundamental (n=1) is given by:
V1RMS=21/2*VS/p=0.45*VS ---(8)
The general Fourier series of the current for a R-L load is given as:
io(t)= (2*VS/p)*Sn=1,3,5…sin(n*w*t-qn)/[n*(R2+(n*w*L)2)1/2] ----(9) qn=tan-1(n*w*L/R)
The fundamental power is given by:
V1RMS*I1RMS*cos(q1)=2*VS2*R/[p2*(R2+(w*L)2] ---(10)
For a pure resistive load the fundamental power becomes: 2*VS2/(p2*R) ---(11)
 Single Phase Full-Bridge Inverter-I

From expression (3) for the half-bridge inverter, the value of Capacitor needed
becomes enormously large for high current and low frequency and low dc
supply. Hence the half-bridge is not suitable for heavy loads (generally above 2
kW) and also not at very low frequency and dc supply. One example is the
domestic inverter which operates at 50 Hz and from battery source of 12 or 24 V.
The schematic circuit, the waveforms and the switching sequence of a Single
Phase half-Bridge Inverter are shown in Figs. 3 and 4. The two capacitors in the
half-bridge circuit have been replaced by two switch-diode combinations. The
switches S1, S2 are ON together in one half-cycle and the switches S3, S4 are
on together in the other half-cycle. The resulting load voltage waveform is an
alternating square wave with amplitude VS as shown. The nature of load current
remains same as for the half-bridge depending on the nature of the load being
pure resistive or mildly inductive (current curve is exponential) or highly
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inductive as defined when the current becomes triangular.
 Single Phase Full-Bridge Inverter-II
The peak inductive current Ipk is given in this case as
L*DI/Dt=L*(2*Ipk)/(1/2*f)=VS ----(12)
From (12) Ipk=VS/(4*f*L) -----(13)
The RMS output voltage is given as VRMS= VS -----(14)
The Fourier series of the load voltage:
vo(t)=(4*VS/p)*Sn=1,3,5.. sin(n*w*t)/n----(15) w=2*p*f
From (15), the RMS of the fundamental (n=1) is given by:
V1RMS=81/2*VS/p=0.90*VS ---(16)
The general Fourier series of the current for a R-L load is:
io(t)= (4*VS/p)*Sn=1,3,5…sin(n*w*t-qn)/[n*(R2+(n*w*L)2)1/2] ----(17)
where qn=tan-1(n*w*L/R)
The fundamental power is given by:
V1RMS*I1RMS*cos(q1)=8*VS2*R/[p2*(R2+(w*L)2] ---(18)
For a pure resistive load the fundamental power becomes:
8*VS2/(p2*R) ---(19)
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 Performance Parameters for Inverters
Alike Rectifiers, Inverters too have performance parameters to qualify them.
Obviously, an ideal inverter would have only the desired fundamental
sinusoid as output without any harmonics. Following factors are defined to
assess the performance of an inverter.

• Harmonic Factor HFn=VnRMS/V1RMS ---- (20)

where V1RMS=RMS value of the fundamental voltage
VnRMS=RMS value of the nth harmonic voltage

• The Total Harmonic Distortion (THD) is defined as:

THD=[Sn=2,3,…VnRMS2]1/2/V1RMS=[VRMS2-V1RMS2]1/2/V1RMS=[(VRMS/V1RMS)2-1]1/2 ----(21)
• The THD is the most commonly used performance parameter for
inverters. Generally, an inverter with THD<5% is accepted as standard.
• The THD for the single phase full-bridge inverter:
THD=[{VS/(0.90*VS)}-1]1/2=48.4% --(22)

As there is generally a (1/n) term in the Fourier series for each harmonic
voltage, the power decreases as (1/n2) with increasing harmonic.
The Distortion Factor DF takes this into account. DFn=VnRMS/(n2*V1RMS) ---(23)
DF=[Sn=2,3…(VnRMS/n2)2]1/2/V1RMS ----(24)
• For the single phase full-bridge using (15) and (24):
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DF=[Sn=3,5…(1/n6)]1/2 --- (25)
 Forced Commuted Inverter
L1=L2=L3=L4=L C1=C2=C3=C4=C
w2=1/(L*C) Commutation time tC<p/(2*w)
When T1 is turned off a resonant
voltage appears across diode D1 for
p/(2*w). and D1 conducts.
Hence for an inverter frequency f, the
half time period is (1/2*f) and it is very
important that (1/2*f) > > (p/w)
The commutation is complimentary.
In the previous examples the switches in the inverter were level controlled,
(BJT/MOSFET/IGBT) or GTO which could be commuted (turned OFF) by control
signals. For certain applications at very high voltages SCRS are used as
switches in inverters and they need extra circuits for commutation.
The most preferred type is the McMurray-Bedford inverter shown in Fig. 5.
L1-L4 and L2-L3 are actually center-tapped inductors with sufficient air-gaps to
carry large current without magnetic saturation. When SCRs T1 and T2 are
conducting, T3 and T4 are OFF the current path is VS-T1-L1-Load-L2-T2. Hence no
voltage appears across capacitors C1, C2 but C3 and C4 are charged to VS in the
polarities shown. The instant T3 and T4 are fired, the voltage across C4 appears
in the resonant loop C4-L4-T4 with the inductor L1-L4 reverse biases T1 by +VS on
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cathode; C3-T3-L3 loop with the inductor L2-L3 reverse biases T2 by -VS on anode.
 Three Phase Inverters

The basic schematic circuit of a three phase Inverter is shown in Fig. 6. For
understanding of the operation, a star connected pure resistive load is considered.
As you know, a delta connected load maybe transformed to star and all the
semiconductor switches are provided with anti-parallel diodes to provide current
path for inductive loads as for single phase inverters. The output voltage waveforms
remain unchanged with inductive load but the current becomes generally
exponential and tends to become triangular with increasing inductance as for single
phase inverters.
The schematic circuit has six semiconductor switches (BJT/GTO/MOSFET/IGBT)
with anti-parallel diodes in 1-3-5 (positive bus) and 4-6-2 (negative bus) sequence
which you are familiar from three phase converters. The sequence remains same as
the phase relation between the switches are similar. The Capacitor is called ‘DC Link
Capacitor’ in a Voltage Source Inverter and keeps the dc supply voltage unchanged
over one full output cycle. The McMurray-Bedford inverter using forced commuted
thyristors as the switches is also used for very high voltage applications.
 180o and 120o Conduction of 3 Phase Inverters
There are two types of operation of a three phase inverter: 120o conduction
and 180o conduction. The concepts of gating sequence, mode equivalent
circuits and associated voltage waveforms are very important to
understand the operation of 3 Phase Inverters. These are studied for
balanced star connected resistive load as shown in Fig. 6.
Gating sequence: This is the sequence of application of control pulses to
the control terminals (usually Gate terminal) of the six switches. When the
gate pulse is applied, the switch is ON and remains OFF otherwise without
the application of gate pulse. For 120o conduction, the gate pulse is applied
for 120o angle in each cycle (that is a pulse width of 1/3f); for 180o
conduction the pulse is for and angle of 180o (a pulse width of 1/2f). Gate
pulses are applied 60o after one another; that is if the gate pulse of S1 starts
at 0o, the gate pulse of S2 shall start at 60o and so on. In this sequence the
gate pulse of S6 shall start at 300o and for a conduction period 120o, the
pulse will end at 300o+120o=420o which becomes 420o-360o=60o in one
cycle. Hence the gate pulse for S6 is shown in two parts in Fig. 9. The same
logic applies for 180o conduction also for the gate pulse of S5. The gate
pulse for S6 in this starts at 300o and ends at 480o which is equivalent to
120o. The Gating sequence for 120o conduction is shown at the top in Fig. 9,
for 180o conduction at the top in Fig. 10. For both types of conduction, the
mode equivalent circuits are determined by the respective gating sequences.
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 Mode Equivalent Circuits for 3 Phase Inverters

Mode equivalent circuit: Since six pulses are applied in each cycle, there are six
mode equivalent circuits for both modes of conduction. Each mode equivalent
circuit shall apply for an angle of 60o and the range of each mode is shown above
its equivalent circuit. The mode equivalent circuits are derived by simply replacing
a switch that is ON by a short circuit and a switch that is OFF by an open circuit
(ideal switch). Also the three load terminals A, B, C always remain connected to the
star connected balanced resistive load with its neutral point n as shown in Fig. 6.
Then the phase to neutral voltages Van, Vbn, Vcn are computed from the mode
equivalent circuits by Kirchoff’s laws. The mode equivalent circuits for 120o
conduction are shown in Fig. 7 and for 180o conduction in Fig. 8.
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Gating Sequence & Voltages for 120o Conduction

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Gating Sequence & Voltages for 180o Conduction

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 General Notes on 3 Phase Inverters
• Output Voltage waveforms: Each voltage waveform shall have six steps from
the six mode equivalent circuits. These are plotted and the line voltages are
derived from the phase voltages: Vab=Van-Vbn and so on. (For the 180o
conduction mode, the phase voltages are plotted below the line voltages but the
method remains the same). The phase and line voltages for 120o conduction are
shown in Fig. 3 and for 180o conduction in Fig. 5.
• Output current and unbalanced loads: For pure resistive load, the output
current waveforms are identical to the voltage waveforms. The effect of
inductive load has been discussed. Generally, three phase inverters are
operated on balanced loads. In cases of severely unbalanced loads (as in UPS
systems for distribution to single phase loads along with three phase loads),
three single phase inverters with proper gate firing sequence to obtain three
phase supply is also done.
• Voltage and frequency control of three phase inverters: Such inverters are used
for speed-torque control of three phase squirrel cage induction motor drives
which have largely replaced dc motor drives with their associated maintenance
hazards.
• IGBT packs for inverters: As two switches are always used in series between
the positive and negative buses of the dc supply in inverters (both single and
three phase), two IGBTs with anti-parallel diodes are made in a common
package with one Collector terminal for positive, one Emitter terminal for
negative and one common Collector-Emitter terminal for load point with signal
terminals for the two gates and emitters. Composite Integrated Circuit drivers
are also available for gating two such IGBTs. 14
 3 Phase Inverter Equations
Equations for 3 Phase Inverter with 120oC Conduction:
VphaseRMS=VS/61/2=0.4082VS - - - (26) VlineRMS=VS/21/2=0.7071VS - - - (27)
Van=(2VS/p)Sn=1,3,5..cos(np/6)sin{n(wt+p/6)}/n - - -(28a)
Vbn=(2VS/p)Sn=1,3,5..cos(np/6)sin{n(wt-p/2)}/n - - - (28b)
Vcn=(2VS/p)Sn=1,3,5..cos(np/6)sin{n(wt-7p/6)}/n - - -(28c)
The line voltages are given as:
Vab=Van-Vbn - - -(29a) Vbc=Vbn-Vcn - - -(29b) Vca=Vcn-Van - - -(29c)
The fundamental magnitudes (n=1) are given as:
Vphase1RMS=(3/2)1/2VS/p=0.3898VS - - - (30)
Vline1RMS=(3/p)Vs/21/2=0.6752VS - - - (31)
Equations for 3 Phase Inverter with 180oC Conduction:
VphaseRMS=21/2VS/3=0.4714VS - - (32) VlineRMS=(2/3)1/2VS=0.8165VS - - -(33)
Vab=(4VS/p)Sn=1,3,5..cos(np/6)sin{n(wt+p/6)}/n - - -(34a)
Vbc=(4VS/p)Sn=1,3,5..cos(np/6)sin{n(wt-p/2)}/n - - - (34b)
Vca=(4VS/p)Sn=1,3,5..cos(np/6)sin{n(wt-7p/6)/}/n - - -(34c)
The fundamental magnitudes (n=1) are given as:
Vphase1RMS=21/2VS/p=0.4502VS - - -(35)
Vline1RMS=61/2VS/p=0.7797VS - - -(36)
The (THD) in both the modes: THD=[(p/3)2-1]1/2=31% - - - (37)
The important point to note is that there are no even harmonics and in all
cases the third harmonic vanishes as cos(3*p/6)=0. 15
 Comparison between 120o and 180o Conduction-I
A comparison between the two modes of conduction is made. For 120o conduction
only one switch on the positive (S1/S3/S5) and one switch on the negative bus
(S4/S6/S2) are on at a time but for 180o conduction we find switches S1 and S5 on
together during 0<wt<p/3 on the positive bus and switches S2 and S6 on together
during p/3<wt<2p/3 on the negative bus and this happens for every mode
equivalent circuit. That means switches come in parallel. One must remember the
switches are not ideal and paralleling may lead to unequal sharing of current
causing unbalance in the system. This problem is totally avoided for 120o
conduction. At the instant wt=p, we find both the switches S1 and S4 become on for
180o conduction. This happens for the other pairs S3-S6 and S5-S2 also at other
instances. This causes an instantaneous short circuit on the dc supply and the
current is limited by the source Impedance which is very low for a voltage source.
For 120o conduction there is a clear gap of wt=p/3 between the switches on the
positive and negative on the same arm bus being turned on (between S1-S4, S3-S6
and S5-S2). Hence there is no possibility of a short circuit of the dc supply. From the
mode equivalent circuits, the neutral point remains at VS/2 all along for 120o
conduction. For 180o conduction the neutral point shifts between VS/3 and
2VS/3 (VS/2+/-VS/6) and such a system is prone to unbalance. The only demerit of
120o conduction is that for every mode equivalent circuit, one load point remains
open; as load point C remains open during 0<wt<p/3. In some cases this could lead
to static charge accumulation. This can be avoided by connecting suitable
equal high ohmic value resistors (to reduce loss) across each switch. In that case
the voltage at the open load point remains at VS/2 which is the neutral voltage.
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 Comparison between 120o and 180o Conduction-II
Cause 120o 180o Effect
Conduction Conduction
Switches on in Not possible Possible Unequal current sharing,
Parallel causes unbalance
Switches on Not possible Possible Instantaneous short
positive and circuit of dc supply
negative bus on
together
Neutral point Possible Not possible Causes system unbalance
voltage steady
with respect to dc
supply
Open load point Possible, can Not possible Static charge may
be avoided by develop and damage
equal shunt switches; shunt resistors
resistors add to losses
Period of Less More RMS voltages more for
Conduction 180o than 120o conduction
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 3 Phase Inverter on Inductive Load
Note that switches S1 and S4 are turned
ON when they are not carrying any
current. Hence simultaneous switching
of switches on positive and negative
buses is no problem for inductive load
for 180o Conduction.
The effect of inductance does not allow
sudden rise in current part of which is
conducted by diodes. Hence parallel
ON of switches is also no problem.
The load current waveform Ia of one phase for an inductive load of a 3 Phase
180o conduction Inverter is shown in Fig. 11. When switch S1 turns on at wt=0
as in Fig. 10, the inductive load forces a negative current through anti-parallel
diode D1 as shown in Fig. 11. With the zero crossing of current, conduction is
taken up by S1. At wt=p the switch S1 is turned OFF and S4 turned ON and the
current in positive direction continues through diode D4. Once the current
crosses zero, switch S4 conducts the current till wt=p after which D1 conducts.
For the nth harmonic impedance Zn=R+j*n*w*L and qn=tan-1(n*w*L/R):
Ia(t)=Sn=1,3,5[(4*VS/31/2)*sin(n*p/3)/{n*p*(R2+n2*w2*L2)1/2}]*sin(n*w*t-qn) - - -(38)
The third harmonic vanishes in (38). As in 120o conduction there is a gap in the
turn-on of the switches S1 and S4, the current tends to become discontinuous
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and the 180o conduction is preferred for inductive loads.
 Single Phase Current Source Inverters

So far we have studied Voltage Source Inverters (VSI) which have a dc

voltage source with a capacitor in parallel that maintains the dc supply
unchanged over a total time period. A Current Source Inverter (CSI), as the
name suggests, use a dc current source. As you know from Circuit Theory,
there can be no practical current source and that is a circuit equivalent of a
voltage source with high source impedance to maintain a constant current
output to the load of significantly less impedance. In CSI the high source
impedance is inductive which keeps the current invariant. The Schematic
circuit, Gating sequence and load current waveforms of a single phase CSI
are shown in Fig. 12 and for a 3 phase CSI on star connected load in Fig. 13.
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Three Phase Current Source Inverters
The basic difference of CSI from a VSI
in topology is that the diodes are not
connected in anti-parallel but in series
with the semiconductor switches. That
is because the high source inductive
impedance will not permit reversal of
current but a substantially large emf
will appear across the switches when
they go OFF from ON (Ldi/dt) owing to
the source inductance. The diodes are
chosen to have sufficiently high PIV to
withstand the back emf and protect the
switches from breakdown. The gating
sequence and conduction logic of the
switches are same as for VSI with the
difference that both the positive bus
and negative bus switches (S1 & S4 in
Figs. 12 &13) can be ON together
without any chance of a short circuit as
the current is limited by the source
impedance. CSI are generally used for
low power precision load applications.
A comparison table between VSI and
CSI is given next.

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 Comparative Table for VSI and CSI
Parameter VSI CSI
Output short circuit NO YES, current limited by high
proof source impedance
Simultaneous switching Causes momentary Causes no short circuit
ON of switches on the short circuit
same arm
Peak current Not limited naturally Limited by source
impedance
DC Source component Capacitor in parallel Inductor in series
Diode connection Anti-parallel to In series with switches to
switches for free- check back emf for
wheel current transition ON to OFF
For semiconductor Extra inductors Source inductor provides
switches being needed for needed inductance for
thyristors with forced commutation commutation
commutation
Cost Less for the same Large inductor increases
power rating cost
Response time Fast Slow owing to large
inductance
Application General power, Low power, precision load
medium and high

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 Fourier Series, Harmonic Elimination
The Fourier series expansions for single and 3 phase CSI are given below:
For single phase: io(t)=(4IS/p)Sn=1,3,5….sin(np/4)sin{n(wt-p/4)}/n - - -(39)
For three phase: IA(t) =(4IS/p)Sn=1,3,5….cos(np/6)sin{n(wt+p/6)}/n - - -(40)
IB(t) =(4IS/p)Sn=1,3,5….cos(np/6)sin{n(wt-p/2)}/n - - -(41)
IC(t) =(4IS/p)Sn=1,3,5….cos(np/6)sin{n(wt-7p/6)}/n - - -(42)
The third harmonics are eliminated for 3 phase again.
The aim of an ideal inverter is to produce a sinusoidal (only fundamental
term in Fourier series) voltage output. As we have seen in practical
inverters this is not possible and the Total Harmonic Distortion is 48% for
single phase and 31% for three phase inverters normally. Harmonics can be
eliminated by phasor summation of multiple inverters.
One example is shown in Fig. 14. Transformers T1 and T2 are similar and
are connected in the polarity shown. The output of inverter A is connected
to the primary of T1 and the output of inverter B is connected to the primary
of T2. Both A and B are similar single phase inverters producing square
wave outputs as shown. But the inverter B is phase shifted by p/3 from
inverter A as shown in Fig. 14. The resulting summation waveform is also
shown. The advantage of this waveform is that the third harmonic is
eliminated and the THD in the output is reduced to 31% from 48% for single
phase output by summing inverters A and B.
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Harmonic Reduction by Summation of Inverters-I

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 Harmonic Reduction by Summation of Inverters-II

Harmonics can be greatly eliminated by obtaining a summation in the shape of

a stepped square wave (VA+VB) as shown in Fig. 15. The stepped square wave is
a close approximation of the sine and has THD below 5%. Once again the
summing will need two transformers but in this case they will not be identical
as evident from the amplitudes of the inverter waveforms VA and VB which are
the primary voltages of the transformers. Also, both the inverters need controlled
gating to achieve the desired output voltage as shown. Each gating sub-cycle is
p/8 (22.5o) in the wt scale in Fig. 15. Note that both VA and VB are pure alternating
waveforms with net zero average value for the full cycle, 0<wt<2p. Hence the
summation output VA+VB is also purely alternating. 24
Pulse Width Modulated (PWM) Inverters-I
The use of PWM in inverters serves two purposes:
1) As the magnitude of output voltage (both rms and fundamental) varies
with the input dc voltage for all cases, the use of PWM with feedback
stabilizes the output voltage magnitude for variation in input dc voltage
and output load.
2) The use of PWM reduces the harmonic content in the output and
thereby reduces the size of the filter needed to obtain the fundamental
voltage.
There are various techniques of PWM and newer techniques are still being
researched to effectively reduce harmonics and provide output control at
reduced costs and bulk.
Three types of PWM are discussed to broadly cover the subject. The
single phase versions are studied but the three phase versions use the
same principles of PWM. The schematic circuit of the single phase full
bridge inverter (already discussed) is shown in Fig. 16.
All PWM make use of a Carrier Signal which is generally a triangular
voltage waveform generated in the control circuit for gate firing. The
carrier signal has p pulses in each half-cycle of the inverter output. That
is, if the inverter output frequency is fo Hz, the carrier frequency fc is given
as: fc=2*p*fo ----(43) w=2*p*fo ----(44)
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 Pulse Width Modulated (PWM) Inverters-II

Together with that there is a Modulating (Controlling) signal. This maybe a

pedestal voltage or a sinusoid or special functions as in sophisticated PWM
techniques. The peak amplitude of the carrier signal is denoted by AC and that
of the modulating signal by AM volts. Gate pulses are generated when the
modulating signal crosses the carrier signal. The Modulation Index M is
defined as: M=AM/AC<1 ----(45)
All PWM performances are determined by the choice of the two parameters p
and M.
In the following text, VS is the dc supply voltage, V1 is the rms of the
fundamental output, Vn the rms of the nth output harmonic and DF% is the
Distortion Factor (already discussed).

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 Single Pulse Width Modulated Inverter

The waveforms are shown in Fig. 17 and the Harmonic profile of the Single
PWM Inverter is shown in Fig. 18. (Note p=1 in this case).
The output (load) rms voltage: Vrms=VS*M1/2 -----(46)
The fundamental rms voltage: V1=2*21/2*VS*sin(M*p/2)/p=0.90*VS*sin(M*p/2) (47)
The Fourier series expansion for output voltage:
VLOAD(t)=(4*VS/p)*Sn=1,3,5…sin(n*M*p/2)sin(n*w*t)/n -----(48)
From (48) the rms value of nth harmonic: Vn= 0.90*VS*sin(n*M*p/2)/n ----(49)
Note that the third harmonic (n=3) in (49) vanishes for M=2/3. This is used in
single PWM inverters for domestic use and the transformer ratio is adjusted to
have the output rms equal to the nominal ac supply (240 V, 50 Hz) for the rated
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battery voltage at M=2/3.
Multiple Pulse Width Modulated Inverter-I

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 Multiple Pulse Width Modulated Inverter-II

The schematic circuit is the same as in Fig. 16. The waveforms and the
harmonic profiles are shown in Fig. 19 and Fig. 20 for p=5. Note the reduction in
DF% in Fig. 20 compared to Fig. 18. The DF% reduces further with increasing p.
The output (load) rms voltage: Vrms=VS*M1/2 -----(50)
The fundamental rms voltage:) V1=2*21/2*VS*sin(M*p/2)/p=0.90*VS*sin(M*p/2) (51)
Note that the rms and fundamental rms voltages remain same as for the single
PWM case but as noted above, the harmonic content keeps on reducing with
increasing value of p. The switching frequency of the semiconductor switches
is given by p*fo (each switch turns ON and OFF p times in each output cycle)
and hence there is increasing switching loss with increasing value of p and the
switching devices shall have to be chosen accordingly.
29
The Fourier expansion of the load voltage in Fig. 19 has odd sine terms only.
Sinusoidal Pulse Width Modulated Inverter (SPWM)-I

30
 Sinusoidal Pulse Width Modulated Inverter-II
The schematic circuit is the same as in Fig. 16. The waveforms and
harmonic profiles are shown in Fig. 21 and Fig.22 for p=5. The
modulating signal is a sinusoid as shown in Fig. 21 and hence the
name. The major advantage is that the lowest order harmonic in the
output is of the order 2*p-1 (in this case it is the ninth harmonic as
shown in Fig. 22). That means, the filter circuit should be designed for a
cutoff at nine times the output frequency and as the product of filter LC
is proportional to 1/fcutoff2, the bulk of the filter reduces with p. In
practical UPS the typical carrier frequency is 16 kHz for the output
frequency 50 Hz. That gives p=160 and the lowest order harmonic is 319
which drastically reduces the size of the filter.
The mathematical derivations for the SPWM are quite complicated.
From Fig. 20 and Fig. 22 it is noticed that the fundamental output
voltage varies quite similar to the Multiple PWM inverter. The harmonic
reduction has been discussed and is evident from comparing DF% in
Fig.22 to Fig.20. The increase in switching frequency and hence losses
in semiconductors is common to that of Multiple PWM. MOSFETS and
IGBTS which could function with high efficiencies at frequencies at kHz
level are easily available. 31
 Sinusoidal Pulse Width Modulated Inverter-III

In equation (45) it has been mentioned that the amplitude of the modulating
signal must be less than that of the carrier signal. It is clear from the waveforms
in Fig. 17 and Fig. 19 that if AM>AC, the gate pulse width will be constant at p
(M=1) and there can be no pulse width control and hence this will lead to an
uncontrolled inverter. For SPWM, there can still be some control of gate pulses
and the plot of peak fundamental voltage (not rms value) V1pk/VS as ratio of dc
supply voltage versus modulation index M is shown in Fig. 23. Till M=1, the
relation is linear but after that the curve becomes non-linear saturating at a
value 4/p. Hence for a linear control, the modulation index is kept within unity.
32
 Three Phase SPWM Inverter

For the 3 Phase VSI shown in Fig. 6, the basic scheme for Sinusoidal PWM is
shown in Fig. 24 for p=6 and 120o conduction. The Gating Signals are denoted
as g1 to g6; the carrier signals are denoted in black and remain unaltered for
all the phases. The modulating signals and gating signals shown in different
colors (R, Y, B) are shifted in phase by 2p/3 as shown. For 120o conduction,
the span of the gate pulses are for 120o and for 180o conduction that will
extend to 180o. As discussed earlier, typical carrier frequency is 16 kHz with
p=160 and processors are used for gate pulse generation with modulation
amplitude control (AM/AC) in feedback loop.
33
 Numerical Problems-I
A single phase half-bridge inverter has dc supply voltage 400 V,
frequency 50 Hz, and average load current 5 A. Considering a safety
factor of 10, find the value of capacitor needed.
Using the safety factor in equation (3):
C=10*Io/(f*VS)=10*5*106/(50*400)=2500 mF

A single phase full bridge inverter has dc supply 220 V. Find the
fundamental rms voltage of the output considering a lossless case.
What should be the dc supply voltage if the output fundamental rms
voltage is to be 220 V?
From equation (16): V1rms=0.90*VS=0.90*220=198 V
For V1rms=220 V, from equation (16): VS=220/0.90=244.44 V

What shall be the rms voltage of the third harmonic for the single phase
full bridge inverter with dc supply 220 V?
From equation (15): V3rms=0.90*VS/3=0.90*220/3=66 V

34
 Numerical Problems-II
The load on a 120o conduction three phase inverter is pure resistive and
rated 15 kW at rms line voltage 200 V 60 Hz. What should be the dc supply
for a lossless condition? What shall be the peak and rms current of each
switch in that condition?
From equation (30): Vlinerms=0.7071*VS hence VS=200/0.7071=282.84 V
The dc supply current IS=15*103/282.84=53 A
The peak current on resistive load shall be 53 A.
Since each switch conducts 2p/3 in 2p cycle the rms current=53/31/2=30.6 A

What would be the dc supply voltage if the drop across each switch is 1 V?
What would be the rms current of each switch for overall efficiency 90%?
As two switches must conduct at a time, the dc supply VS=282.8+2=284.8 V
The dc supply current IS=15*103/(284.8*0.9)=58.5 A
The rms current of switch 58.5/31/2=33.8 A

35
 Numerical Problems-III
The load on a 180o conduction three phase inverter is pure resistive and
rated 15 kW at rms line voltage 200 V 60 Hz. What should be the dc supply
for a lossless condition? What shall be the peak and rms current of each
switch in that condition?
From equation (33): Vlinerms=0.8165*VS hence VS=200/0.8165=245 V
The dc supply current IS=15*103/245=61.2 A
The peak current on resistive load shall be 61.2 A.
Since each switch conducts p in 2p cycle the rms current=61.2/21/2=43.3 A

What would be the dc supply voltage if the drop across each switch is 1 V?
What would be the rms current of each switch for overall efficiency 90%?
As two switches must conduct at a time, the dc supply VS=245+2=247 V
The dc supply current IS=15*103/(247*0.9)=67.5 A
The rms current of switch 67.5/21/2=47.7 A

36
 Numerical Problems-IV
Find the ratio of the rms value of the lowest order harmonic to the
fundamental rms in line voltage for a 120o conduction three phase inverter.

From equation 28, the third harmonic vanishes. Hence the lowest order
harmonic is the fifth (n=5).
From 28(a), 28(b) and 29(a):
Vab=(2VS/5p)*cos(5*p/6)*[sin{5(wt+p/6)}-sin{5(wt-p/2)}] this gives
Vab=(4VS/5p)*cos(5*p/6)*sin(5*p/3)*cos{5(wt-p/6)}
Vline5RMS=(0.8/p)*(31/2/2)*(31/2/2)*Vs/21/2=0.1350*VS
From (31): Vline1RMS=(3/p)Vs/21/2=0.6752VS
Ratio=0.1350/0.6752=0.2=20%

Find the ratio of the rms value of the lowest order harmonic to the
fundamental rms in line voltage for a 180o conduction three phase inverter.

From equation 34, the third harmonic vanishes. Hence the lowest order
harmonic is the fifth (n=5).
From (34): Vline5RMS=(4VS/5p)*cos(5*p/6)/21/2=(0.8/p)*(31/2/2)*Vs/21/2=0.1559*VS
From (36): Vline1RMS=61/2VS/p=0.7797VS
Ratio=0.1559/0.7797=0.2=20%

37
 Numerical Problems-V
A Single Phase Single PWM inverter has nominal dc input 12 V and rms
output 240 V with third harmonic elimination. Find the transformer ratio for
zero regulation. Find the rms value of the third harmonic in the output if the
supply voltage reduces by 5% and the output rms remains constant.

From equation (49) Vn= 0.90*VS*sin(n*M*p/2)/n

Third harmonic vanishes for M=2/3
Hence from (46) primary nominal rms Vnomrms=M1/2*VS=(2/3)1/2*12= 9.798 V
Hence transformation ratio=240/9.798=24.5
As the output (secondary) rms remains same, the primary rms also is same.
VS=0.95*12=11.4 V From equation (46): 9.798=11.4*M1/2
This gives M=0.7387
From (49): primary rms V3=|0.90*11.4*sin(3*0.7387*p/2)/3|=1.1386 V
Secondary rms=24.5*1.1386=27.89 V

A Single Phase Single PWM inverter has fifth harmonic eliminated. Find the
rms value of the third harmonic for a dc supply of 216 V.

M=2/5 for fifth harmonic elimination.

From (49): V3= 0.90*216*sin(3*p/5)/3=61.63 V

38
 Numerical Problems-VI
A Sinusoidal PWM inverter with output frequency 50 Hz is to have 99th as
the lowest order harmonic. Find the carrier frequency.

The lowest order harmonic is 2*p-1=99 Hence 2*p=100

From (43): fc=2*p*fo =100*50=5 kHz

A Sinusoidal PWM inverter has dc supply 96 V. What can be the maximum

value of the peak fundamental output voltage?

V1pk=4*VS/p=4*96/p=122.23 V

39