UNIT-V: Input/Output Organization: Accredited by Naac & Nba (Cse, It, Ece, Eee&Me)

LAKIREDDY BALI REDDY COLLEGE OF ENGINEERING
(AUTONOMOUS)
ACCREDITED BY NAAC & NBA (CSE, IT, ECE, EEE&ME)
APPROVED BY AICTE, NEW DELHI AND AFFILIATED TO JNTUK, KAKINADA
L.B.REDDY NAGAR, MYLAVARAM-521230, KRISHNA DIST., ANDHRA PRADESH, INDIA
UNIT-V: Input/Output Organization
Department of ECE 04-02-2021

(AUTONOMOUS)
Address Lines
System
Data Lines Bus
Control Lines
I/O Module
2 Links to
peripheral
devices
Figure 7.1 Generic Model of an I/O Module

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Three categories:
External Devices  Human readable
◼ Provide a means of  Suitable for communicating
exchanging data between with the computer user
the external environment  Video display terminals (VDTs),
and the computer printers
 Machine readable
◼ Attach to the computer by a
 Suitable for communicating
link to an I/O module with equipment
◼ The link is used to exchange  Magnetic disk and tape
control, status, and data systems, sensors and actuators
3 between the I/O module and
the external device  Communication
 Suitable for communicating
◼ Peripheral device with remote devices such as a
terminal, a machine-readable
◼ An external device device, or another computer
connected to an I/O module
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Control Status Data bits

signals from signals to to and from
I/O module I/O module I/O module
Control Buffer
Logic
Transducer
4
Data (device-unique)
to and from
environment
Figure 7.2 Block Diagram of an External Device

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Keyboard/Monitor Most common means of computer/user interaction

User provides input through the keyboard
International Reference Alphabet The monitor displays data provided by the
(IRA) computer
 Basic unit of exchange is the character Keyboard Codes

 Associated w ith each character is a code
 When the user depresses a key it generates an
 Each character in this code is represented by a unique 7- electronic signal that is interpreted by the
bit binary code
transducer in the keyboard and translated into
 128 different characters can be represented
the bit pattern of the corresponding IRA code
 Characters are of two types:
 This bit pattern is transmitted to the I/O module
 Printable
in the computer
 Alphabetic, numeric, and special characters that can
be printed on paper or displayed on a screen  On output, IRA code characters are
5  Control transmitted to an external device from the I/O
module
 Have to do with controlling the printing or displaying of
characters
 The transducer interprets the code and sends
 Example is carriage return
the required electronic signals to the output
 Other control charact ers are concerned with
communications procedures device either to display the indicated
character or perform the requested control
function

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Major functions for an I/O module

Control and timing
• Coordinates the flow of traffic between internal resources and external devices
Processor communication
• Involves command decoding, data, status reporting, address recognition
Device communication
• Involves commands, status information, and data
6 Data buffering
• Performs the needed buffering operation to balance device and memory speeds
Error detection
• Detects and reports transmission errors

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Interface to Interface to
System Bus External Device
Data
Data Registers External
Device
Data Status
Interface
Lines
Logic
Status/Control Registers Control
Address
Lines Data
External
I/O Device
7 Logic Interface
Status
Control Logic
Lines Control
Figure 7.3 Block Diagram of an I/O Module

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Programmed I/O
Three techniques are possible for I/O operations:
◼ Programmed I/O
◼ Data are exchanged between the processor and the I/O module
◼ Processor executes a program that gives it direct control of the I/O operation
◼ When the processor issues a command it must wait until the I/O operation is complete
◼ If the processor is faster than the I/O module this is wasteful of processor time
◼ Interrupt-driven I/O
◼ Processor issues an I/O command, continues to execute other instructions, and is
8
interrupted by the I/O module when the latter has completed its work
◼ Direct memory access (DMA)
◼ The I/O module and main memory exchange data directly without processor
involvement

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I/O Commands
◼ There are four types of I/O commands that an I/O module may receive when it is
addressed by a processor:
1) Control
- used to activate a peripheral and tell it what to do
2) Test
- used to test various status conditions associated with an I/O module and its
peripherals
3) Read
9 - causes the I/O module to obtain an item of data from the peripheral and place it in an
internal buffer
4) Write
- causes the I/O module to take an item of data from the data bus and subsequently
transmit that data item to the peripheral
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Issue Read Issue Read CPU I/O Issue Read CPU DMA
command to CPU I/O command to Do something block command Do something
I/O module I/O module else to I/O module else
Read status Read status Interrupt Read status Interrupt

of I/O I/O CPU of I/O of DMA
I/O CPU
module module module DMA CPU
Not
ready Next instruction
Check Error Check Error
status condition status condition (c) Direct memory access
Ready Ready
Read word Read word
from I/O I/O CPU from I/O I/O CPU
Module Module
Write word Write word

CPU memory CPU memory
into memory into memory
10
No No
Done? Done?
Yes Yes
Next instruction Next instruction
(a) Programmed I/O (b) Interrupt-driven I/O
Figure 7.4 Three Techniques for Input of a Block of Data

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With programmed I/O there is a close correspondence between the I/O-related instructions that
the processor fetches from memory and the I/O commands that the processor issues to an I/O
module to execute the instructions
Each I/O device connected through I/O modules is given a
I/O unique identifier or address
Instructions
The form of the

When the processor
issues an I/O Memory-mapped I/O
instruction depends command, the
on the way in which command contains the
external devices are address of the desired
addressed device
11
Thus each I/O module There is a single address space for A single read line and a single write
must interpret the memory locations and I/O devices line are needed on the bus
address lines to
determine if the
command is for itself

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◼ Memory mapped I/O

◼ Devices and memory share an address space
◼ I/O looks just like memory read/write
◼ No special commands for I/O
◼ Large selection of memory access commands available
◼ Isolated I/O
◼ Separate address spaces
12
◼ Need I/O or memory select lines
◼ Special commands for I/O
◼ Limited set

(AUTONOMOUS)
7 6 5 4 3 2 1 0
516 Keyboard input data r egister
7 6 5 4 3 2 1 0
Keyboard input status
517
and control register
1 = ready Set to 1 to
0 = busy start read
ADDRESS INSTRUCTION OPERAND COMMENT

200 Load AC "1" Load accumulator
Store AC 517 Initiate keyboard read
202 Load AC 517 Get status byte
Branch if Sign = 0 202 Loop until ready
Load AC 516 Load data byte
(a) Memory-mapped I/O
13 ADDRESS
200
INSTRUCTION
Load I/O
OPERAND
5
COMMENT
Initiate keyboard read
201 Test I/O 5 Check for completion
Branch Not Ready 201 Loop until complete
In 5 Load data byte
(b) Isolated I/O
Figure 7.5 Memory-Mapped and Isolated I/O

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The problem with programmed I/O is that the processor

has to wait a long time for the I/O module to be ready for
either reception or transmission of data
Interrupt-
An alternative is for the processor to issue an I/O
Driven I/O command to a module and then go on to do some
other useful work
The I/O module will then interrupt the processor to

request service when it is ready to exchange data
14 with the processor
The processor executes the data transfer and

resumes its former processing
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Hardware Software
Device controller or
other system hardware
issues an interrupt
Save remainder of
process state
information
Processor finishes
execution of current
instruction
Process interrupt
Processor signals
acknowledgment
of interrupt
Restore process state
information
Processor pushes PSW
and PC onto control
stack
15 Restore old PSW
and PC
Processor loads new
PC value based on
interrupt
Department of ECE Figure 7.6 Simple Interrupt Processing 04-02-2021

(AUTONOMOUS)
T–M T–M
Y N+1
Control Control
Stack Stack
T T
N+1 Y+L
Program Program
Counter Counter
Y Start Y Start
Interrupt General Interrupt General
Service Registers Service Registers
Y+L Return Routine T Y+L Return Routine T–M
Stack Stack
Pointer Pointer
Processor Processor
T–M T
N User's N User's
N+1 N+1
16
Program Program
Main Main
Memory Memory
(a) Interrupt occurs after instruction

(b) Return from interrupt
at location N
Figure 7.7 Changes in Memory and Registers for an Interrupt

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Design Issues
• Because there
will be multiple
I/O modules
how does the
processor
determine which
Two design device issued
issues arise in the interrupt?
implementing
interrupt I/O: • If multiple
17 interrupts have
occurred how
does the
processor
decide which
one to process?
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Device Identification
Four general categories of techniques are in common use:
◼ Multiple interrupt lines
◼ Between the processor and the I/O modules
◼ Most straightforward approach to the problem
◼ Consequently even if multiple lines are used, it is likely that each line will have multiple I/O modules
attached to it
◼ Software poll
◼ When processor detects an interrupt it branches to an interrupt-service routine whose job is to poll
each I/O module to determine which module caused the interrupt
◼ Time consuming
◼ Daisy chain (hardware poll, vectored)

◼ The interrupt acknowledge line is daisy chained through the modules
◼ Vector – address of the I/O module or some other unique identifier
18 ◼ Vectored interrupt – processor uses the vector as a pointer to the appropriate device-service routine,
avoiding the need to execute a general interrupt-service routine first
◼ Bus arbitration (vectored)

◼ An I/O module must first gain control of the bus before it can raise the interrupt request line
◼ When the processor detects the interrupt it responds on the interrupt acknowledge line
◼ Then the requesting module places its vector on the data lines

(AUTONOMOUS)
Slave
82C59A
interrupt
controller
External device 00 IR0
External device 01 IR1 INT
IR2
IR3
IR4
IR5
IR6
Slave Master
82C59A 82C59A
interrupt interrupt 80386
controller controller processor
External device 08 IR0 IR0
External device 09 IR1 INT IR1 INT INTR
IR2 IR2
IR3 IR3
IR4 IR4
IR5 IR5
IR6 IR6
External device 15 IR7 IR7
19 Slave
82C59A
interrupt
controller
External device 57 IR1 INT
IR2
IR3
IR4
IR5
IR6
Department of ECE
Figure 7.8 Use of the 82C59A Interrupt Controller 04-02-2021
(AUTONOMOUS)
PA3 1 40 PA4
Power +5 V PA2 2 39 PA5
supplies Group Group A
GND Port A PA1 3 38 PA6
A I/O
control (8) PA7 - PA0 PA0 4 37 PA7
RD 5 36 WR
CS 6 35 Reset
Bi-directional Group A GND 7 34 D0
data bus Data Port C I/O A1 8 33 D1
bus upper (4) PC7 - PC4 A0 9 8255A 32 D2
D7 - D0 buffer PC7 10 31 D3
8-bit Group B PC6 11 30 D4
internal Port C I/O PC5 12 29 D5
data bus Lower(4) PC3 - PC0
PC4 13 28 D6
RD PC3 14 27 D7
Read/
WR PC2 15 26 V
write Group
A1 Group B
control B PC1 16 25 PB7
A0 Port B I/O
logic control PC0 17 24 PB6
(8) PB7 - PB0
Reset PB0 18 23 PB5
20 CS
PB1
PB2
19
20
22
21
PB4
PB3
(a) Block diagram (b) Pin layout
Figure 7.9 The Intel 8255A Programmable Peripheral Interface

(AUTONOMOUS)
Interrupt
request
C3 A0 R0
A1 R1
A2 R2
A3 R3
INPUT A4 R4 KEYBOARD
PORT A5 R5
A6 Shift
A7 Control
C4 Data ready
C5 Acknowledge
82C55A
B0 S0
B1 S1
B2 S2
B3 S3
OUTPUT DISPLAY
B4 S4
PORT
B5 S5
21 B6
B7
Backspace
Clear
C1 Data ready
C2 Acknowledge
C6 Blanking
C0 C7 Clear line
Interrupt
request
Figure 7.11 Keyboard/Display Interface to 82C55A

(AUTONOMOUS)
Drawbacks of Programmed and Interrupt-Driven I/O
◼ Both forms of I/O suffer from two inherent drawbacks:
1) The I/O transfer rate is limited by the speed with which the processor
can test and service a device
2) The processor is tied up in managing an I/O transfer; a number of

instructions must be executed for each I/O transfer
◼ When large volumes of data are to be moved a more efficient

22
technique is direct memory access (DMA)

(AUTONOMOUS)
Data
count
Data lines Data

register
Address
Address lines register
Request to DMA
Acknowledge from DMA
Control
Interrupt
logic
Read
23 Write
Figure 7.12 Typical DMA Block Diagram

(AUTONOMOUS)
Time
Instruction Cycle
Processor Processor Processor Processor Processor Processor

Cycle Cycle Cycle Cycle Cycle Cycle
Fetch Decode Fetch Execute Store Process

Instruction Instruction Operand Instruction Result Interrupt
24 DMA Interrupt
Breakpoints Breakpoint
Figure 7.13 DMA and Interrupt Breakpoints During an Instruction Cycle

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Processor DMA I/O I/O Memory
(a) Single-bus, detached DMA
Processor DMA DMA Memory
I/O
I/O I/O
(b) Single-bus, Integrated DMA-I/O
System bus
Processor DMA Memory
25 I/O bus
I/O I/O I/O
(c) I/O bus
Figure 7.14 Alternative DMA Configurations

(AUTONOMOUS)
CPU
Data bus
DREQ
HRQ
8237 DMA Main Disk
chip memory controller
HLDA DACK
Address bus
26
Control bus (IOR, IOW, MEMR, MEMW)
DACK = DMA acknowledge

DREQ = DMA request
HLDA = HOLD acknowledge
HRQ = HOLD request
Figure 7.15 8237 DMA Usage of System Bus
(AUTONOMOUS)
Fly-By DMA Controller
Data does not pass 8237 contains four

through and is not DMA channels
stored in DMA chip • Programmed
• DMA only between independently
I/O port and Can do memory to
memory via register • Any one active
memory • Numbered 0, 1, 2,
• Not between two and 3
27 I/O ports or two
memory locations

(AUTONOMOUS)
Bit Command Status Mode Single Mask All Mask
Memory-to- Channel 0 has Clear/set

D0 channel 0 mask
Intel
memory E/D reached TC
Select channal bit
Channel select
Channel 0 mask bit Clear/set
Channel 1 has
8237A
D1 address hold channel 1 mask
reached TC
E/D bit
Clear/set
Registers
Channel 2 has Clear/set mask
D2 Controller E/D channel 2 mask
reached TC bit
Verify/write/ bit
read transfer Clear/set
Normal/compre Channel 3 has
D3 channel 3 mask
ssed timing reached TC
bit
Auto-
Fixed/rotating Channel 0
D4 initialization
priority request
E/D
Address
28 D5
Late/extended
write selection
Channel 0
request
increment/
decrement
Not used
Not used
select
D6 DREQ sense Channel 0

active high/low request
Demand/single/
DACK sense Channel 0
D7 block/cascade
active high/low request
mode select
E/D = enable/disable
TC = terminal count
(AUTONOMOUS)
Evolution of the I/O Function
4. The I/O module is given direct
1. The CPU directly controls a access to memory via DMA. It can
peripheral device. now move a block of data to or
from memory without involving
2. A controller or I/O module the CPU, except at the beginning
is added. The CPU uses and end of the transfer.
programmed I/O without 5. The I/O module is enhanced to
interrupts. become a processor in its own
right, with a specialized
3. Same configuration as in instruction set tailored for I/O
step 2 is used, but now
29 interrupts are employed. 6. The I/O module has a local
The CPU need not spend memory of its own and is, in fact, a
time waiting for an I/O computer in its own right. With
operation to be performed, this architecture a large set of I/O
thus increasing efficiency. devices can be controlled with
minimal CPU involvement.
(AUTONOMOUS)
Data and
address channel
to main memory
Selector
channel
Control signal I/O I/O

path to CPU Controller Controller
(a) Selector
Data and
address channel
to main memory
Multi-
plexor
channel
Control signal
path to CPU I/O
Controller
I/O
Controller
30 I/O
Controller
I/O
Controller
(b) Multiplexor
Figure 7.18 I/O Channel Architecture

(AUTONOMOUS)
Standard I/O interfaces

 I/O device is connected to a computer using an interface circuit.
 Do we have to design a different interface for every combination of an I/O device and a
computer?
 A practical approach is to develop standard interfaces and protocols.
 A personal computer has:
 A motherboard which houses the processor chip, main memory and some I/O
interfaces.
 A few connectors into which additional interfaces can be plugged.
31  Processor bus is defined by the signals on the processor chip.
 Devices which require high-speed connection to the processor are connected directly
to this bus.

(AUTONOMOUS)
 Because of electrical reasons only a few devices can be

connected directly to the processor bus.
 Motherboard usually provides another bus that can support
more devices.
 Processor bus and the other bus (called as expansion bus) are interconnected by a
circuit called “bridge”.
 Devices connected to the expansion bus experience a small delay in data transfers.
32  Design of a processor bus is closely tied to the architecture of

the processor.
 No uniform standard can be defined.
 Expansion bus however can have uniform standard defined.

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 A number of standards have been developed for the

expansion bus.
 Some have evolved by default.
 IBM’s Industry Standard Architecture.
 Three widely used bus standards:
 PCI (Peripheral Component Interconnect)
 SCSI (Small Computer System Interface)
33  USB (Universal Serial Bus)

(AUTONOMOUS)
Processor
Main
memory
Bridge circuit translates
signals and protocols from
processor bus to PCI bus.
Processor bus
Bridge
PCI bus
Expansion bus on
the motherboard
Additional SCSI Ethernet USB ISA
memory controller Interface controller
SCSI b us
IDE
34 V ideo
disk
Disk CD-R OM
controller controller
CD-
Disk 1 Disk 2 R OM K eyboard Game

(AUTONOMOUS)
PCI Bus
 Peripheral Component Interconnect
 Introduced in 1992
 Low-cost bus
 Processor independent
 Plug-and-play capability
 In today’s computers, most memory transfers involve a burst of data rather than just one
word. The PCI is designed primarily to support this mode of operation.
 The bus supports three independent address spaces: memory, I/O, and configuration.
 we assumed that the master maintains the address information on the bus until data transfer
35
is completed. But, the address is needed only long enough for the slave to be selected. Thus,
the address is needed on the bus for one clock cycle only, freeing the address lines to be used
for sending data in subsequent clock cycles. The result is a significant cost reduction.
 A master is called an initiator in PCI terminology. The addressed device that responds to read
and write commands is called a target.
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Data transfer signals on the PCI bus.
36

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37

(AUTONOMOUS)
Device Configuration
 When an I/O device is connected to a computer, several actions are needed to
configure both the device and the software that communicates with it.
 PCI incorporates in each I/O device interface a small configuration ROM
memory that stores information about that device.
 The configuration ROMs of all devices are accessible in the configuration
address space. The PCI initialization software reads these ROMs and determines
whether the device is a printer, a keyboard, an Ethernet interface, or a disk
controller. It can further learn bout various device options and characteristics.
 Devices are assigned addresses during the initialization process.
 This means that during the bus configuration operation, devices cannot be
38 accessed based on their address, as they have not yet been assigned one.
 Hence, the configuration address space uses a different mechanism. Each device
has an input signal called Initialization Device Select, IDSEL#
 Electrical characteristics:
 PCI bus has been defined for operation with either a 5 or 3.3 V power supply
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SCSI Bus
 The acronym SCSI stands for Small ComputerSystem Interface.
 It refers to a standard bus defined by the American National Standards Institute
(ANSI) under the designation X3.131 .
 In the original specifications of the standard, devices such as disks are connected
to a computer via a 50-wire cable, which can be up to 25 meters in length and can
transfer data at rates up to 5 megabytes/s.
 The SCSI bus standard has undergone many revisions, and its data transfer
capability has increased very rapidly, almost doubling every two years.
39  SCSI-2 and SCSI-3 have been defined, and each has several options.
 Because of various options SCSI connector may have 50, 68 or 80 pins.

(AUTONOMOUS)
 Devices connected to the SCSI bus are not part of the address space of the processor
 The SCSI bus is connected to the processor bus through a SCSI controller. This controller uses
DMA to transfer data packets from the main memory to the device, or vice versa.
 A packet may contain a block of data, commands from the processor to the device, or status
information about the device.
 A controller connected to a SCSI bus is one of two types – an initiator or a target.
 An initiator has the ability to select a particular target and to send commands specifying the
operations to be performed. The disk controller operates as a target. It carries out the commands it
receives from the initiator.
 The initiator establishes a logical connection with the intended target.
40  Once this connection has been established, it can be suspended and restored as needed to transfer
commands and bursts of data.
 While a particular connection is suspended, other device can use the bus to transfer information.
 This ability to overlap data transfer requests is one of the key features of the SCSI bus that leads to
its high performance.
(AUTONOMOUS)
 Data transfers on the SCSI bus are always controlled by the target controller.
 To send a command to a target, an initiator requests control of the bus and,
after winning arbitration, selects the controller it wants to communicate with
and hands control of the bus over to it.
 Then the controller starts a data transfer operation to receive a command
from the initiator.
41

(AUTONOMOUS)
 Assume that processor needs to read block of data from a disk drive and that data are stored in disk sectors
that are not contiguous.
 The processor sends a command to the SCSI controller, which causes the following sequence of events to take
place:
1. The SCSI controller, acting as an initiator, contends for control of the bus.
2. When the initiator wins the arbitration process, it selects the target controller and hands over control
of the bus to it.
3. The target starts an output operation (from initiator to target); in response to this, the initiator sends a
command specifying the required read operation.
4. The target, realizing that it first needs to perform a disk seek operation, sends a message to the
initiator indicating that it will temporarily suspend the connection between them. Then it releases the
42 bus.
5. The target controller sends a command to the disk drive to move the read head to the first sector
involved in the requested read operation. Then, it reads the data stored in that sector and stores them
in a data buffer. When it is ready to begin transferring data to the initiator, the target requests control
of the bus. After it wins arbitration, it reselects the initiator controller, thus restoring the suspended
connection.

(AUTONOMOUS)
6. The target transfers the contents of the data buffer to the initiator and then
suspends the connection again
7. The target controller sends a command to the disk drive to perform another seek
operation. Then, it transfers the contents of the second disk sector to the initiator
as before. At the end of this transfers, the logical connection between the two
controllers is terminated.
8. As the initiator controller receives the data, it stores them into the main memory
using the DMA approach.
9. The SCSI controller sends as interrupt to the processor to inform it that the
43 requested operation has been completed

(AUTONOMOUS)
The SCSI bus signals.
Category Name Function
Data – DB(0) to Data lines: Carry one byte of information

– DB(7) during the information transfer phase and
iden tify device during arbitration,selection and
reselection phases
– DB(P) Parity bit for the data bus
Phase – BSY Busy: Asserted when the bus is notfree
– SEL Selection: Asserted during selection and

reselection
– C/D
44 Information Control/Data: Asserted during transfer of
type con trol information (command, status or
message)
– MSG Message: indicates thatthe information being

transferred is a message

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Category Name Function
Handshake – REQ Request: Asserted by a target to requesta data

transfercycle
– ACK Acknowledge: Asserted by the initiator when it

has completed a data transfer op eration
Direction of – I/O Input/Output: Asserted to indicate an input

transfer operation (relative to the initiator)
Other – ATN Attention: Asserted by an initiator when it

45 wishes to send a message to a target
– RST Reset: Causes all device controls to disconnect

from the bus and assume their start-upstate

(AUTONOMOUS)
Main Phases involved
 Arbitration
 A controller requests the bus by asserting BSY and by asserting it’s associated data
line
 When BSY becomes active, all controllers that are requesting bus examine data
lines
 Selection
 Controller that won arbitration selects target by asserting SEL and data line of
target. After that initiator releases BSY line.
 Target responds by asserting BSY line
46  Target controllerwill have control on the bus from then

 Information Transfer
 Handshaking signals are used between initiator and target
 At the end target releases BSY line
 Reselection
(AUTONOMOUS)
Targets examine ID
Arbitration and selection on the SCSI bus. Device 6 wins arbitration
and selects device 2.
DB 2
DB 5
DB 6
BS Y
47
SEL
Free Arbitration Selection

(AUTONOMOUS)
USB
 Universal Serial Bus (USB) is an industry standard developed
through a collaborative effort of several computer and
communication companies, including Compaq, Hewlett-Packard,
Intel, Lucent, Microsoft, Nortel Networks, and Philips.
 Speed
 Low-speed(1.5 Mb/s)
 Full-speed(12 Mb/s)
 High-speed(480 Mb/s)
48  Port Limitation
 Device Characteristics
 Plug-and-play

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Universal Serial Bus tree structure
Host computer
Root
hub
Hub Hub
49 I/O I/O I/O I/O

Hub device device device device
I/O I/O
device device

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 To accommodate a large number of devices that can be added or removed at any

time, the USB has the tree structure as shown in the figure.
 Each node of the tree has a device called a hub, which acts as an intermediate
control point between the host and the I/O devices. At the root of the tree, a root
hub connects the entire tree to the host computer. The leaves of the tree are the
I/O devices being served (for example, keyboard, Internet connection, speaker, or
digital TV)
 In normal operation, a hub copies a message that it receives from its upstream
connection to all its downstream ports. As a result, a message sent by the host
computer is broadcast to all I/O devices, but only the addressed device will
50 respond to that message. However, a message from an I/O device is sent only
upstream towards the root of the tree and is not seen by other devices. Hence, the
USB enables the host to communicate with the I/O devices, but it does not enable
these devices to communicate with each other.

(AUTONOMOUS)
Addressing
 When a USB is connected to a host computer, its root hub is attached to the processor bus, where it
appears as a single device. The host software communicates with individual devices attached to the USB
by sending packets of information, which the root hub forwards to the appropriate device in the USB
tree.
 Each device on the USB, whether it is a hub or an I/O device, is assigned a 7-bit address. This address is
local to the USB tree and is not related in any way to the addresses used on the processor bus.
 A hub may have any number of devices or other hubs connected to it, and addresses are assigned
arbitrarily. When a device is first connected to a hub, or when it is powered on, it has the address 0. The
hardware of the hub to which this device is connected is capable of detecting that the device has been
connected, and it records this fact as part of its own status information. Periodically, the host polls each
hub to collect status information and learn about new devices that may have been added or
disconnected.
51
 When the host is informed that a new device has been connected, it uses a sequence of commands to
send a reset signal on the corresponding hub port, read information from the device about its
capabilities, send configuration information to the device, and assign the device a unique USB address.
Once this sequence is completed the device begins normal operation and responds only to the new
address.

(AUTONOMOUS)
USB Protocols
 All information transferred over the USB is organized in packets, where a packet consists of one
or more bytes of information. There are many types of packets that perform a variety of control
functions.
 The information transferred on the USB can be divided into two broad categories: control and
data.
 Control packets perform such tasks as addressing a device to initiate data transfer,
acknowledging that data have been received correctly, or indicating an error.
 Data packets carry information that is delivered to a device.
 A packet consists of one or more fields containing different kinds of information. The first field
52 of any packet is called the packet identifier, PID, which identifies the type of that packet.
 They are transmitted twice. The first time they are sent with their true values, and the second
time with each bit complemented
 The four PID bits identify one of 16 different packet types. Some control packets, such as ACK
(Acknowledge), consist only of the PID byte.
(AUTONOMOUS)
USB packet format
53

(AUTONOMOUS)
An output transfer Host Hub I/O Device
Token
Data0
ACK
Time
Token
Data0
ACK
Token
Data1
54 ACK
Token
Data1
ACK

(AUTONOMOUS)
Isochronous Traffic on USB
 One of the key objectives of the USB is to support the transfer of isochronous data.
 Devices that generates or receives isochronous data require a time reference to control the
sampling process.
 To provide this reference. Transmission over the USB is divided into frames of equal length.
 A frame is 1ms long for low-and full-speed data.
 The root hub generates a Start of Frame control packet (SOF) precisely once every 1 ms to mark the
beginning of a new frame.
 The arrival of an SOF packet at any device constitutes a regular clock signal that the device can use
for its own purposes.
 To assist devices that may need longer periods of time, the SOF packet carries an 11-bit frame
55
number.
 Following each SOF packet, the host carries out input and output transfers for isochronous
devices.
 This means that each device will have an opportunity for an input or output transfer once every 1
ms.
(AUTONOMOUS)
Electrical Characteristics
 The cables used for USB connections consist of four wires.
 Two are used to carry power, +5V and Ground.
 Thus, a hub or an I/O device may be powered directly from the bus, or it
may have its own external power connection.
 The other two wires are used to carry data.
 Different signaling schemes are used for different speeds of transmission.
 At low speed, 1s and 0s are transmitted by sending a high voltage state (5V)
56 on one or the other o the two signal wires. For high-speed links, differential
transmission is used.

UNIT-V: Input/Output Organization: Accredited by Naac & Nba (Cse, It, Ece, Eee&Me)

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LAKIREDDY BALI REDDY COLLEGE OF ENGINEERING

UNIT-V: Input/Output Organization

Department of ECE 04-02-2021

Figure 7.1 Generic Model of an I/O Module

Department of ECE 04-02-2021

Control Status Data bits

Figure 7.2 Block Diagram of an External Device

Keyboard/Monitor Most common means of computer/user interaction

 Basic unit of exchange is the character Keyboard Codes

Department of ECE 04-02-2021

Major functions for an I/O module

Department of ECE 04-02-2021

Figure 7.3 Block Diagram of an I/O Module

Department of ECE 04-02-2021

Department of ECE 04-02-2021

Read status Read status Interrupt Read status Interrupt

Write word Write word

Department of ECE 04-02-2021

The form of the

Department of ECE 04-02-2021

◼ Memory mapped I/O

Department of ECE 04-02-2021

ADDRESS INSTRUCTION OPERAND COMMENT

(a) Memory-mapped I/O

(b) Isolated I/O

Figure 7.5 Memory-Mapped and Isolated I/O

Department of ECE 04-02-2021

The problem with programmed I/O is that the processor

The I/O module will then interrupt the processor to

The processor executes the data transfer and

Department of ECE Figure 7.6 Simple Interrupt Processing 04-02-2021

(a) Interrupt occurs after instruction

Figure 7.7 Changes in Memory and Registers for an Interrupt

Department of ECE 04-02-2021

◼ Daisy chain (hardware poll, vectored)

◼ Bus arbitration (vectored)

Department of ECE 04-02-2021

Figure 7.9 The Intel 8255A Programmable Peripheral Interface

Department of ECE 04-02-2021

Figure 7.11 Keyboard/Display Interface to 82C55A

2) The processor is tied up in managing an I/O transfer; a number of

◼ When large volumes of data are to be moved a more efficient

Department of ECE 04-02-2021

Data lines Data

Figure 7.12 Typical DMA Block Diagram

Department of ECE 04-02-2021

Processor Processor Processor Processor Processor Processor

Fetch Decode Fetch Execute Store Process

Figure 7.13 DMA and Interrupt Breakpoints During an Instruction Cycle

Department of ECE 04-02-2021

Processor DMA I/O I/O Memory

(a) Single-bus, detached DMA

Processor DMA DMA Memory

(b) Single-bus, Integrated DMA-I/O

Processor DMA Memory

I/O I/O I/O

(c) I/O bus

Figure 7.14 Alternative DMA Configurations

Department of ECE 04-02-2021

DACK = DMA acknowledge

Fly-By DMA Controller

Data does not pass 8237 contains four

Department of ECE 04-02-2021