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Dell / Compal Confidential: Schematic Document
Dell / Compal Confidential: Schematic Document
X76@ : 76 level
46@ : 46 level
@ : Nopop component BOM config
CONN@ : Connector component UMA : UMA@,EMI@,ESD@,RF@,XDP@
XDP@ : XDP function DIS SUN : SUN@,DIS@,EMI@,ESD@,RF@,XDP@
UMA@ : Only for UMA ZZZ R1@
RF@ : RF parts
GDDR5*8 GDDR5*8
P.27 Conn. P.6
P.34 P.35
3 3
LPC Bus
SMBus
33MHz
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Block diagram
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9981P
Date: Saturday, March 09, 2013 Sheet 2 of 55
A B C D E
A B C D E
Compal Confidential
Project Code : VAW00 / VAW01
File Name : LA-9981P / LA-9982P
1 1
LS-9101P (PWR/B)
UE5
Lid (SA00003VQ00)
JMINI PJPDC
PWR-BTN FFC MINI Card
5 pin
4 pin JLVDS
40 pin
JKB
30 pin
2 2
JFAN LS-9102P (USB/B)
3 pin
HDMI
JHDMI JTP
6 pin
JODD
JTOUCH JPWR USB JUSB4
6 pin 4 pin
USB-DB FFC
JLAN RJ-45
XDP LA-9981P M/B 8 pin
8 pin
Hot Bar
JXDP
LA-9982P M/B
JUSB1 USB Top Side JHDD
Bottom Side JDB
8 pin
TP-MB FFC
6 pin JUSB2 USB
(OAK 15")
JRTC
2 pin
JUSB3 USB JSPK
3
4 pin JREAD 3
RTC
Card
TP-Module JHP HP Reader
Led1 Led3
Led2 Led4
TP-BTN FFC
4 pin
LS-9103P (TP-BTN/B)
4 pin
Hot Bar
SW2 SW3
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DB block diagram
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-9981P
Date: Saturday, March 09, 2013 Sheet 3 of 55
A B C D E
A
PCI EXPRESS
EC_SMB_CK2
EC_SMB_DA2
KB9012 V V
Lane 1
SMBCLK
SMBDATA
ULT V V V V
Link Lane 2
SML0CLK ULT
SML0DATA
Lane 3 10/100 LAN
SML1CLK ULT
SML1DATA
Lane 4 MINI Card (WLAN)
2.2K 10K
SMBUS Address [0x9a]
2.2K
+3.3V_ALW_PCH 10K
+3VS
N-MOS
AP2 MEM_SMBCLK DDR_XDP_WLAN_TP_SMBCLK 202 DIMMA SMBUS Address [A0]
N-MOS
AH1 MEM_SMBDATA DDR_XDP_WLAN_TP_SMBDAT 200
D D
1K
202 DIMMB
+3.3V_ALW_PCH SMBUS Address [A4]
1K 200
AN1 SML0CLK
MCH 0 ohm
AK1 SML0DATA DDR_XDP_SMBCLK_R1 53 XDP1 SMBUS Address [TBD]
Shark bay 0 ohm
2.2K DDR_XDP_SMBDAT_R1 51
2.2K
+3.3V_ALW_PCH
30 JMINI SMBUS Address [TBD]
N-MOS 32
AN1 SML1_SMBCLK EC_SMB_CK2
N-MOS
AK1 SML1_SMBDATA EC_SMB_DA2
5 JTP SMBUS Address [TBD]
6
2.2K
C 2.2K
+3VALW C
2.2K
2.2K
+3VS_VGA
N-MOS
VGA_SMB_CK2 T4 UV28 GPU SMBUS Address [0xXX]
N-MOS
VGA_SMB_DA2 T3
2.2K
2.2K
+3VALW
0 ohm
77 EC_SMB_CK1 SCL 11 PU701 POWER SMBUS Address [0x12]
0 ohm Charger
KBC 78 EC_SMB_DA1 SDA 10
B
KB9012A4 100 ohm
B
A A
UC1 4200Ui5G2R1@
i5-4200U-15W-GT2-QS
CL8064701477702-QEVE-C0-1.6G_BGA1168~D
SA00006SM0L
UC1 4010Ui3G2R1@
HASWELL_MCP_E
UC1A
i3-4010U-15W-GT2-QS
CL8064701478202-QEVG-C0-1.7G_BGA1168~D
SA00006SX0L DDI1_LANE_N0 C54 C45 EDP_CPU_LANE_N0
<20> DDI1_LANE_N0 DDI1_LANE_P0 C55 DDI1_TXN0 EDP_TXN0 B46 EDP_CPU_LANE_P0 EDP_CPU_LANE_N0 <19>
D <20> DDI1_LANE_P0 B58 DDI1_TXP0 EDP_TXP0 A47 EDP_CPU_LANE_P0 <19> D
UC1 4500Ui7G2R1@ DDI1_LANE_N1 EDP_CPU_LANE_N1
<20> DDI1_LANE_N1 DDI1_LANE_P1 C58 DDI1_TXN1 EDP_TXN1 B47 EDP_CPU_LANE_P1 EDP_CPU_LANE_N1 <19>
<20> DDI1_LANE_P1 B55 DDI1_TXP1 EDP_TXP1 EDP_CPU_LANE_P1 <19>
DDI1_LANE_N2
<20> DDI1_LANE_N2 DDI1_TXN2
DDI1_LANE_P2 A55 C47
<20> DDI1_LANE_P2 DDI1_LANE_N3 A57 DDI1_TXP2 EDP_TXN2 C46
i7-4500U-15W-GT2-QS <20> DDI1_LANE_N3 B57 DDI1_TXN3 EDP_TXP2 A49 COMPENSATION PU FOR eDP
DDI1_LANE_P3
<20> DDI1_LANE_P3 DDI1_TXP3 DDI EDP EDP_TXN3 B49
CL8064701477202-QEVD-C0-1.8G_BGA1168~D EDP_TXP3
C51
SA00006SL0L C50 DDI2_TXN0 A45 EDP_CPU_AUX# +VCCIOA_OUT
C53 DDI2_TXP0 EDP_AUXN B45 EDP_CPU_AUX EDP_CPU_AUX# <19>
DDI2_TXN1 EDP_AUXP EDP_CPU_AUX <19>
B54
C49 DDI2_TXP1 D20 EDP_COMP 2 1
B50 DDI2_TXN2 EDP_RCOMP A43 EDP_DISP_UTIL 1 2 24.9_0402_1%~D RC71
DDI2_TXP2 EDP_DISP_UTIL EDP_BIA_PWM <10,19>
A53
B53 DDI2_TXN3 @
DDI2_TXP3 RC72
CAD Note:Trace width=20 mils ,Spacing=25mil,
0_0402_5% Max length=100 mils.
1 OF 19 Rev1p2
+1.05VS
+3VS
+1.05VS +1.05VS
0.1U_0402_10V7K
0.1U_0402_10V7K
CC13
2 1 1 1
UC4 @ JXDP1
CC14
XDP@
CC15
XDP@
0.1U_0402_10V7K 1 2
14 XDP_PREQ# 3 GND0 GND1 4 CFG17
VCC 2 2 5 OBSFN_A0 OBSFN_C0 6 CFG17 <16>
XDP_PRDY# CFG16
PCH_JTAG_TDO 1 2 TDO_XDP 2 3 XDP_TDO 7 OBSFN_A1 OBSFN_C1 8 CFG16 <16>
C <8> PCH_JTAG_TDO 1A 1B 9 GND2 GND3 10 C
RC43 0_0402_5% CFG0 CFG8
<16> CFG0 OBSDATA_A0 OBSDATA_C0 CFG8 <16>
CFG1 11 12 CFG9
RUNPWROK 1 <16> CFG1 13 OBSDATA_A1 OBSDATA_C1 14 CFG9 <16>
1OE CFG2 15 GND4 GND5 16 CFG10
1 2 TDI_XDP 1 2 TDI_XDP_R 5 6 XDP_TDI <16> CFG2 CFG3 17 OBSDATA_A2 OBSDATA_C2 18 CFG11 CFG10 <16>
<8> PCH_JTAG_TDI 2A 2B <16> CFG3 19 OBSDATA_A3 OBSDATA_C3 20 CFG11 <16>
RC44 0_0402_5% RC45 0_0402_5% Place near JXDP1
XDP_OBS0_R 21 GND6 GND7 22 CFG19
RUNPWROK 4 XDP_OBS1_R 23 OBSFN_B0 OBSFN_D0 24 CFG18 CFG19 <16>
2OE OBSFN_B1 OBSFN_D1 CFG18 <16>
25 26
1 2 TMS_XDP 9 8 XDP_TMS CFG4 27 GND8 GND9 28 CFG12
<8> PCH_JTAG_TMS 3A 3B <16> CFG4 29 OBSDATA_B0 OBSDATA_D0 30 CFG12 <16>
RC46 0_0402_5% CFG5 CFG13
<16> CFG5 OBSDATA_B1 OBSDATA_D1 CFG13 <16>
31 32
RUNPWROK 10 CFG6 33 GND10 GND11 34 CFG14
3OE <16> CFG6 35 OBSDATA_B2 OBSDATA_D2 36 CFG14 <16>
CFG7 CFG15
TRST#_XDP 12 11 XDP_TRST# <16> CFG7 37 OBSDATA_B3 OBSDATA_D3 38 CFG15 <16>
4A 4B H_CPUPWRGD RC48 1 XDP@ 2 1K_0402_5% H_VCCST_PWRGD_XDP 39 GND12 GND13 40 CLK_XDP RC139 1 XDP@ 2 0_0402_5%
PWRGOOD/HOOK0 ITPCLK/HOOK4 CLK_CPU_ITP <9>
RC49 1 XDP@ 2 0_0402_5% CFD_PWRBTN#_XDP 41 42 CLK_XDP# RC140 1 XDP@ 2 0_0402_5%
<10,30> PBTN_OUT# HOOK1 ITPCLK#/HOOK5 CLK_CPU_ITP# <9>
RUNPWROK 13 7 43 44
<30> RUNPWROK 4OE GND 1 XDP@ 2 0_0402_5% VCC_OBS_AB VCC_OBS_CD
RC50 CPU_PWR_DEBUG#_R 45 46 XDP_RST#_R 2 1 PLT_RST#
<13> CPU_PWR_DEBUG# HOOK2 RESET#/HOOK6 PLT_RST# <10,21,26,30,48>
15 SYS_PWROK RC52 1 XDP@ 2 0_0402_5% SYS_PWROK_XDP 47 48 XDP_DBRESET# 2 1
GND PAD <10,30> SYS_PWROK HOOK3 DBR#/HOOK7 +3VS
49 50 RC51
1 8 DDR_XDP_SMBDAT_R1 51 GND14 GND15 52 TDO_XDP 1K_0402_5% RC362
<17,18,19,26,27,9> DDR_XDP_WLAN_TP_SMBDAT 2 7 DDR_XDP_SMBCLK_R1 53 SDA TD0 54 TRST#_XDP
74CBTLV3126BQ_DHVQFN14_2P5X3 XDP@ 1K_0402_1%
<17,18,19,26,27,9> DDR_XDP_WLAN_TP_SMBCLK 3 6 55 SCL TRST# 56 1 2
TDI_XDP
PCH_JTAG_TCK 4 5 XDP_TCLK 57 TCK1 TDI 58 TMS_XDP
59 TCK0 TMS 60 CFG3_R 1 2 CFG3 CC17
RP46 GND16 GND17 RC56 1K_0402_5% 0.1U_0402_10V7K
0_8P4R_5% SAMTE_BSH-030-01-L-D-A XDP@
reference Shark Bay ULT Validation Customer Debug Port XDP@
CONN@
Implementation Requirement Rev 1.0
+3VALW_PCH
+1.05VS
2
1 2 H_CATERR#
@ RC58 49.9_0402_1% PCH_JTAG_RST# 2 1 XDP_TRST# @
1 2 H_PROCHOT# 0_0402_5% RC57 RC64
RC60 62_0402_5% 1K_0402_5% XDP_DBRESET# 1 2 SYS_RESET#
2 1 SYS_RESET# <10>
XDP_TCLK
1
<8> PCH_JTAG_JTAGX
0_0402_5% RC59 RC26
SYS_PWROK_XDP 0_0402_5%
2 1 TDO_XDP
B 0_0402_5% XDP@ RC62 B
1
XDP@
PCH_JTAG_TDO 2 1 TDI_XDP_R CC16
0_0402_5% XDP@ RC63 0.1U_0402_10V7K
2
PCH_JTAG_TCK 2 1 XDP_TCLK
<8> PCH_JTAG_TCK Place near JXDP1.47
0_0402_5% XDP@ RC65
H_CPUPWRGD
HASWELL_MCP_E
UC1B
1
CAD Note:
Trace width=12~15 mil, Spcing=20 mils
Max trace length= 500 mil
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
MCP(1,2/19) eDP,XDP,MISC
Size Docum ent Num ber Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9981P
Date: Saturday, March 09, 2013 Sheet 6 of 55
5 4 3 2 1
5 4 3 2 1
HASWELL_MCP_E HASWELL_MCP_E
D UC1C UC1D D
<18> DDR_B_D[0..63]
<17> DDR_A_D[0..63]
DDR_A_D0 AH63 AU37 M_CLK_DDR#0
SA_DQ0 SA_CLK#0 M_CLK_DDR#0 <17>
DDR_A_D1 AH62 AV37 M_CLK_DDR0 DDR_B_D0 AY31 AM38 M_CLK_DDR#2
SA_DQ1 SA_CLK0 M_CLK_DDR0 <17> SB_DQ0 SB_CK#0 M_CLK_DDR#2 <18>
DDR_A_D2 AK63 AW36 M_CLK_DDR#1 DDR_B_D1 AW31 AN38 M_CLK_DDR2
SA_DQ2 SA_CLK#1 M_CLK_DDR#1 <17> SB_DQ1 SB_CK0 M_CLK_DDR2 <18>
DDR_A_D3 AK62 AY36 M_CLK_DDR1 DDR_B_D2 AY29 AK38 M_CLK_DDR#3
SA_DQ3 SA_CLK1 M_CLK_DDR1 <17> SB_DQ2 SB_CK#1 M_CLK_DDR#3 <18>
DDR_A_D4 AH61 DDR_B_D3 AW29 AL38 M_CLK_DDR3
SA_DQ4 SB_DQ3 SB_CK1 M_CLK_DDR3 <18>
DDR_A_D5 AH60 AU43 DDR_CKE0_DIMMA DDR_B_D4 AV31
SA_DQ5 SA_CKE0 DDR_CKE0_DIMMA <17> SB_DQ4
DDR_A_D6 AK61 AW43 DDR_CKE1_DIMMA DDR_B_D5 AU31 AY49 DDR_CKE2_DIMMB
SA_DQ6 SA_CKE1 DDR_CKE1_DIMMA <17> SB_DQ5 SB_CKE0 DDR_CKE2_DIMMB <18>
DDR_A_D7 AK60 AY42 DDR_B_D6 AV29 AU50 DDR_CKE3_DIMMB
SA_DQ7 SA_CKE2 SB_DQ6 SB_CKE1 DDR_CKE3_DIMMB <18>
DDR_A_D8 AM63 AY43 DDR_B_D7 AU29 AW49
DDR_A_D9 AM62 SA_DQ8 SA_CKE3 DDR_B_D8 AY27 SB_DQ7 SB_CKE2 AV50
DDR_A_D10 AP63 SA_DQ9 AP33 DDR_CS0_DIMMA# DDR_B_D9 AW27 SB_DQ8 SB_CKE3
SA_DQ10 SA_CS#0 DDR_CS0_DIMMA# <17> SB_DQ9
DDR_A_D11 AP62 AR32 DDR_CS1_DIMMA# DDR_B_D10 AY25 AM32 DDR_CS2_DIMMB#
SA_DQ11 SA_CS#1 DDR_CS1_DIMMA# <17> SB_DQ10 SB_CS#0 DDR_CS2_DIMMB# <18>
DDR_A_D12 AM61 DDR_B_D11 AW25 AK32 DDR_CS3_DIMMB#
SA_DQ12 SB_DQ11 SB_CS#1 DDR_CS3_DIMMB# <18>
DDR_A_D13 AM60 AP32 DDR_B_D12 AV27
DDR_A_D14 AP61 SA_DQ13 SA_ODT0 DDR_B_D13 AU27 SB_DQ12 AL32
DDR_A_D15 AP60 SA_DQ14 AY34 DDR_A_RAS# DDR_B_D14 AV25 SB_DQ13 SB_ODT0
SA_DQ15 SA_RAS DDR_A_RAS# <17> SB_DQ14
DDR_A_D16 AP58 AW34 DDR_A_WE# DDR_B_D15 AU25 AM35 DDR_B_RAS#
SA_DQ16 SA_WE DDR_A_WE# <17> SB_DQ15 SB_RAS DDR_B_RAS# <18>
DDR_A_D17 AR58 AU34 DDR_A_CAS# DDR_B_D16 AM29 AK35 DDR_B_WE#
SA_DQ17 SA_CAS DDR_A_CAS# <17> SB_DQ16 SB_WE DDR_B_WE# <18>
DDR_A_D18 AM57 DDR_B_D17 AK29 AM33 DDR_B_CAS#
SA_DQ18 SB_DQ17 SB_CAS DDR_B_CAS# <18>
DDR_A_D19 AK57 AU35 DDR_A_BS0 DDR_B_D18 AL28
SA_DQ19 SA_BA0 DDR_A_BS0 <17> SB_DQ18
DDR_A_D20 AL58 AV35 DDR_A_BS1 DDR_B_D19 AK28 AL35 DDR_B_BS0
SA_DQ20 SA_BA1 DDR_A_BS1 <17> SB_DQ19 SB_BA0 DDR_B_BS0 <18>
DDR_A_D21 AK58 AY41 DDR_A_BS2 DDR_B_D20 AR29 AM36 DDR_B_BS1
SA_DQ21 SA_BA2 DDR_A_BS2 <17> SB_DQ20 SB_BA1 DDR_B_BS1 <18>
DDR_A_D22 AR57 DDR_B_D21 AN29 AU49 DDR_B_BS2
SA_DQ22 DDR_A_MA[0..15] <17> SB_DQ21 SB_BA2 DDR_B_BS2 <18>
DDR_A_D23 AN57 AU36 DDR_A_MA0 DDR_B_D22 AR28
SA_DQ23 SA_MA0 SB_DQ22 DDR_B_MA[0..15] <18>
DDR_A_D24 AP55 AY37 DDR_A_MA1 DDR_B_D23 AP28 AP40 DDR_B_MA0
DDR_A_D25 AR55 SA_DQ24 SA_MA1 AR38 DDR_A_MA2 DDR_B_D24 AN26 SB_DQ23 SB_MA0 AR40 DDR_B_MA1
DDR_A_D26 AM54 SA_DQ25 SA_MA2 AP36 DDR_A_MA3 DDR_B_D25 AR26 SB_DQ24 SB_MA1 AP42 DDR_B_MA2
DDR_A_D27 AK54 SA_DQ26 SA_MA3 AU39 DDR_A_MA4 DDR_B_D26 AR25 SB_DQ25 SB_MA2 AR42 DDR_B_MA3
DDR_A_D28 AL55 SA_DQ27 SA_MA4 AR36 DDR_A_MA5 DDR_B_D27 AP25 SB_DQ26 SB_MA3 AR45 DDR_B_MA4
DDR_A_D29 AK55 SA_DQ28 SA_MA5 AV40 DDR_A_MA6 DDR_B_D28 AK26 SB_DQ27 SB_MA4 AP45 DDR_B_MA5
DDR_A_D30 AR54 SA_DQ29 SA_MA6 AW39 DDR_A_MA7 DDR_B_D29 AM26 SB_DQ28 SB_MA5 AW46 DDR_B_MA6
DDR_A_D31 AN54 SA_DQ30 SA_MA7 AY39 DDR_A_MA8 DDR_B_D30 AK25 SB_DQ29 SB_MA6 AY46 DDR_B_MA7
DDR_A_D32 AY58 SA_DQ31 SA_MA8 AU40 DDR_A_MA9 DDR_B_D31 AL25 SB_DQ30 SB_MA7 AY47 DDR_B_MA8
DDR_A_D33 AW58 SA_DQ32 SA_MA9 AP35 DDR_A_MA10 DDR_B_D32 AY23 SB_DQ31 SB_MA8 AU46 DDR_B_MA9
DDR_A_D34 AY56 SA_DQ33 SA_MA10 AW41 DDR_A_MA11 DDR_B_D33 AW23 SB_DQ32 SB_MA9 AK36 DDR_B_MA10
C C
DDR_A_D35 AW56 SA_DQ34 DDR CHANNEL A SA_MA11 AU41 DDR_A_MA12 DDR_B_D34 AY21 SB_DQ33 DDR CHANNEL B SB_MA10 AV47 DDR_B_MA11
DDR_A_D36 AV58 SA_DQ35 SA_MA12 AR35 DDR_A_MA13 DDR_B_D35 AW21 SB_DQ34 SB_MA11 AU47 DDR_B_MA12
DDR_A_D37 AU58 SA_DQ36 SA_MA13 AV42 DDR_A_MA14 DDR_B_D36 AV23 SB_DQ35 SB_MA12 AK33 DDR_B_MA13
DDR_A_D38 AV56 SA_DQ37 SA_MA14 AU42 DDR_A_MA15 DDR_B_D37 AU23 SB_DQ36 SB_MA13 AR46 DDR_B_MA14
DDR_A_D39 AU56 SA_DQ38 SA_MA15 DDR_B_D38 AV21 SB_DQ37 SB_MA14 AP46 DDR_B_MA15
SA_DQ39 DDR_A_DQS#[0..7] <17> SB_DQ38 SB_MA15
DDR_A_D40 AY54 AJ61 DDR_A_DQS#0 DDR_B_D39 AU21
SA_DQ40 SA_DQSN0 SB_DQ39 DDR_B_DQS#[0..7] <18>
DDR_A_D41 AW54 AN62 DDR_A_DQS#1 DDR_B_D40 AY19 AW30 DDR_B_DQS#0
DDR_A_D42 AY52 SA_DQ41 SA_DQSN1 AM58 DDR_A_DQS#2 DDR_B_D41 AW19 SB_DQ40 SB_DQSN0 AV26 DDR_B_DQS#1
DDR_A_D43 AW52 SA_DQ42 SA_DQSN2 AM55 DDR_A_DQS#3 DDR_B_D42 AY17 SB_DQ41 SB_DQSN1 AN28 DDR_B_DQS#2
DDR_A_D44 AV54 SA_DQ43 SA_DQSN3 AV57 DDR_A_DQS#4 DDR_B_D43 AW17 SB_DQ42 SB_DQSN2 AN25 DDR_B_DQS#3
DDR_A_D45 AU54 SA_DQ44 SA_DQSN4 AV53 DDR_A_DQS#5 DDR_B_D44 AV19 SB_DQ43 SB_DQSN3 AW22 DDR_B_DQS#4
DDR_A_D46 AV52 SA_DQ45 SA_DQSN5 AL43 DDR_A_DQS#6 DDR_B_D45 AU19 SB_DQ44 SB_DQSN4 AV18 DDR_B_DQS#5
DDR_A_D47 AU52 SA_DQ46 SA_DQSN6 AL48 DDR_A_DQS#7 DDR_B_D46 AV17 SB_DQ45 SB_DQSN5 AN21 DDR_B_DQS#6
DDR_A_D48 AK40 SA_DQ47 SA_DQSN7 DDR_B_D47 AU17 SB_DQ46 SB_DQSN6 AN18 DDR_B_DQS#7
SA_DQ48 DDR_A_DQS[0..7] <17> SB_DQ47 SB_DQSN7
DDR_A_D49 AK42 AJ62 DDR_A_DQS0 DDR_B_D48 AR21
SA_DQ49 SA_DQSP0 SB_DQ48 DDR_B_DQS[0..7] <18>
DDR_A_D50 AM43 AN61 DDR_A_DQS1 DDR_B_D49 AR22 AV30 DDR_B_DQS0
DDR_A_D51 AM45 SA_DQ50 SA_DQSP1 AN58 DDR_A_DQS2 DDR_B_D50 AL21 SB_DQ49 SB_DQSP0 AW26 DDR_B_DQS1
DDR_A_D52 AK45 SA_DQ51 SA_DQSP2 AN55 DDR_A_DQS3 DDR_B_D51 AM22 SB_DQ50 SB_DQSP1 AM28 DDR_B_DQS2
DDR_A_D53 AK43 SA_DQ52 SA_DQSP3 AW57 DDR_A_DQS4 DDR_B_D52 AN22 SB_DQ51 SB_DQSP2 AM25 DDR_B_DQS3
DDR_A_D54 AM40 SA_DQ53 SA_DQSP4 AW53 DDR_A_DQS5 DDR_B_D53 AP21 SB_DQ52 SB_DQSP3 AV22 DDR_B_DQS4
DDR_A_D55 AM42 SA_DQ54 SA_DQSP5 AL42 DDR_A_DQS6 DDR_B_D54 AK21 SB_DQ53 SB_DQSP4 AW18 DDR_B_DQS5
DDR_A_D56 AM46 SA_DQ55 SA_DQSP6 AL49 DDR_A_DQS7 DDR_B_D55 AK22 SB_DQ54 SB_DQSP5 AM21 DDR_B_DQS6
DDR_A_D57 AK46 SA_DQ56 SA_DQSP7 DDR_B_D56 AN20 SB_DQ55 SB_DQSP6 AM18 DDR_B_DQS7
DDR_A_D58 AM49 SA_DQ57 AP49 DDR_B_D57 AR20 SB_DQ56 SB_DQSP7
SA_DQ58 SM_VREF_CA +SM_VREF_CA SB_DQ57
DDR_A_D59 AK49 AR51 +SM_VREF_DQ0 DDR_B_D58 AK18
DDR_A_D60 AM48 SA_DQ59 SM_VREF_DQ0 AP51 DDR_B_D59 AL18 SB_DQ58
SA_DQ60 SM_VREF_DQ1 +SM_VREF_DQ1 SB_DQ59
DDR_A_D61 AK48 DDR_B_D60 AK20
DDR_A_D62 AM51 SA_DQ61 DDR_B_D61 AM20 SB_DQ60
DDR_A_D63 AK51 SA_DQ62 DDR_B_D62 AR18 SB_DQ61
SA_DQ63 DDR_B_D63 AP18 SB_DQ62
SB_DQ63
B B
3 OF 19 Rev1p2 4 OF 19 Rev1p2
1
RC14 RC15 RC16
1.82K_0402_1% 1.82K_0402_1% 1.82K_0402_1%
+SM_VREF_CA_DIMM +SM_VREF_CA +SM_VREF_DQ1_DIMM2 +SM_VREF_DQ1 +SM_VREF_DQ0_DIMM1 +SM_VREF_DQ0
2
2
1 2 1 2 1 2
1 1
RC17 1 RC18 RC19
2.2_0402_1% 2.2_0402_1% CC9 2.2_0402_1% CC10
1
1
CC8 0.022U_0402_16V7K 0.022U_0402_16V7K
RC20 0.022U_0402_16V7K RC21 2 RC22 2
1.82K_0402_1% 2 1.82K_0402_1% change 22nF 1.82K_0402_1% change 22nF
1
1
change 22nF
1
RC24 RC25
2
2
RC23 24.9_0402_1%~D 24.9_0402_1%~D
24.9_0402_1%~D
2
2
2
+RTCVCC
1
RTC Battery RC1
330K_0402_1%
+RTCBATT
2
D PCH_INTVRMEN D
1
+CHGRTC RC10
@
1K_0402_5%
RC2
330K_0402_1% +3VS
W=20mils JP12
1
2
W=20mils 2 1 1 2 PCH_AZ_SDOUT
+CHGRTC +3VLP
3
2
2 1 @ RC3 1K_0402_5%
DC1 JUMP_43X39
BAT54CW_SOT323-3
INTVRMEN - INTEGRATED SUS 1.05V VRM FLASH DESCRIPTOR SECURITY OVERRIDE
ENABLE LOW = DESABLED (DEFAULT)
1
CC1
1 2 PCH_RTCX1
15P_0402_50V8J
1
XTAL@
XTAL@ XTAL@
RC4
HASWELL_MCP_E
YC1 10M_0402_5% UC1E
2
32.768KHZ_12.5PF_Q13FC1350000
2
CC2 XTAL@
15P_0402_50V8J AW5
1 2 PCH_RTCX2 AY5 RTCX1
1 2 INTRUDER# AU6 RTCX2 J5
INTRUDER RTC SATA_RN0/PERN6_L3 SATA_PRX_DTX_N0_C <32>
RC7 1M_0402_5% PCH_INTVRMEN AV7 H5
INTVRMEN SATA_RP0/PERP6_L3 SATA_PRX_DTX_P0_C <32>
C +RTCVCC 1 2 SRTCRST# AV6 B15 SATA HDD C
SRTCRST SATA_TN0/PETN6_L3 SATA_PTX_DRX_N0_C <32>
RC5 1 2 20K_0402_5% PCH_RTCRST# AU7 A15
RTCRST SATA_TP0/PETP6_L3 SATA_PTX_DRX_P0_C <32>
RC6 20K_0402_5%
J8
SATA_RN1/PERN6_L2 SATA_PRX_DTX_N1_C <32>
H8
SATA_RP1/PERP6_L2 SATA_PRX_DTX_P1_C <32>
A17 SATA ODD
SATA_TN1/PETN6_L2 SATA_PTX_DRX_N1_C <32>
B17
SATA_TP1/PETP6_L2 SATA_PTX_DRX_P1_C <32>
1 2 1 2 PCH_AZ_BITCLK AW8 J6
1 2 1 2 PCH_AZ_SYNC AV11 HDA_BCLK/I2S0_SCLK SATA_RN2/PERN6_L1 H6
HDA_SYNC/I2S0_SFRM SATA_RP2/PERP6_L1 PCH Rx side need use strap pin to update PCIE +/-
PCH_AZ_RST# AU8 B14
PCH_AZ_CODEC_SDIN0 AY10 HDA_RST/I2S_MCLK SATA_TN2/PETN6_L1 C15 +3VS
<22> PCH_AZ_CODEC_SDIN0 HDA_SDI0/I2S0_RXD SATA_TP2/PETP6_L1
@ @ AU12 AUDIO SATA
ME1 SHORT PADS~D CMOS1 SHORT PADS~D 1 2 PCH_AZ_SDOUT AU11 HDA_SDI1/I2S1_RXD F5
<30> ME_EN
2
1 2 1 2 RC8 1K_0402_5% AW10 HDA_SDO/I2S0_TXD SATA_RN3/PERN6_L0 E5
CC3 1U_0402_6.3V6K CC4 1U_0402_6.3V6K AV10 HDA_DOCK_EN/I2S1_TXD SATA_RP3/PERP6_L0 C17
AY8 HDA_DOCK_RST/I2S1_SFRM SATA_TN3/PETN6_L0 D17 RC107
I2S1_SCLK SATA_TP3/PETP6_L0 10K_0402_5%
1
V1 EC_SMI#
SATA0GP/GPIO34 EC_SMI# <30>
U1 PCH_GPIO35
CMOS place near DIMM SATA1GP/GPIO35 V6 ODD_DETECT# +1.05VS_ASATA3PLL
SATA2GP/GPIO36 ODD_DETECT# <32>
AC1 PCH_GPIO37
PCH_JTAG_RST# AU62 SATA3GP/GPIO37
<6> PCH_JTAG_RST# PCH_TRST
PCH_JTAG_TCK AE62 A12 SATA_IREF RC126 1 2 0_0603_5%
<6> PCH_JTAG_TCK PCH_TCK SATA_IREF
PCH_JTAG_TDI AD61 L11
<6> PCH_JTAG_TDI PCH_TDI RSVD
PCH_JTAG_TDO AE61 K10
<6> PCH_JTAG_TDO PCH_TDO JTAG RSVD
PCH_JTAG_TMS AD62 C12 SATA_RCOMP RC131 1 2 3.01K_0402_1%
<6> PCH_JTAG_TMS
AL11 PCH_TMS SATA_RCOMP U3 SATA_ACT#
SATA Impedance Compensation
RSVD SATALED SATA_ACT# <26>
AC4 within 500 mils
PCH_JTAG_JTAGX AE63 RSVD
<6> PCH_JTAG_JTAGX JTAGX CAD note:
AV2
RSVD Place the resistor within 500 mils of the PCH. Avoid
routing next to clock pins.
reference FFRD sch 0.5
5 OF 19 Rev1p2
B B
+1.05VS
+3VS
@
RC130
2 1 PCH_JTAG_JTAGX
1K_0402_1% HDA for Codec
@ 2 1 PCH_JTAG_TCK
CMOS_CLR1 CMOS setting ODD_DETECT# 1 8
RC135 51_0402_1% PCH_GPIO35 2 7
Shunt Clear CMOS EMI@ R2356 1 2 33_0402_5% PCH_AZ_SDOUT PCH_GPIO37 3 6
<22> PCH_AZ_CODEC_SDOUT
4 5
Open Keep CMOS EMI@ R2357 1 2 33_0402_5% PCH_AZ_SYNC
<22> PCH_AZ_CODEC_SYNC
RP37
ME_CLR1 TPM setting EMI@ R2358 1 2 33_0402_5% PCH_AZ_RST# 10K_8P4R_5%
<22> PCH_AZ_CODEC_RST#
RP48
51_8P4R_5%
EMI depop location
A A
+3VALW_PCH
MEM Bus : DDR/XDP/WLAN/TP
D +3VS D
1
R2329 R2330 +3VS
10K_0402_5% 10K_0402_5%
1
HASWELL_MCP_E
UC1G R2331 R2332
2
10K_0402_5% 10K_0402_5%
LPC_LAD0 AU14 AN2 PCH_SMB_ALERT#
<30> LPC_LAD0
2
LPC_LAD1 AW12 LAD0 SMBALERT/GPIO11 AP2 MEM_SMBCLK
<30> LPC_LAD1 LAD1 SMBCLK
2
AY12 LPC AH1
G
LPC_LAD2 MEM_SMBDATA
<30> LPC_LAD2 LAD2 SMBDATA
LPC_LAD3 AW11 AL2 MEM_SMBCLK 6 1
<30> LPC_LAD3 LAD3 SML0ALERT/GPIO60 DDR_XDP_WLAN_TP_SMBCLK <17,18,19,26,27,6>
S
LPC_LFRAME# AV12 SMBUS AN1 SML0CLK
<30> LPC_LFRAME# LFRAME SML0CLK AK1 SML0DATA QC1B
SML0DATA
5
AU4 PCH_HOT# DMN66D0LDW-7_SOT363-6
EMI EMI@ SML1ALERT/PCHHOT/GPIO73 AU3 SML1_SMBCLK
PCH_HOT# <30>
G
R2333 SML1CLK/GPIO75 AH3 SML1_SMBDATA MEM_SMBDATA 3 4
SML1DATA/GPIO74 DDR_XDP_WLAN_TP_SMBDAT <17,18,19,26,27,6>
S
PCH_SPI_CLK_R 1 1 2 15_0402_1% PCH_SPI_CLK AA3
PCH_SPI_CS0# Y7 SPI_CLK AF2 @ T97 QC1A
@EMI@ Y4 SPI_CS0 CL_CLK AD2 @ T98 DMN66D0LDW-7_SOT363-6
C2326 RP39 AC2 SPI_CS1 SPI C-LINK CL_DATA AF4 @ T99
68P_0402_50V8J 2 PCH_SPI_MOSI_1 1 8 PCH_SPI_MOSI AA2 SPI_CS2 CL_RST
PCH_SPI_MISO_1 2 7 PCH_SPI_MISO AA4 SPI_MOSI
PCH_SPI_WP1# 3 6 PCH_SPI_WP# Y6 SPI_MISO
PCH_SPI_HOLD1# 4 5 PCH_SPI_HOLD# AF1 SPI_IO2
SPI_IO3
15_8P4R_5%
+3VS
+3VALW_PCH
+3VS
+3VALW_PCH
2
C2327 QH1B
0.1U_0402_10V7K
G
SPI ROM ( 8MByte ) 1 2
1
RP40
8
SML1_SMBCLK 1 6 EC_SMB_CK2 <19,30,49>
D
MEM_SMBCLK
5
U2302 MEM_SMBDATA 2 7 DMN66D0LDW-7_SOT363-6
PCH_SPI_CS0# 1 8 SML1_SMBCLK 3 6
G
PCH_SPI_MISO_1 2 CS# VCC 7 PCH_SPI_HOLD1# SML1_SMBDATA 4 5 SML1_SMBDATA 4 3
DO(IO1) HOLD#(IO3) EC_SMB_DA2 <19,30,49>
3 6
D
PCH_SPI_WP1# PCH_SPI_CLK_R
4 WP#(IO2) CLK 5 PCH_SPI_MOSI_1 2.2K_0804_8P4R_5% QH1A
GND DI(IO0) DMN66D0LDW-7_SOT363-6
64M EN25Q64-104HIP SOP 8P
RP49
SML0CLK 1 8
SML0DATA 2 7
3 6
PN : SA000046400 ,64M,EN25Q64-104HIP 4 5
1K_0804_8P4R_5%
EC_SPI_MOSI_1
<30> EC_SPI_MOSI_1
EC_SPI_MISO_1
PAD~D T183 @ For GCLK
<30> EC_SPI_MISO_1 PAD~D T184 @
EC_SPI_CLK_R
<30> EC_SPI_CLK_R PAD~D T185 @
EC_SPI_CS0# XTAL24_IN
<30> EC_SPI_CS0# PAD~D T186 @ <29> XTAL24_IN
1M_0402_5%
XTAL@
2
PCH_SPI_CLK_R
3
4
HASWELL_MCP_E
RC12
UC1F
PCH_SPI_CS0# YC2
near U2302 24MHZ_12PF_X3G024000DC1H
XTAL@ XTAL@
1
2
CC7
C43 A25 XTAL24_IN 15P_0402_50V8J
C42 CLKOUT_PCIE_N0 XTAL24_IN B25 XTAL24_OUT 2 1
U2 CLKOUT_PCIE_P0 XTAL24_OUT
PCIECLKRQ0/GPIO18 K21 RC13 XTAL@
B41 RSVD M21 3.01K_0402_1%
A41 CLKOUT_PCIE_N1 RSVD C26 CLK_BIASREF 1 2
CLKOUT_PCIE_P1 DIFFCLK_BIASREF +1.05VS_AXCK_LCPLL
Y5 RP41 10K_8P4R_5%
PCIECLKRQ1/GPIO19 C35 1 8
CLK_PCIE_LAN# C41 CLOCK TESTLOW_C35 C34 2 7
<21> CLK_PCIE_LAN# CLKOUT_PCIE_N2 TESTLOW_C34
10/100 LAN -------> CLK_PCIE_LAN B42 AK8 3 6 EMI@
<21> CLK_PCIE_LAN CLKOUT_PCIE_P2 SIGNALS TESTLOW_AK8
AD1 AL8 4 5 R2336
<21> LAN_CLKREQ# PCIECLKRQ2/GPIO20 TESTLOW_AL8 22_0402_5%
CLK_PCIE_WLAN# B38 AN15 CLKOUT_LPC0 2 1
<26> CLK_PCIE_WLAN# CLKOUT_PCIE_N3 CLKOUT_LPC_0 CLK_PCI_LPC <30>
WLAN(Mini Card)---> CLK_PCIE_WLAN C37 AP15
<26> CLK_PCIE_WLAN CLKOUT_PCIE_P3 CLKOUT_LPC_1
N1
<26> WLAN_CLKREQ# PCIECLKRQ3/GPIO21 B35
CLKOUT_ITPXDP_N CLK_CPU_ITP# <6>
CLK_PEG_VGA# A39 A35
<48> CLK_PEG_VGA# CLKOUT_PCIE_N4 CLKOUT_ITPXDP_P CLK_CPU_ITP <6>
dGPU---> CLK_PEG_VGA B39
<48> CLK_PEG_VGA CLKOUT_PCIE_P4
U5
<49> PEG_CLKREQ# PCIECLKRQ4/GPIO22
B37
A37 CLKOUT_PCIE_N5
T2 CLKOUT_PCIE_P5
PCIECLKRQ5/GPIO23
6 OF 19 Rev1p2
+3VS
RP42
A 1 8 A
2 7
3 6
4 5
10K_8P4R_5%
+3VS
+3VALW_PCH
D @ CC11 D
1 2 ME_SUS_PWR_ACK 1 2
RC27 10K_0402_5%
1 2 SUSACK# 0.1U_0402_10V7K
@ RC28 10K_0402_5%
1 2 SUS_STAT#/LPCPD#
5
@ RC29 10K_0402_5%
VCC
PCH_PLTRST# 1
IN1 4 PLT_RST#
OUT PLT_RST# <21,26,30,48,6>
2
GND
+3VALW_PCH IN2
1
UC3
MC74VHC1G08DFT2G_SC70-5 R159
3
1 2 PCH_BATLOW# 100K_0402_5%
RC31 8.2K_0402_5%
1 2 AC_PRESENT PCH_DPWROK 1 2 PCH_RSMRST#_R
2
RC32 10K_0402_5% RC33 0_0402_5%
1 2 PCIE_WAKE#_R
RC34 10K_0402_5% ME_SUS_PWR_ACK_R 1 2 SUSACK#
RC35 @ 0_0402_5%
+3VS
HASWELL_MCP_E
UC1I CPU_DPB_CTRLCLK 1 8
+3VS CPU_DPB_CTRLDAT 2 7
@ CPU_DPC_CTRLCLK 3 6
RC81 CPU_DPC_CTRLDAT 4 5
0_0402_1%
1 2 DGPU_PWROK EDP_BIA_PWM 2 1 EDP_BKLCTL B8 B9 CPU_DPB_CTRLCLK RP52
<19,6> EDP_BIA_PWM EDP_BKLCTL DDPB_CTRLCLK CPU_DPB_CTRLCLK <20>
RC73 10K_0402_5% PANEL_BKLEN A9 C9 CPU_DPB_CTRLDAT 2.2K_8P4R_5%
<30> PANEL_BKLEN EDP_BKLEN eDP SIDEBAND DDPB_CTRLDATA CPU_DPB_CTRLDAT <20>
1 2 TOUCHPAD_INTR# ENVDD_PCH C6 D9 CPU_DPC_CTRLCLK
<19,30> ENVDD_PCH EDP_VDDEN DDPC_CTRLCLK
RC74 10K_0402_5% D11 CPU_DPC_CTRLDAT
1 @ 2 EDP_BIA_PWM
DDPC_CTRLDATA CPU_DPB_AUX# 1 8
B B
RC75 10K_0402_5% CPU_DPC_AUX# 2 7
1 2 TOUCH_RST_N_GYRO_INT1 DGPU_PWROK U6 CPU_DPB_AUX 3 6
<30,44> DGPU_PWROK PIRQA/GPIO77
RC76 10K_0402_5% PXS_PWREN P4 C5 CPU_DPB_AUX# CPU_DPC_AUX 4 5
<11,39,43,44,50> PXS_PWREN PIRQB/GPIO78 DISPLAY DDPB_AUXN
1 2 DGPU_HOLD_RST# DGPU_HOLD_RST# N4 B6 CPU_DPC_AUX#
<48> DGPU_HOLD_RST# PIRQC/GPIO79 DDPC_AUXN
RC77 10K_0402_5% N2 B5 CPU_DPB_AUX RP51
T117 @ AD4 PIRQD/GPIO80 DDPB_AUXP A6 CPU_DPC_AUX 100K_8P4R_5%
PME GPIO DDPC_AUXP
TOUCHPAD_INTR# U7
1 2 ENVDD_PCH TOUCH_RST_N_GYRO_INT1 L1 GPIO55
@ RC87 100K_0402_5% L3 GPIO52 C8 DPB_HPD
GPIO54 DDPB_HPD DPB_HPD <20>
2 1 CODEC_IRQ R5 A8 DPC_HPD
@ RC88 1K_0402_1% CODEC_IRQ L4 GPIO51 DDPC_HPD D6 CPU_EDP_HPD#
GPIO53 EDP_HPD
9 OF 19 Rev1p2 DPC_HPD 2 1
1
RC84 RC78 @
100K_0402_5%
10K_0402_5%
2
CPU_EDP_HPD#
CPU_EDP_HPD# 1 2
1
RC89
100K_0402_5% D
2 QC3 @
<19> EDP_CPU_HPD
G 2N7002K_SOT23-3
S
3
symbol OK
A A
RC105
EDP_CPU_HPD 1 2 CPU_EDP_HPD#
D D
+1.05VS
1
HASWELL_MCP_E
UC1J
R2346
1K_0402_5%
2
PCH_AUDIO_EN P1 D60 H_THERMTRIP#
AU2 BMBUSY/GPIO76 THERMTRIP V4 KB_RST#
GPIO8 RCIN/GPIO82 KB_RST# <30>
PCH_GPIO12 AM7 T4 SERIRQ
@ T182 PAD~D LAN_PHY_PWR_CTRL/GPIO12 CPU/ SERIRQ SERIRQ <30>
EC_LID_OUT# AD6 AW15 PCH_OPI_COMP 1 2
<30> EC_LID_OUT# GPIO15 PCH_OPI_RCOMP
ODD_EN# Y1 MISC AF20
<32> ODD_EN# GPIO16 RSVD
ODD_DA# T3 AB21 RC101
<32> ODD_DA# GPIO17 RSVD +3VS +3VS
BT_ON# AD5 49.9_0402_1%
<26> BT_ON# GPIO24
KB_DET# AN5
KB_DET# GPIO27
"KB_DET#" for OAK 17 only HOST_ALERT1_R_N AD7 +3VS
GPIO28
1
AN3
GPIO26 R6 PCH_GPIO83 SUN@ UMA@
GSPI0_CS/GPIO83 PAD~D T177 @
HDD_DET# AG6 L6 PCH_GPIO84 RC112 RC100 SERIRQ 2 1
<32> HDD_DET# GPIO56 GSPI0_CLK/GPIO84 PAD~D T176 @
AP1 N6 PCH_GPIO85 10K_0402_5% 10K_0402_5% 10K_0402_5% RC102
GPIO57 GSPI0_MISO/GPIO85 PAD~D T175 @
+3VS SLATE_MODE_R AL4 L8 BBS_BIT LCD_CBL_DET# 2 1
2
WL_OFF# AT5 GPIO58 GSPI0_MOSI/GPIO86 R7 DGPU_PRSNT# 10K_0402_5% RC106
<26> WL_OFF# GPIO59 GSPI1_CS/GPIO87
PCH_GPIO44 AK4 L5 Project_ID CPPE# 2 1
2 1 DEVSLP0 PCH_GPIO47 AB6 GPIO44 GPIO GSPI1_CLK/GPIO88 N7 PCH_GPIO89 100K_0402_5% RC108
C @ T174 PAD~D PAD~D T178 @ C
GPIO47 GSPI1_MISO/GPIO89
1
RC11 10K_0402_5% PCH_GPIO48 U4 K2 PCH_GPIO90 CPUSB# 2 1
@ T124 PAD~D GPIO48 GSPI_MOSI/GPIO90 PAD~D T179 @ VENUS@ DIS@
PCH_GPIO49 Y3 J1 CPPE# 100K_0402_5% RC111
@ T125 PAD~D GPIO49 UART0_RXD/GPIO91
2 1 SIO_EXT_SCI# TOUCH_PANEL_INTR# P3 K3 CPUSB# RC113 RC99
RC98 100K_0402_5% Y2 GPIO50 UART0_TXD/GPIO92 J2 PCH_GPIO93 10K_0402_5% 10K_0402_5%
HSIOPC/GPIO71 LPIO UART0_RTS/GPIO93 PAD~D T180 @
AT3 G1 PCH_GPIO94 RP53
PAD~D T181 @
2
2 1 HDD_DET# PCH_GPIO14 AH4 GPIO13 UART0_CTS/GPIO94 K4 I2C1_SDA_TCH_PAD 1 8
@ T126 PAD~D GPIO14 UART1_RXD/GPIO0
RC9 100K_0402_5% PCH_GPIO25 AM4 G2 I2C1_SCL_TCH_PAD 2 7
@ T127 PAD~D GPIO25 UART1_TXD/GPIO1
AG5 J3 LCD_CBL_DET# I2C0_SDA 3 6
PCH_GPIO46 AG3 GPIO45 UART1_RST/GPIO2 J4 I2C0_SCL 4 5
GPIO46 UART1_CTS/GPIO3 F2 I2C0_SDA
PCH_GPIO9 AM3 I2C0_SDA/GPIO4 F3 I2C0_SCL 2.2K_0804_8P4R_5%
EC_SCI# AM2 GPIO9 I2C0_SCL/GPIO5 G4 I2C1_SDA_TCH_PAD
<30> EC_SCI# GPIO10 I2C1_SDA/GPIO6
DEVSLP0 P2 F1 I2C1_SCL_TCH_PAD RP43
<32> DEVSLP0 DEVSLP0/GPIO33 I2C1_SCL/GPIO7
C4 E3 KB_RST# 8 1
L2 SDIO_POWER_EN/GPIO70 SDIO_CLK/GPIO64 F4 TOUCH_PANEL_INTR# 7 2
SIO_EXT_SCI# N5 DEVSLP1/GPIO38 SDIO_CMD/GPIO65 D3 PCH_GPIO66 6 3
HDA_SPKR V2 DEVSLP2/GPIO39 SDIO_D0/GPIO66 E4 5 4
<22> HDA_SPKR SPKR/GPIO81 SDIO_D1/GPIO67 C3
SDIO_D2/GPIO68 E2 10K_8P4R_5%
SDIO_D3/GPIO69
+3VALW_PCH 10 OF 19 Rev1p2
2 1 KB_DET#
RC103 10K_0402_5%
2 1 PCH_GPIO44
RC104 10K_0402_5%
2 1 SLATE_MODE_R
RC110 10K_0402_5%
2 1 PCH_AUDIO_EN
RC116 10K_0402_5% +3VS +3VS
1
@
@ RC119
RC118 10K_0402_5%
1K_0402_5% +3VALW_PCH +3VS
B B
2
1
PCH_GPIO66 BBS_BIT
@ @
1
RC120 RC121
1
@ 1K_0402_5% 1K_0402_5%
RC122
2
1K_0402_5% RC123
1K_0402_5% HOST_ALERT1_R_N HDA_SPKR
2
+3VS
2
RC124 RC125
10K_0402_5% 10K_0402_5%
2
PCH_GPIO46 PCH_GPIO9
A A
D D
HASWELL_MCP_E
UC1K
C PCIE_PRX_LANTX_N3 G11 C
<21> PCIE_PRX_LANTX_N3 PERN3
PCIE_PRX_LANTX_P3 F11 G20 USB3RN1_JUSB2
<21> PCIE_PRX_LANTX_P3 PERP3 USB3RN1 USB3RN1_JUSB2 <24>
10/100 LAN H20 USB3RP1_JUSB2
USB3RP1 USB3RP1_JUSB2 <24>
PCIE_PTX_LANRX_N3 CC32 1 2 0.1U_0402_10V7K PCIE_PTX_LANRX_N3_C C29 USB Conn JUSB2
<21> PCIE_PTX_LANRX_N3 PETN3
PCIE_PTX_LANRX_P3 CC40 1 2 0.1U_0402_10V7K PCIE_PTX_LANRX_P3_C B30 PCIe USB C33 USB3TN1_JUSB2
<21> PCIE_PTX_LANRX_P3 PETP3 USB3TN1 USB3TN1_JUSB2 <24>
B34 USB3TP1_JUSB2
USB3TP1 USB3TP1_JUSB2 <24>
PCIE_PRX_WLANTX_N4 F13
<26> PCIE_PRX_WLANTX_N4 PERN4
PCIE_PRX_WLANTX_P4 G13 E18 USB3RN2_JUSB1
<26> PCIE_PRX_WLANTX_P4 PERP4 USB3RN2 USB3RN2_JUSB1 <24>
WLAN (Mini Card) F18 USB3RP2_JUSB1
USB3RP2 USB3RP2_JUSB1 <24>
PCIE_PTX_WLANRX_N4 B29 USB Conn JUSB1
<26> PCIE_PTX_WLANRX_N4 PETN4
PCIE_PTX_WLANRX_P4 A29 B33 USB3TN2_JUSB1
<26> PCIE_PTX_WLANRX_P4 PETP4 USB3TN2 USB3TN2_JUSB1 <24>
A33 USB3TP2_JUSB1
USB3TP2 USB3TP2_JUSB1 <24>
G17
F17 PERN1/USB3RN3
PERP1/USB3RP3
C30
C31 PETN1/USB3TN3 AJ10 USBRBIAS
PETP1/USB3TP3 USBRBIAS AJ11
F15 USBRBIAS AN10 PAD~D T118 @
PERN2/USB3RN4 RSVD
1
G15 AM10 PAD~D T119 @
PERP2/USB3RP4 RSVD RC90
B31 22.6_0402_1%~D
A31 PETN2/USB3TN4
PETP2/USB3TP4 AL3 USB_OC0#
USB_OC0# <24>
2
OC0/GPIO40 AT1 USB_OC1#
OC1/GPIO41 USB_OC1# <25>
AH2 USB_OC2#
RC91 @ T120PAD~D E15 OC2/GPIO42 AV3 USB_OC3#
3.01K_0402_1% @ T121PAD~D E13 RSVD OC3/GPIO43
1 2 PCH_PCIE_RCOMP A27 RSVD
+1.05VS_AUSB3PLL PCIE_RCOMP
B27 CAD NOTE:
PCIE_IREF
Route single-end 50-ohms and max 500-mils length.
Avoid routing next to clock pins or under stitching capacitors.
11 OF 19 Rev1p2 Recommended minimum spacing to other signal traces is 15 mils.
B B
+3VALW_PCH
USB_OC0# 1 8
USB_OC1# 2 7
USB_OC2# 3 6
USB_OC3# 4 5
RP55
10K_8P4R_5%
A A
+CPU_CORE +1.35V
C40
1 2
+CPU_CORE
UC1L HASWELL_MCP_E
D 22U_0603_6.3V6M D
+1.05VS ESD@
L59 C36
+1.35V J58 RSVD VCC C40
ESD solution RSVD VCC
1
C44
R286 AH26 VCC C48
AJ31 VDDQ VCC C52
10K_0402_5%
AJ33 VDDQ VCC C56
AJ37 VDDQ VCC E23
2
AN33 VDDQ VCC E25
VCCST_PG_EC AP43 VDDQ VCC E27
<30> VCCST_PG_EC VDDQ VCC
AR48 E29
AY35 VDDQ VCC E31
AY40 VDDQ VCC E33
Define EC OD pin, need double confirm. +VCCIO_OUT AY44 VDDQ VCC E35
+CPU_CORE AY50 VDDQ VCC E37
VDDQ VCC E39
2
F59 VCC E41
N58 VCC VCC E43
AC58 RSVD VCC E45
R245 @ RSVD VCC E47
0_0603_5% VCCSENSE E63 VCC E49
VCC_SENSE VCC
1
T38 @ AB23 E51
+VCCIO_OUT_R A59 RSVD VCC E53
E20 VCCIO_OUT VCC E55
+VCCIOA_OUT VCCIOA_OUT VCC
AD23 E57
AA23 RSVD 12 OF 19 VCC F24
AE59 RSVD VCC F28
SVID ALERT +1.05VS
RSVD VCC
VCC
F32
H_CPU_SVIDALRT# L62 F36
0_0402_5% 1 2 R248 H_CPU_SVIDCLK N63 VIDALERT VCC F40
<42> VR_SVID_CLK VIDSCLK VCC
H_CPU_SVIDDATA L63 F44
VIDSOUT VCC
1
CPU_PWR_DEBUG#
+CPU_CORE VDDQ DECOUPLING
2
@
B R255 B
1
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
10K_0402_5%
C35
C36
C37
C38
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
1 1 1 1 1 1 1 1 1 1
R1
1
C39
C41
C72
C42
C45
C74
100_0402_1%
2
2 2 2 2 2 2 2 2 2 2
<15,42> VSSSENSE VSSSENSE CAD Note: PD resistor on HW side +1.35V : 470UF/2V/7343 *2 (PWR)
10UF/6.3V/0603 * 6
1
2.2UF/6.3V/0402 * 4
R2
100_0402_1%
2
A A
D D
Close to N8
+1.05VS C57 @1 2 1U_0402_6.3V6K
+RTCVCC
+1.05VS +1.05VS_AUSB3PLL
1U_0402_6.3V6K
0.1U_0402_10V7K
0.1U_0402_10V7K
2.2UH_LQM2MPN2R2NG0L_30% 1 1 1
UC1M HASWELL_MCP_E
C54
C55
C56
+1.05VS_ASATA3PLL K9
+1.05VS VCCHSIO 2 2 2
L10 0_0603_5% 2 1 R264 +3VALW_PCH
M9 VCCHSIO
L21 2 C63 1 2 1U_0402_6.3V6K N8 VCCHSIO mPHY AH11 C51 1 2 1U_0402_6.3V6K
+1.05VS VCC1_05 VCCSUS3_3
C65 1 2 100U_1206_6.3V6M P9 RTC AG10
VCC1_05 VCCRTC +RTCVCC
2.2UH_LQM2MPN2R2NG0L_30% +1.05VS_AUSB3PLL
B18 AE7
B11 VCCUSB3PLL DCPRTC +VCCRTCEXT C52 1 2 0.1U_0402_10V7K
+1.05VS_APLLOPI +1.05VS_ASATA3PLL VCCSATA3PLL
R267 +3VS
0_0805_5%
1 2 Y20 SPI Y8 @ C68 1 2 0.1U_0402_10V7K
C69 1 2 1U_0402_6.3V6K AA21 RSVD OPI VCCSPI
+1.05VS_APLLOPI VCCAPLL
L31 @ 2 C70 @1 2 100U_1206_6.3V6M W21
2.2UH_LQM2MPN2R2NG0L_30% VCCAPLL AG14 +1.05VS +3VS
VCCASW +1.05VS
AG13 C44
+1.05VS_AXCK_DCB VCCASW 1 2
+1.05VS
T53 @ J13 USB3
DCPSUS3 J11 C60 1 2 10U_0603_6.3V6M 22U_0603_6.3V6M
C83 1 2 1U_0402_6.3V6K VCC1_05 H11 C61 1 2 1U_0402_6.3V6K ESD@
L4 1 2 C84 1 2 100U_1206_6.3V6M AH14 AXALIA/HDA VCC1_05 H15 C62 1 2 1U_0402_6.3V6K
+VCCHDA VCCHDA VCC1_05
2.2UH_LQM2MPN2R2NG0L_30% AE8 C64
C
VCC1_05 AF22 1U_0402_6.3V6K ESD solution C
13 OF 19 Rev1p2
C50 1 2 1U_0402_6.3V6K
+1.05VS C53 1 2 1U_0402_6.3V6K Close to K9,M9
B B
+3VALW_PCH C81 1 2 0.1U_0402_10V7K Close to AH10
@
+3VS
C82 1 2 22U_0603_6.3V6M Close to V8
+1.05VS
C88 1 2 1U_0402_6.3V6K Close to R21
A A
D D
HASWELL_MCP_E HASWELL_MCP_E
UC1N UC1O UC1P HASWELL_MCP_E
H17
A11 AJ35 AP22 AV59 D33 VSS H57
A14 VSS VSS AJ39 AP23 VSS VSS AV8 D34 VSS VSS J10
A18 VSS VSS AJ41 AP26 VSS VSS AW16 D35 VSS VSS J22
A24 VSS VSS AJ43 AP29 VSS VSS AW24 D37 VSS VSS J59
A28 VSS VSS AJ45 AP3 VSS VSS AW33 D38 VSS VSS J63
A32 VSS VSS AJ47 AP31 VSS VSS AW35 D39 VSS VSS K1
A36 VSS VSS AJ50 AP38 VSS VSS AW37 D41 VSS VSS K12
A40 VSS VSS AJ52 AP39 VSS VSS AW4 D42 VSS VSS L13
A44 VSS VSS AJ54 AP48 VSS VSS AW40 D43 VSS VSS L15
A48 VSS VSS AJ56 AP52 VSS VSS AW42 D45 VSS VSS L17
A52 VSS VSS AJ58 AP54 VSS VSS AW44 D46 VSS VSS L18
A56 VSS VSS AJ60 AP57 VSS VSS AW47 D47 VSS VSS L20
AA1 VSS VSS AJ63 AR11 VSS VSS AW50 D49 VSS VSS L58
AA58 VSS VSS AK23 AR15 VSS VSS AW51 D5 VSS VSS L61
AB10 VSS VSS AK3 AR17 VSS VSS AW59 D50 VSS VSS L7
AB20 VSS VSS AK52 AR23 VSS VSS AW60 D51 VSS VSS M22
AB22 VSS VSS AL10 AR31 VSS VSS AY11 D53 VSS VSS N10
C C
AB7 VSS VSS AL13 AR33 VSS VSS AY16 D54 VSS VSS N3
AC61 VSS VSS AL17 AR39 VSS VSS AY18 D55 VSS VSS P59
AD21 VSS VSS AL20 AR43 VSS VSS AY22 D57 VSS VSS P63
AD3 VSS VSS AL22 AR49 VSS VSS AY24 D59 VSS VSS R10
AD63 VSS VSS AL23 AR5 VSS VSS AY26 D62 VSS VSS R22
AE10 VSS VSS AL26 AR52 VSS VSS AY30 D8 VSS VSS R8
AE5 VSS VSS AL29 AT13 VSS VSS AY33 E11 VSS VSS T1
AE58 VSS VSS AL31 AT35 VSS VSS AY4 E17 VSS VSS T58
AF11 VSS VSS AL33 AT37 VSS VSS AY51 F20 VSS VSS U20
AF12 VSS VSS AL36 AT40 VSS VSS AY53 F26 VSS VSS U22
AF14 VSS VSS AL39 AT42 VSS VSS AY57 F30 VSS VSS U61
AF15 VSS VSS AL40 AT43 VSS VSS AY59 F34 VSS VSS U9
AF17 VSS VSS AL45 AT46 VSS VSS AY6 F38 VSS VSS V10
AF18 VSS VSS AL46 AT49 VSS VSS B20 F42 VSS VSS V3
AG1 VSS VSS AL51 AT61 VSS VSS B24 F46 VSS VSS V7
AG11 VSS VSS AL52 AT62 VSS VSS B26 F50 VSS VSS W20
AG21 VSS VSS AL54 AT63 VSS VSS B28 F54 VSS VSS W22
AG23 VSS VSS AL57 AU1 VSS VSS B32 F58 VSS VSS Y10
AG60 VSS VSS AL60 AU16 VSS VSS B36 F61 VSS VSS Y59
AG61 VSS VSS AL61 AU18 VSS VSS B4 G18 VSS VSS Y63
AG62 VSS VSS AM1 AU20 VSS VSS B40 G22 VSS VSS
AG63 VSS VSS AM17 AU22 VSS VSS B44 G3 VSS
AH17 VSS VSS AM23 AU24 VSS VSS B48 G5 VSS V58
AH19 VSS VSS AM31 AU26 VSS VSS B52 G6 VSS VSS AH46
AH20 VSS VSS AM52 AU28 VSS VSS B56 G8 VSS VSS V23
AH22 VSS VSS AN17 AU30 VSS VSS B60 H13 VSS VSS E62
VSS VSS VSS VSS VSS VSS_SENSE VSSSENSE <13,42>
AH24 AN23 AU33 C11 AH16
AH28 VSS VSS AN31 AU51 VSS VSS C14 16 OF 19 Rev1p2 VSS
VSS VSS VSS VSS
1
AH30 AN32 AU53 C18
AH32 VSS VSS AN35 AU55 VSS VSS C20 X@
AH34 VSS VSS AN36 AU57 VSS VSS C25 RC163
AH36 VSS VSS AN39 AU59 VSS VSS C27 100_0402_1%
AH38 VSS VSS AN40 AV14 VSS VSS C38
2
AH40 VSS VSS AN42 AV16 VSS VSS C39
AH42 VSS VSS AN43 AV20 VSS VSS C57
AH44 VSS VSS AN45 AV24 VSS VSS D12
AH49 VSS VSS AN46 AV28 VSS VSS D14
B B
AH51 VSS VSS AN48 AV33 VSS VSS D18
AH53 VSS VSS AN49 AV34 VSS VSS D2
AH55 VSS VSS AN51 AV36 VSS VSS D21
AH57 VSS VSS AN52 AV39 VSS VSS D23 CAD Note: RC163 SHOULD BE PLACED CLOSE TO CPU
AJ13 VSS VSS AN60 AV41 VSS VSS D25
AJ14 VSS VSS AN63 AV43 VSS VSS D26
AJ23 VSS VSS AN7 AV46 VSS VSS D27
AJ25 VSS VSS AP10 AV49 VSS VSS D29
AJ27 VSS VSS AP17 AV51 VSS VSS D30
AJ29 VSS VSS AP20 AV55 VSS VSS D31
VSS VSS VSS 15 OF 19 Rev1p2 VSS
14 OF 19 Rev1p2
A A
D D
HASWELL_MCP_E HASWELL_MCP_E
UC1Q UC1R
@
DC_TEST_AY2_AW2 AY2 A3 DC_TEST_A3_B3 N23 RSVD_N23 PAD~D T129
DAISY_CHAIN_NCTF_AY2 DAISY_CHAIN_NCTF_A3 RSVD @
DC_TEST_AY3_AW3 AY3 A4 DC_TEST_A4 PAD~D T168 @ R23 RSVD_R23 PAD~D T130
DAISY_CHAIN_NCTF_AY3 DAISY_CHAIN_NCTF_A4 RSVD @
@ T166PAD~D DC_TEST_AY60 AY60 @ T23 RSVD_T23 PAD~D T131
DAISY_CHAIN_NCTF_AY60 T128 PAD~D RSVD_AT2 AT2 RSVD @
DC_TEST_AY61_AW61 AY61 A60 DC_TEST_A60 PAD~D T169 @ @ RSVD U10 RSVD_U10 PAD~D T133
DAISY_CHAIN_NCTF_AY61 DAISY_CHAIN_NCTF_A60 T132 PAD~D RSVD_AU44 AU44 RSVD
DC_TEST_AY62_AW62 AY62 A61 DC_TEST_A61_B61 @ RSVD
DAISY_CHAIN_NCTF_AY62 DAISY_CHAIN_NCTF_A61 T134 PAD~D RSVD_AV44 AV44
@ T167PAD~D TP_DC_TEST_B2 B2 A62 DC_TEST_A62 PAD~D T170 @ @ RSVD
DAISY_CHAIN_NCTF_B2 DAISY_CHAIN_NCTF_A62 T135 PAD~D RSVD_D15 D15 @
DC_TEST_A3_B3 B3 AV1 DC_TEST_AV1 PAD~D T171 @ RSVD AL1 RSVD_AL1 PAD~D T136
DAISY_CHAIN_NCTF_B3 DAISY_CHAIN_NCTF_AV1 RSVD @
DC_TEST_A61_B61 B61 AW1 DC_TEST_AW1 PAD~D T172 @ AM11 RSVD_AM11 PAD~D T137
DAISY_CHAIN_NCTF_B61 DAISY_CHAIN_NCTF_AW1 RSVD @
B62 AW2 DC_TEST_AY2_AW2 @ AP7 RSVD_AP7 PAD~D T139
DAISY_CHAIN_NCTF_B62 DAISY_CHAIN_NCTF_AW2 T138 PAD~D RSVD_F22 F22 RSVD @
DC_TEST_B62_B63 B63 AW3 DC_TEST_AY3_AW3 @ RSVD AU10 RSVD_AU10 PAD~D T141
DAISY_CHAIN_NCTF_B63 DAISY_CHAIN_NCTF_AW3 T140 PAD~D RSVD_H22 H22 RSVD @
C1 AW61 DC_TEST_AY61_AW61 @ RSVD AU15 RSVD_AU15 PAD~D T142
DAISY_CHAIN_NCTF_C1 DAISY_CHAIN_NCTF_AW61 T143 PAD~D RSVD_J21 J21 RSVD @
DC_TEST_C1_C2 C2 AW62 DC_TEST_AY62_AW62 RSVD AW14 RSVD_AW14 PAD~D T144
DAISY_CHAIN_NCTF_C2 DAISY_CHAIN_NCTF_AW62 RSVD @
AW63 DC_TEST_AW63 PAD~D T173 @ AY14 RSVD_AY14 PAD~D T145
17 OF 19 Rev1p2 DAISY_CHAIN_NCTF_AW63 RSVD
18 OF 19 Rev1p2
C C
UC1S HASWELL_MCP_E
1
CFG5 Y62 CFG4 RSVD_TP C62 PAD~D T149 @
<6> CFG5 CFG5 RSVD_TP
CFG6 Y61 B43 PAD~D T150 @ RC138
<6> CFG6 CFG6 RSVD
CFG7 Y60 1K_0402_1%
<6> CFG7 CFG7
CFG8 V62 A51 PAD~D T151 @
<6> CFG8 CFG8 RSVD_TP
CFG9 V61 B51 PAD~D T152 @
<6> CFG9 CFG9 RSVD_TP
2
CFG10 V60
<6> CFG10 CFG10
CFG11 U60 L60 PAD~D T153 @
<6> CFG11 CFG11 RESERVED RSVD_TP
CFG12 T63
<6> CFG12 CFG12
CFG13 T62 N60 PAD~D T154 @
<6> CFG13 CFG13 RSVD
B CFG14 T61 B
<6> CFG14 CFG14
CFG15 T60 W23 PAD~D T155 @
<6> CFG15 CFG15 RSVD Y22 PAD~D T156 @ Display Port Presence Strap
CFG16 AA62 RSVD AY15 PROC_OPI_RCOMP
<6> CFG16 CFG16 PROC_OPI_RCOMP
CFG18 U63
<6>
<6>
CFG18
CFG17
CFG17 AA61 CFG18 AV62 PAD~D T157 @ 1: Disabled; No Physical Display Port
CFG19 U62 CFG17 RSVD D58 PAD~D T158 @
<6> CFG19 CFG19 RSVD CFG4 attached to Embedded Display Port
CFG_RCOMP V63 P22
CFG_RCOMP VSS N21 0: Enabled; An external Display Port device is
@ T159PAD~D A5 VSS
RSVD P20 PAD~D T160 @ connected to the Embedded Display Port
@ T161PAD~D E1 RSVD R20 PAD~D T162 @
@ T163PAD~D D1 RSVD RSVD
@ T164PAD~D J20 RSVD
@ T165PAD~D H18 RSVD
TDI_IREF B12 RSVD
TD_IREF
19 OF 19 Rev1p2
2 1 CFG_RCOMP
RC132 49.9_0402_1%
1 2 TDI_IREF PROC_OPI_RCOMP 1 2
RC133 8.2K_0402_1% 49.9_0402_1% RC134
A A
+DIMM1_VREF_DQ
H=4mm
+1.35V +1.35V
1 2 1
JDIMM1 CONN@
2
2-3A to 1 DIMMs/channel
+SM_VREF_DQ0_DIMM1 VREF_DQ VSS1
3 4 DDR_A_D9
VSS2 DQ4
2.2U_0402_6.3V6M
0.1U_0402_10V7K
D @ DDR_A_D13 5 6 DDR_A_D12 D
RD1 DDR_A_D8 7 DQ0 DQ5 8 +1.35V
0_0402_1% 9 DQ1 VSS3 10
Populate RD1, De-Populate RD7 for Intel DDR3 1 1 VSS4 DQS#0
DDR_A_DQS#1
CD1
CD2
11 12 DDR_A_DQS1
VREFDQ multiple methods M1 13 DM0 DQS0 14
1
DDR_A_D14 15 VSS5 VSS6 16 DDR_A_D15
Populate RD7, De-Populate RD1 for Intel DDR3 2 2 17 DQ2 DQ6 18 RD3
DDR_A_D10 DDR_A_D11
VREFDQ multiple methods M3 19 DQ3 DQ7 20 470_0402_5%
DDR_A_D29 21 VSS7 VSS8 22 DDR_A_D25
DDR_A_D28 23 DQ8 DQ12 24 DDR_A_D24
DQ9 DQ13
2
25 26
DDR_A_DQS#3 27 VSS9 VSS10 28 1 2
DQS#1 DM1 <18> DDR3_DRAMRST# DDR3_DRAMRST#_CPU <6>
DDR_A_DQS3 29 30 DDR3_DRAMRST#
31 DQS1 RESET# 32 @
DDR_A_D30 33 VSS11 VSS12 34 DDR_A_D27 @ RD5
<7> DDR_A_DQS#[0..7] DQ10 DQ14 1
DDR_A_D31 35 36 DDR_A_D26 CD3 0_0402_1%
37 DQ11 DQ15 38 0.1U_0402_10V7K
<7> DDR_A_D[0..63] All VREF traces should
DDR_A_D44 39 VSS13 VSS14 40 DDR_A_D45
have 10 mil trace width DQ16 DQ20 2
DDR_A_D41 41 42 DDR_A_D40
<7> DDR_A_DQS[0..7] DQ17 DQ21
43 44
DDR_A_DQS#5 45 VSS15 VSS16 46
<7> DDR_A_MA[0..15] DQS#2 DM2
DDR_A_DQS5 47 48
49 DQS2 VSS17 50 DDR_A_D42
DDR_A_D43 51 VSS18 DQ22 52 DDR_A_D46
Layout Note: Note: DDR_A_D47 53 DQ18 DQ23 54 CAD NOTE
55 DQ19 VSS19 56 DDR_A_D52
Place near JDIMM1 Check voltage tolerance of DDR_A_D51 57 VSS20 DQ28 58 DDR_A_D53
PLACE THE CAP NEAR TO
59 DQ24 DQ29 60
DDR_A_D50
DQ25 VSS21 DIMM RESET PIN
VREF_DQ at the DIMM socket 61
63 VSS22 DQS#3
62
64
DDR_A_DQS#6
DDR_A_DQS6
65 DM3 DQS3 66
DDR_A_D49 67 VSS23 VSS24 68 DDR_A_D54
+1.35V DDR_A_D48 69 DQ26 DQ30 70 DDR_A_D55
71 DQ27 DQ31 72
VSS25 VSS26
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
C 1 1 1 1 1 1 1 1 DDR_CKE0_DIMMA 73 74 DDR_CKE1_DIMMA C
<7> DDR_CKE0_DIMMA CKE0 CKE1 DDR_CKE1_DIMMA <7>
75 76
VDD1 VDD2
CD4
CD5
CD6
CD7
CD8
CD9
CD10
CD11
77 78 DDR_A_MA15
DDR_A_BS2 79 NC1 A15 80 DDR_A_MA14
2 2 2 2 2 2 2 2 <7> DDR_A_BS2 BA2 A14
81 82
DDR_A_MA12 83 VDD3 VDD4 84 DDR_A_MA11
DDR_A_MA9 85 A12/BC# A11 86 DDR_A_MA7
87 A9 A7 88
DDR_A_MA8 89 VDD5 VDD6 90 DDR_A_MA6
DDR_A_MA5 91 A8 A6 92 DDR_A_MA4
93 A5 A4 94
DDR_A_MA3 95 VDD7 VDD8 96 DDR_A_MA2
DDR_A_MA1 97 A3 A2 98 DDR_A_MA0
+1.35V 99 A1 A0 100
<7> M_CLK_DDR0
M_CLK_DDR0
M_CLK_DDR#0
101
103
VDD9
CK0
VDD10
CK1
102
104
M_CLK_DDR1
M_CLK_DDR#1
M_CLK_DDR1 <7> DDR3L SODIMM ODT GENERATION
<7> M_CLK_DDR#0 CK0# CK1# M_CLK_DDR#1 <7>
105 106
VDD11 VDD12 +5VALW +1.35V
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
330U_D3_2.5VY_R6M
1
CD16
CD17
CD12
CD18
CD19
CD20
CD13
CD14
CD15
S
<7> DDR_A_CAS# CAS# ODT0
117 118 R2347 R2348 66.5_0402_1%
DDR_A_MA13 119 VDD15 VDD16 120 M_ODT1 220K_0402_5%~D 1 2 M_ODT1
2 2 2 2 2 2 2 2 2 DDR_CS1_DIMMA# 121 A13 ODT1 122 +SM_VREF_CA_DIMM R2349 66.5_0402_1%
G
<7> DDR_CS1_DIMMA# S1# NC2
2
123 124 1 2
M_ODT2 <18>
2
125 VDD17 VDD18 126 1 2 R2350 66.5_0402_1%
NCTEST VREF_CA
2.2U_0402_6.3V6M
0.1U_0402_10V7K
127 128 1 2
VSS27 VSS28 M_ODT3 <18>
DDR_A_D0 129 130 DDR_A_D5 @ R2352 66.5_0402_1%
DQ32 DQ36
2
DDR_A_D1 131 132 DDR_A_D4 1 1 RD4 @
DQ33 DQ37
CD21
CD22
133 134 0_0402_1% R2351
DDR_A_DQS#0 135 VSS29 VSS30 136 2M_0402_5% 0.675V_DDR_VTT_ON
DQS#4 DM4 0.675V_DDR_VTT_ON <41>
DDR_A_DQS0 137 138
139 DQS4 VSS31 140 DDR_A_D3 2 2
1
DDR_A_D2 141 VSS32 DQ38 142 DDR_A_D7
Layout Note: DQ34 DQ39
DDR_A_D6 143 144
Place near JDIMM1.203,204 145 DQ35 VSS33 146 DDR_A_D18
DDR_A_D21 147 VSS34 DQ44 148 DDR_A_D19
B B
DDR_A_D20 149 DQ40 DQ45 150
151 DQ41 VSS35 152 DDR_A_DQS#2
153 VSS36 DQS#5 154 DDR_A_DQS2
155 DM5 DQS5 156 +1.35V
DDR_A_D17 157 VSS37 VSS38 158 DDR_A_D22 @
DDR_A_D16 159 DQ42 DQ46 160 DDR_A_D23 CD23
+0.675VS 161 DQ43 DQ47 162 U2303 0.1U_0402_10V7K
DDR_A_D36 163 VSS39 VSS40 164 DDR_A_D37 1 5 1 2
DDR_A_D33 165 DQ48 DQ52 166 DDR_A_D32 NC VCC
167 DQ49 DQ53 168 2
VSS41 VSS42 <6> DDR_PG_CTRL A
DDR_A_DQS#4 169 170 4 0.675V_DDR_VTT_ON
DQS#6 DM6 Y
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
10U_0603_6.3V6M
10U_0603_6.3V6M
CD25
CD26
CD27
CD28
CD29
@ +0.675VS
CD30
CD31
205 206
G1 G2
2 2 LCN_DAN06-K4406-0102
A A
+3VS +1.35V
CD62
1 2
22U_0603_6.3V6M
ESD@
Security Classification Compal Secret Data Compal Electronics, Inc.
ESD solution 2013/03/09 2014/04/01 Title
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRIII DIMMA
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9981P
Date: Saturday, March 09, 2013 Sheet 17 of 55
5 4 3 2 1
5 4 3 2 1
+DIMM2_VREF_DQ
H=4mm
+1.35V
JDIMM2 CONN@
+1.35V 2-3A to 1 DIMMs/channel
+SM_VREF_DQ1_DIMM2
1 2 1 2
3 VREF_DQ VSS1 4 DDR_B_D12
VSS2 DQ4
2.2U_0402_6.3V6M
0.1U_0402_10V7K
@ DDR_B_D8 5 6 DDR_B_D9
RD8 DDR_B_D14 7 DQ0 DQ5 8
0_0402_1% 9 DQ1 VSS3 10 DDR_B_DQS#1
1 1 VSS4 DQS#0
CD32
CD33
D 11 12 DDR_B_DQS1 D
13 DM0 DQS0 14
Populate RD4, De-Populate RD8 for Intel DDR3 15 VSS5 VSS6 16
DDR_B_D10 DDR_B_D13
VREFDQ multiple methods M1 2 2 DDR_B_D11 17 DQ2 DQ6 18 DDR_B_D15
19 DQ3 DQ7 20
Populate RD8, De-Populate RD4 for Intel DDR3 DDR_B_D28 21 VSS7 VSS8 22 DDR_B_D25
VREFDQ multiple methods M3 DDR_B_D29 23 DQ8 DQ12 24 DDR_B_D24
25 DQ9 DQ13 26
DDR_B_DQS#3 27 VSS9 VSS10 28
DDR_B_DQS3 29 DQS#1 DM1 30 DDR3_DRAMRST#
DQS1 RESET# DDR3_DRAMRST# <17>
31 32
<7> DDR_B_DQS#[0..7] VSS11 VSS12
DDR_B_D26 33 34 DDR_B_D30 1
DDR_B_D27 35 DQ10 DQ14 36 DDR_B_D31
<7> DDR_B_D[0..63] All VREF traces should DQ11 DQ15
have 10 mil trace width 37 38 @
DDR_B_D40 39 VSS13 VSS14 40 DDR_B_D45 CD34
<7> DDR_B_DQS[0..7] DQ16 DQ20 2
DDR_B_D41 41 42 DDR_B_D44 0.1U_0402_10V7K
43 DQ17 DQ21 44
<7> DDR_B_MA[0..15] VSS15 VSS16
DDR_B_DQS#5 45 46
DDR_B_DQS5 47 DQS#2 DM2 48
49 DQS2 VSS17 50 DDR_B_D47
Layout Note: Note: DDR_B_D46 51 VSS18
DQ18
DQ22
DQ23
52 DDR_B_D43
CAD NOTE
DDR_B_D42 53 54
Place near JDIMM2 Check voltage tolerance of 55 DQ19 VSS19 56
DDR_B_D56 57 VSS20 DQ28 58
DDR_B_D61
DDR_B_D60
PLACE THE CAP NEAR TO
DQ24 DQ29
VREF_DQ at the DIMM socket DDR_B_D57 59
61 DQ25 VSS21
60
62 DDR_B_DQS#7
DIMM RESET PIN
63 VSS22 DQS#3 64 DDR_B_DQS7
65 DM3 DQS3 66
DDR_B_D59 67 VSS23 VSS24 68 DDR_B_D63
DDR_B_D58 69 DQ26 DQ30 70 DDR_B_D62
+1.35V 71 DQ27 DQ31 72
VSS25 VSS26
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
DDR_CKE2_DIMMB 73 74 DDR_CKE3_DIMMB
<7> DDR_CKE2_DIMMB CKE0 CKE1 DDR_CKE3_DIMMB <7>
1 1 1 1 1 1 1 1 75 76
77 VDD1 VDD2 78 DDR_B_MA15
NC1 A15
CD35
CD36
CD37
CD38
CD39
CD40
CD41
CD42
C DDR_B_BS2 79 80 DDR_B_MA14 C
<7> DDR_B_BS2 BA2 A14
81 82
2 2 2 2 2 2 2 2 DDR_B_MA12 83 VDD3 VDD4 84 DDR_B_MA11
DDR_B_MA9 85 A12/BC# A11 86 DDR_B_MA7
87 A9 A7 88
DDR_B_MA8 89 VDD5 VDD6 90 DDR_B_MA6
DDR_B_MA5 91 A8 A6 92 DDR_B_MA4
93 A5 A4 94
DDR_B_MA3 95 VDD7 VDD8 96 DDR_B_MA2
DDR_B_MA1 97 A3 A2 98 DDR_B_MA0
+1.35V 99 A1 A0 100
M_CLK_DDR2 101 VDD9 VDD10 102 M_CLK_DDR3
<7> M_CLK_DDR2 CK0 CK1 M_CLK_DDR3 <7>
M_CLK_DDR#2 103 104 M_CLK_DDR#3
<7> M_CLK_DDR#2 CK0# CK1# M_CLK_DDR#3 <7>
105 106
VDD11 VDD12
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
330U_D3_2.5VY_R6M
CD44
CD45
CD46
CD47
CD48
CD49
CD50
CD51
2.2U_0402_6.3V6M
0.1U_0402_10V7K
DDR_B_D4 129 130 DDR_B_D5 @
DDR_B_D1 131 DQ32 DQ36 132 DDR_B_D0 RD10
133 DQ33 DQ37 134 0_0402_1%
VSS29 VSS30 1 1
CD53
DDR_B_DQS#0 135 136
DQS#4 DM4
CD52
DDR_B_DQS0 137 138
139 DQS4 VSS31 140 DDR_B_D2
DDR_B_D3 141 VSS32 DQ38 142 DDR_B_D6 2 2
DDR_B_D7 143 DQ34 DQ39 144
145 DQ35 VSS33 146
Layout Note: VSS34 DQ44
DDR_B_D16
DDR_B_D21 147 148 DDR_B_D17
Place near JDIMM2.203,204 DDR_B_D20 149 DQ40 DQ45 150
151 DQ41 VSS35 152 DDR_B_DQS#2
153 VSS36 DQS#5 154 DDR_B_DQS2
B B
155 DM5 DQS5 156
DDR_B_D22 157 VSS37 VSS38 158 DDR_B_D19
DDR_B_D23 159 DQ42 DQ46 160 DDR_B_D18
161 DQ43 DQ47 162
DDR_B_D36 163 VSS39 VSS40 164 DDR_B_D37
+0.675VS DDR_B_D33 165 DQ48 DQ52 166 DDR_B_D32
167 DQ49 DQ53 168
DDR_B_DQS#4 169 VSS41 VSS42 170
DDR_B_DQS4 171 DQS#6 DM6 172
173 DQS6 VSS43 174 DDR_B_D34
VSS44 DQ54
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
10U_0603_6.3V6M
10U_0603_6.3V6M
CD55
CD56
CD57
CD58
CD59
0.1U_0402_10V7K
205 206
G1 G2
2.2U_0402_6.3V6M
1 1
CD61
@ LCN_DAN06-K4406-0102
CD60
2
2 2
A A
0.1U_0402_10V7K
0.1U_0402_10V7K
10U_0603_6.3V6M
0.1U_0402_10V7K
22U_0805_6.3V6M
0.1U_0402_10V7K
0.1U_0402_10V7K
30mil 30mil
CX35 LVDS@
CX33
CX31
CX45 LVDS@
CX41
CX36 LVDS@
CX40
CX34
1 1 1 1 1 1 1 1
D 1 2 +SWR_V12 D
LVDS@
LVDS@
LVDS@
LVDS@
LVDS@
22U_0805_6.3V6M
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
@
2 2 2 2 2 2 2 2
CX48 LVDS@
CX37
CX47
CX32
RX4 1 1 1 1
0_0805_1%
LVDS@
LVDS@
LVDS@
2 2 2 2
Close to 5 pin Close to 18 pin Close to 22 pin
+3VS_RT +3VS_RT
UX4 LVDS@
+DVCC33 RTD2136R
1
@ 35 LVDS_ACLK+
+3VS_RT TXOC+ LVDS_ACLK+ <31>
RX168 RX169 22 36 LVDS_ACLK-
EEPROM 4.7K_0402_5% 4.7K_0402_5% EEPROM LVDS@ LX7 2 1 +DVCC33 40 mils 18
PVCC TXOC-
41 LVDS_A0+
LVDS_ACLK- <31>
TXO0-
PWR
LVDS@ LX8 2 1 +AVCC33 5
FBMA-L11-201209-221LMA30T_0805 DP_V33 39 LVDS_A1+
TXO1+ LVDS_A1+ <31>
MIIC_SDA MIIC_SCL +SWR_V12 LVDS@ LX9 1 2 +SW_LX 60 mils 17 40 LVDS_A1-
SWR_LX TXO1- LVDS_A1- <31>
4.7UH_PG031B-4R7MS_1.1A_20%
60 mils 15 37 LVDS_A2+
SWR_VCCK TXO2+ LVDS_A2+ <31>
1
@ 38 LVDS_A2-
TXO2- LVDS_A2- <31>
RX170 RX171 43
ROMLESS 4.7K_0402_5% 4.7K_0402_5% ROMLESS 11
VCCK
TXO3+
33
34
C C
LVDS@ DP_V12 TXO3-
2
25 LVDS_BCLK+
LVDS_BCLK+ <31>
LVDS
EDP_CPU_LANE_P0 CX42 1 2 0.1U_0402_10V7K CPU_EDP_P0_C 7 TXEC+ 26 LVDS_BCLK-
<6> EDP_CPU_LANE_P0 LANE0P TXEC- LVDS_BCLK- <31>
EDP_CPU_LANE_N0 CX46 1 2 0.1U_0402_10V7K CPU_EDP_N0_C 8
<6> EDP_CPU_LANE_N0 LANE0N 31 LVDS_B0+
TXE0+ LVDS_B0+ <31>
EDP_CPU_LANE_P1 CX38 1 2 0.1U_0402_10V7K CPU_EDP_P1_C 9 32 LVDS_B0-
<6> EDP_CPU_LANE_P1 LANE1P TXE0- LVDS_B0- <31>
EDP_CPU_LANE_N1 CX39 1 2 0.1U_0402_10V7K CPU_EDP_N1_C 10
<6> EDP_CPU_LANE_N1 LANE1N
DP
29 LVDS_B1+
TXE1+ LVDS_B1+ <31>
EDP_CPU_AUX CX43 1 2 0.1U_0402_10V7K CPU_EDP_AUX_C 4 30 LVDS_B1-
<6> EDP_CPU_AUX AUX-CH_P TXE1- LVDS_B1- <31>
EDP_CPU_AUX# CX44 1 2 0.1U_0402_10V7K CPU_EDP_AUX#_C 3
<6> EDP_CPU_AUX# AUX-CH_N 27 LVDS_B2+
TXE2+ LVDS_B2+ <31>
EDP_CPU_HPD 1 28 LVDS_B2-
<10> EDP_CPU_HPD DP_HPD TXE2- LVDS_B2- <31>
23
+3VS_RT EDP_CPU_HPD TXE3+ 24
TXE3-
1
EDP_BIA_PWM 21
<10,6> EDP_BIA_PWM PWMIN
1
OTHERS
RX30 100K_0402_5%
100K_0402_5% LVDS@ 20 TL_ENVDD
PANEL_VCC TL_ENVDD <31>
2
19 TL_INVT_PWM
TL_INVT_PWM <31>
2
1
EDP_BIA_PWM
DDR_XDP_WLAN_TP_SMBCLK RX6 1 @ 2 0_0402_5% CSCL 13 6
<17,18,26,27,6,9> DDR_XDP_WLAN_TP_SMBCLK CIICSCL1 DP_GND
1
GND
16 100K_0402_5%
RX25 @ RX36 GND
2
100K_0402_5% 100K_0402_5% 49
PAD
2
@ RTD2136R-CG_QFN48_6x6
B AUX termination B
RTD2136S : SA00004NW10
RTD2136R : SA000067100
+3VS_RT
CPU_EDP_AUX#_C RX37 1 eDP@ 2 0_0402_5% EDP_AUX# RX38 1 eDP@ 2 0_0402_5% LVDS_B0-
LVDS@
CPU_EDP_P0_C RX41 1 eDP@ 2 0_0402_5% EDP_P0 RX42 1 eDP@ 2 0_0402_5% LVDS_B1-
G
+DVCC33
will swap NET on cable
VCC
1
<30> BKOFF# IN1 4 EDP_BIA_PWM RX49 1 eDP@ 2 0_0402_5% TL_INVT_PWM
OUT TL_BKOFF# <31>
TL_BKOFF#_R 2 Across to UX4.19 & UX4.21
GND
1 8 IN2
2 7 UX2 LVDS@ BKOFF# RX50 1 eDP@ 2 0_0402_5% TL_BKOFF#
EDID_CLK 3 6 MC74VHC1G08DFT2G_SC70-5 Close to UX2
3
EDID_DATA 4 5
ENVDD_PCH RX51 1 eDP@ 2 0_0402_5% TL_ENVDD
<10,30> ENVDD_PCH
A RP56 LVDS@ Close to UX4 A
2.2K_8P4R_5%
EDP_CPU_HPD RX52 1 eDP@ 2 0_0402_5% EDP_HPD_PANEL
EDP_HPD_PANEL <31>
1 8
Close to UX4
CSDA
CSCL 2 7 For eDP co-layout
3 6
4 5
RP57 @
2.2K_8P4R_5%
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2013/03/09 2014/04/01 Title
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
eDP to LVDS converter
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9981P
Date: Saturday, March 09, 2013 Sheet 19 of 55
5 4 3 2 1
5 4 3 2 1
W=40mils
D Place close to JHDMI1 D
+VDISPLAY_VCC
WCM-2012HS-900T_4P
TMDS_TXCN 1 2 TMDS_L_TXCN +5VS
2 1
1 2
10U_0603_6.3V6M
0.1U_0402_16V7K
1 1
CX21
CX12 2 1 0.1U_0402_10V7K TMDS_TXCN FX1
<6> DDI1_LANE_N3
CX13 2 1 0.1U_0402_10V7K TMDS_TXCP TMDS_TXCP 4 3 TMDS_L_TXCP 1.5A_6V_1206L150PR~D CX22
<6> DDI1_LANE_P3 4 3
CX14 2 1 0.1U_0402_10V7K TMDS_TX0N LX2 EMI@ +3VS 2 2
<6> DDI1_LANE_N2
CX15 2 1 0.1U_0402_10V7K TMDS_TX0P
<6> DDI1_LANE_P2
CX16 2 1 0.1U_0402_10V7K TMDS_TX1N
<6> DDI1_LANE_N1
CX17 2 1 0.1U_0402_10V7K TMDS_TX1P
<6> DDI1_LANE_P1
1
CX18 2 1 0.1U_0402_10V7K TMDS_TX2N RX12
<6> DDI1_LANE_N0 WCM-2012HS-900T_4P
CX19 2 1 0.1U_0402_10V7K TMDS_TX2P 10K_0402_5%
<6> DDI1_LANE_P0
TMDS_TX0N 1 2 TMDS_L_TX0N
1 2
2
JHDMI
TMDS_TX0P 4 3 TMDS_L_TX0P HDMI_HPLUG 19
1
2
3
4
4
3
2
1
4 3 18 HP_DET
RP59 RP58 LX3 EMI@ 17 +5V
CPU_DPB_CTRLDAT_R 16 DDC/CEC_GND
680_8P4R_5% 680_8P4R_5%
CPU_DPB_CTRLCLK_R 15 SDA
14 SCL
Reserved
8
7
6
5
5
6
7
8
13
TMDS_L_TXCN 12 CEC 20
11 CK- GND 21
WCM-2012HS-900T_4P TMDS_L_TXCP 10 CK_shield GND 22
TMDS_TX1N 1 2 TMDS_L_TX1N TMDS_L_TX0N 9 CK+ GND 23
1 2 8 D0- GND
TMDS_L_TX0P 7 D0_shield
+3VS TMDS_TX1P 4 3 TMDS_L_TX1P TMDS_L_TX1N 6 D0+
4 3 D1-
1
5
D LX4 EMI@ TMDS_L_TX1P 4 D1_shield
C C
2 QX3 TMDS_L_TX2N 3 D1+
G 2N7002K_SOT23-3 2 D2-
D2_shield
1
S TMDS_L_TX2P 1
RX13 D2+
3
100K_0402_5% LOTES_ABA-HDM-022-K01
CONN@
2
LX5 EMI@
TMDS_TX2P 4 3 TMDS_L_TX2P
4 3
TMDS_TX2N 1 2 TMDS_L_TX2N
1 2
WCM-2012HS-900T_4P
RX16 RX17
2.2K_0402_5% 2.2K_0402_5%
QX4B
2
DMN66D0LDW-7_SOT363-6 +3VS
G
1 6 CPU_DPB_CTRLCLK_R
<10> CPU_DPB_CTRLCLK
S
D
5
1
C
QX5 2 1 2 HDMI_HPLUG
G
<10> CPU_DPB_CTRLDAT
4 3 CPU_DPB_CTRLDAT_R MMBT3904_NL_SOT23-3 B
S
E RX15 1
1
QX4A <10> DPB_HPD 150K_0402_5%
DMN66D0LDW-7_SOT363-6 CX20 @
1
220P_0402_50V8J RX34
2 20K_0402_5%
RX14
2
100K_0402_5%
2
A A
W=40mils
JP3 @
2 1
W=40mils
+3VALW 2MM
+LAN_IO rising time : >1ms and <100ms
+LAN_IO
CL39 W=40mils 1.5A
1U_0402_6.3V6K UL2
2 1 5 1
VIN VOUT
0.1U_0402_10V7K
0.1U_0402_10V7K
1 1
D WOL_EN 3 D
<30> WOL_EN EN CL15 CL19
4 2 2 2 RL19
SS GND
2
75_0603_5%
RL27 APL3512ABI-TRG_SOT23-5 MCT0 1 2
100K_0402_5% 1
@
CL38 MCT1 1 2
These caps close to Pin 23,32
1
0.1U_0603_25V7K
2 RL20 1
For 8106E pop the capacitor close pin 23,32 75_0603_5% EMI@
CL33
10P_1206_2KV8J
2
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
1 1 1
CL20 CL22 CL26 TL1
2 2 2 MDI1- 1 16 MDO1-
MDI1+ 2 RD+ RX+ 15 MDO1+
3 RD- RX- 14 MCT0
4 CT CT 13
5 NC NC 12
These caps close to Pin 8,30 MDI0-
6
7
NC
CT
NC
CT
11
10
MCT1
MDO0-
TD+ TX+
For 8106E pop capacitor close to pin 8,30 MDI0+ 8
TD- TX-
9 MDO0+
C 2 C
X'FORM_ NS0014
CL30, CL31 close to UL1 Pin 17, 18 CL41
0.01U_0402_16V7K
UL1 1 Change CPN to SP050007J00 only
CL30 1 2 0.1U_0402_10V7K PCIE_PRX_LANTX_P3_C 17 1 MDI0+ Need CIS symbol
<12> PCIE_PRX_LANTX_P3 HSOP MDIP0
CL31 1 2 0.1U_0402_10V7K PCIE_PRX_LANTX_N3_C 18 4 MDI1+
<12> PCIE_PRX_LANTX_N3 HSON MDIP1 2 MDI0-
MDIN0 5 MDI1-
PCIE_PTX_LANRX_P3 13 MDIN1
<12> PCIE_PTX_LANRX_P3 HSIP
PCIE_PTX_LANRX_N3 14
<12> PCIE_PTX_LANRX_N3 HSIN 8
AVDD10 30
+LAN_VDD For GCLK
19 AVDD10 32
<10,26,30,48,6> PLT_RST# PERSTB AVDD33 +LAN_IO
23 XTLI
DVDD33 <29> XTLI
ISOLATEB 20
ISOLATEB 15
REFCLK_P CLK_PCIE_LAN <9>
PCIE_WAKE# 21 16
<10,30> PCIE_WAKE# LANWAKEB REFCLK_N CLK_PCIE_LAN# <9>
26 12
PAD~D T96 @ GPO CLKREQB LAN_CLKREQ# <9>
28 XTLO CL36
CKXTAL1 29 XTLI 1 2 XTLI
3 CKXTAL2
6 NC 27 @ T94 PAD~D 10P_0402_50V8J YL2 XTAL@
7 NC LED0 25 @ T95 PAD~D XTAL@ 1 2
+LAN_IO 9 NC LED1 OSC GND
10 NC 31 RL31 2 1 2.49K_0402_1% 3 4
11 NC RSET OSC GND
22 NC 33 CL37 25MHZ_10PF_7V25000014
1 2 PCIE_WAKE# 24 NC GND 1 2 XTLO
NC
RL34 RTL8106E-CG_QFN32_4X4 10P_0402_50V8J
10K_0402_5% XTAL@
B
W=20mils B
+LAN_VDD
0.1U_0402_10V7K
1U_0402_6.3V6K
1 1
JLAN
CL34 CL35
8
2 2 PR4-
7
PR4+
MDO1- 6
+3VS PR2-
+LAN_IO 5
PR3-
1
4
RL33 PR3+
1K_0402_5% @ MDO1+ 3
RL37 10K_0402_5% PR2+
LAN_CLKREQ# 1 2 MDO0- 2
2
PR1-
ISOLATEB RL38 10K_0402_5% MDO0+ 1
WOL_EN 1 2 PR1+
@ 9
SHLD1
2
10
RL35 SHLD2
15K_0402_5%
Reserve 10K pull LAN_IO SANTA_130456-311
CONN@
1
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LAN RTL8106E
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9981P
Date: Saturday, March 09, 2013 Sheet 21 of 55
5 4 3 2 1
5 4 3 2 1
1
RA9 1 @ 2 0_0402_5%
RA165
4.7K_0402_5%
RA166 JACK_PLUG Delay circutis
4.7K_0402_5%
+5V_PVDD +5V_PVDD +5VA
+3VS +3VS
2
+5V_PVDD +5VS
4.7U_0603_6.3V6K
CA55
4.7U_0603_6.3V6K
CA53
4.7U_0603_6.3V6K
CA71
CA53, CA55 change Value 1 1 1
1 1 1 LINE1-L CA67 1 2 1 2 Line-IN-L
from 10U_0603_6.3V6M~D to
1
0.1U_0402_16V7K
CA56
0.1U_0402_16V7K
CA54
0.1U_0402_16V7K
CA51
D 2 1 4.7U_0603_6.3V6K RA80 1K_0402_1% @ @ JACK_SENSE# D
4.7U_0603_6.3V6K RV54 LINE1-R CA68 1 2 1 2 Line-IN-R RA1 RA2
2 2 2 +5VA @ 0_0603_1% +5VS 4.7U_0603_6.3V6K RA82 1K_0402_1% 100K_0402_5% 100K_0402_5%
2 2 2
2
2 1
3
RV59 @
+3VS @ 0_0603_1% 5 G
D
QA5A
UA1 @ S DMN66D0LDW-7_SOT363-6
1 1 QA5B
4
0.1U_0402_16V7K
CA58
4.7U_0603_6.3V6K
CA57
41 AVDD1 16 @ S
2 2 +3VS PVDD1 MONO-OUT
1 1 46 @ CA69 1 2 100P_0402_50V8J RA3
PVDD2
1
CA59 CA60 24 10K_0402_5% 1 1
4.7U_0603_6.3V6K 0.1U_0402_16V7K 1 LINE2-L(PORT-E-L) 23
36 DVDD LINE2-R(PORT-E-R) @ RA81 2 1 10K_0402_5% @ @
2 2 CPVDD 22 LINE1-L CA1 CA2
9 LINE1-L(PORT-C-L) 21 LINE1-R 10U_0603_6.3V6M 2 2 10U_0603_6.3V6M
CA57,CA58 close +CODEC_AVDD2 1 40 DVDD-IO LINE1-R(PORT-C-R)
CA61 AVDD2
to UA1 pin1 4.7U_0603_6.3V6K 20 CA74 10U_0603_6.3V6M
MIC1-R(PORT-B-R) 19 MIC1-L 1 2
RA130 1 2 22_0402_5% 2 8 MIC1-L(PORT-B-L)
<8> PCH_AZ_CODEC_SDIN0 SDATA-IN
<8> PCH_AZ_CODEC_SDOUT
5 18 MIC_IN
6 SDATA-OUT MIC2-R(PORT-F-R) 17 RING2
<8> PCH_AZ_CODEC_BITCLK BCLK MIC2-L(PORT-F-L)
<8> PCH_AZ_CODEC_SYNC
10 JACK_PLUG# RA4 1 @ 2 0_0402_1% JACK_SENSE#
11 SYNC
<8> PCH_AZ_CODEC_RST# RESETB
ALC3223-CG_MQFN48_6X6~D
Place on the moat between GND & GNDA.
LA1 EMI@
MIC_CLK_C 1 2 MIC_CLK
MIC_CLK <31>
BLM15BB221SN1D_2P DA8
2
EC Beep <30> BEEP#
+3VALW SM01000BV00 1
@EMI@ 1 PC_BEEP
CA22
need CIS symbol 22P_0402_50V8J 3
MCU Beep <11> HDA_SPKR
1
2
1
MIC_IN BAT54C-7-F_SOT23-3 @
RA5 RA19
100K_0402_5% 10K_0402_5%
2
2
PC Beep
3
B D B
5 G
QA6A
QA6B S DMN66D0LDW-7_SOT363-6
DMN66D0LDW-7_SOT363-6
Close to UA1
6
@ D
PCH_AZ_CODEC_RST# 1 2 2
Pin11,13,14,16
G
RA6 10K_0402_5% S
close to Codec
1
+3VS 1 2 JSPK
RA7 10K_0402_5% INT-SPK-R- EMI@ LA3 1 2 0_0603_5% SPK_R1-_CONN 1
INT-SPK-R+ EMI@ LA4 1 2 0_0603_5% SPK_R2+_CONN 2 1
INT-SPK-L- EMI@ LA5 1 2 0_0603_5% SPK_L1-_CONN 3 2 5
INT-SPK-L+ EMI@ LA6 1 2 0_0603_5% SPK_L2+_CONN 4 3 GND 6
4 GND
E&T_3703-Q04N-11R
Trace width for SPK-L+/SPK-L-/SPK-R+/SPK-R- CONN@
1000P_0402_50V7K
1000P_0402_50V7K
1000P_0402_50V7K
1000P_0402_50V7K
1 1 1 1
Speaker 4 ohm : 40mil
CA29
EMI@ CA30
EMI@ CA31
EMI@ CA32
Speaker 8 ohm : 20mil 2 2 2 2
EMI@
iPhone and Nokia type Combo Jack
EMI@
MIC_IN LA7 2 1 FBMA-L10-160808-800LMT_2P 40mil MIC_IN_R
EMI@
RA55 RING2 LA10 2 1 FBMA-L10-160808-800LMT_2P 40mil RING2_R JHP
8.2_0402_1% EMI@ RING2_R 3
HPOUT-L 1 2 Line-IN-L LA8 2 1 FBMA-L10-160808-800LMT_2P AUD_HP_OUT_L_CN AUD_HP_OUT_L_CN 1
EMI@
HPOUT-R 1 2 Line-IN-R LA9 2 1 FBMA-L10-160808-800LMT_2P AUD_HP_OUT_R_CN
JACK_PLUG# 5
8.2_0402_1%
1
RA56
RA84 RA83 6
10K_0402_5% 10K_0402_5% AUD_HP_OUT_R_CN 2
MIC_IN_R 4
A 7 A
2
2
AZ5125-02S.R7G_SOT23-3
DA10
ESD@
AZ5125-02S.R7G_SOT23-3
DA12
ESD@
SINGA_2SJ3080-000111F
1 1 1 1 CONN@
100P_0402_50V8J
CA39 EMI@
100P_0402_50V8J
CA33 EMI@
100P_0402_50V8J
CA38 EMI@
100P_0402_50V8J
CA40 EMI@
2 2 2 2
1
D D
SD_CD# MS_INS#
1 1
CR9 EMI@ CR10 EMI@
0.1U_0402_10V7K 0.1U_0402_10V7K
+3VS +VCC_3IN1 2 2
5
UR1
3V3_IN
CARD_3V3
RR1 2 1 6.19K_0402_1% RREF 1 22 MS_BS
EMI@ RREF SP14 21 SD_D2
LR2 SP13 20 MS_D1_SD_D3
<12> USB20_CR_P6
USB20_CR_P6 4
4 3
3 USB20_CR_P6_R USB20_CR_N6_R 2
DM
SP12
SP11
19 close to chip side
USB20_CR_P6_R 3 18 SD_CMD
DP SP10 16 MS_D0
<12> USB20_CR_N6
USB20_CR_N6 1
1 2
2 USB20_CR_N6_R SP9
SP8
15 MS_D2_SD_CLK_R 1 2 MS_D2_SD_CLK 拉MS_D2_SD_CLK到Conn pin 13 SD_CLK
WCM-2012HS-900T_4P
RTS5179-GR_QFN24
EMI@
RR2 再打Via拉到pin 10 MS_D2
14 22_0402_5%
7 SP7 13 SD_CD#
23 XD_CD# SP6 12 MS_D3
17 XD_D7 SP5 11 SD_D0
GPIO0 SP4 10
Thermal pad
SD_D1
6 SP3 9 MS_INS#
C V18 24 SDREG
V18
SP2
SP1
8 MS_CLK_SD_WP_R 1 2 MS_CLK_SD_WP 拉MS_CLK_SD_WP到Conn pin 5 MS_CLK C
5P_0402_50V8C
CR5
EMI@
5P_0402_50V8C
CR6
EMI@
2 2 RR3
22_0402_5%
25
1U_0402_6.3V6K
CR3
1U_0402_6.3V6K
CR4
RTS5179-GR_QFN24_4X4
2 2
1 1
+3VS
1 1
CR1 CR2
+VCC_3IN1
0.1U_0402_10V7K 4.7U_0603_6.3V6K
2 2
+VCC_3IN1
JREAD
SD_D2 1
2 SD-DAT2
MS_D1_SD_D3 3 MS-VSS1
4 SD-CD/DAT3 MMC-RSV
MS_CLK_SD_WP 5 MS-VCC
SD_CMD 6 MS-SCLK
1 1 SD-CMD MMC-CMD
CR8 CR7 MS_D3 7
MS_INS# 8 MS-DATA3
4.7U_0603_6.3V6K 0.1U_0402_10V7K 9 MS-INS
2 2 MS_D2_SD_CLK 10 SD-VSS MMC-VSS1
11 MS-DATA2
B B
MS_D0 12 SD-VDD MMC-VDD
MS_D1_SD_D3 13 MS-DATA0
MS_D2_SD_CLK 14 MS-DATA1
MS_BS 15 SD-CLK MMC-CLK
16 MS-BS
17 MS-VSS2
Close to JREAD SD_D0
SD_D1
18
19
SD-VSS MMC-VSS2
SD-DAT0 MMC-DAT
SD_CD# 20 SD-DAT1
21 SD-CD 23
MS_CLK_SD_WP 22 SD-GND GND1 24
SD-WP(SW) GND2
T-SOL_143-2300302602_RV
SD_CMD CONN@
1
EMI@
CR11
10P_0402_50V8J
2
For EMI request.
Place close to JREAD
A A
+5VALW
1 1 1
CI18 CI12 CI14
<12> USB3RP2_JUSB1
USB3RP2_JUSB1 4 3 USB3RP2_JUSB1_R 1
2 GND
VIN
VOUT
VOUT
8
7 80mil USB20 port1
DLW21SN670HQ2L_4P 3 6
VIN VOUT
USB30 port2
EPAD
USB_EN# 4 5 USB_OC0#
<25,30> USB_EN# EN FLG
1 1
CI13 CI15
9
AP2301MPG-13_MSOP8 +5V_USB_PWR1
0.1U_0402_16V7K
0.1U_0402_16V7K JUSB1
2 2 USB3TP2_JUSB1_R 9
1 SSTX+
VBUS
10U_0603_6.3V6M
0.1U_0402_16V7K
USB3TN2_JUSB1_R 8
USB20_JUSB1_P1_R 3 SSTX-
1 D+
1 1 7
LI3 EMI@ CI1 + USB20_JUSB1_N1_R 2 GND 10
D- GND
CI40
CI2
USB3TN2_JUSB1 2 1 USB3TN2_JUSB1_C 1 2 USB3TN2_JUSB1_R USB3RP2_JUSB1_R 6 11
<12> USB3TN2_JUSB1 SSRX+ GND
CI3 0.1U_0402_10V7K 220U_6.3V_M 4 12
2 2 2 USB3RN2_JUSB1_R 5 GND GND 13
SSRX- GND
3
USB3TP2_JUSB1 2 1 USB3TP2_JUSB1_C 4 3 USB3TP2_JUSB1_R
<12> USB3TP2_JUSB1
CI4 0.1U_0402_10V7K ESD@ ACON_TARA4-9K1311
DLW21SN670HQ2L_4P DI1 DI2 CONN@
USB3RN2_JUSB1_R 1 10 USB3RN2_JUSB1_R
L30ESDL5V0C3-2_SOT23-3
USB3RP2_JUSB1_R 2 9 USB3RP2_JUSB1_R
ESD@
USB3TN2_JUSB1_R 4 7 USB3TN2_JUSB1_R
1
USB3TP2_JUSB1_R 5 6 USB3TP2_JUSB1_R
3
EMI@ 8
LI2
USB20_JUSB1_N1 1 2 USB20_JUSB1_N1_R IP4292CZ10-TBR_XSON10_2.5X1~D
<12> USB20_JUSB1_N1 1 2
C C
USB20_JUSB1_P1 4 3 USB20_JUSB1_P1_R
<12> USB20_JUSB1_P1 4 3
WCM-2012HS-900T_4P
+5VALW
1 1
CI6 CI7
USB3RP1_JUSB2 4 3 USB3RP1_JUSB2_R 1
UI2
8
USB connector2
<12> USB3RP1_JUSB2 GND VOUT 80mil
B
DLW21SN670HQ2L_4P
2
3 VIN
VIN
VOUT
VOUT
7
6 USB20 port0 B
EPAD
USB_EN# 4 5 USB_OC0#
EN FLG USB_OC0# <12>
USB30 port1
1 1
CI26 CI17
9
AP2301MPG-13_MSOP8
0.1U_0402_16V7K
0.1U_0402_16V7K
2 2
+5V_USB_PWR2
JUSB2 CONN@
LI6 EMI@ USB3TP1_JUSB2_R 9
USB3TN1_JUSB2 2 1 USB3TN1_JUSB2_C 1 2 USB3TN1_JUSB2_R 1 SSTX+
<12> USB3TN1_JUSB2 VBUS
10U_0603_6.3V6M
0.1U_0402_16V7K
CI10 0.1U_0402_10V7K USB3TN1_JUSB2_R 8
USB20_JUSB2_P0_R 3 SSTX-
1 D+
USB3TP1_JUSB2 2 1 USB3TP1_JUSB2_C 4 3 USB3TP1_JUSB2_R 1 1 7
<12> USB3TP1_JUSB2 GND
CI11 0.1U_0402_10V7K CI8 + USB20_JUSB2_N0_R 2 10
D- GND
CI43
CI9
DLW21SN670HQ2L_4P USB3RP1_JUSB2_R 6 11
220U_6.3V_M 4 SSRX+ GND 12
2 2 2 USB3RN1_JUSB2_R 5 GND GND 13
ESD@ SSRX- GND
3
DI4 ACON_TARA4-9K1311
USB3RN1_JUSB2_R 1 10 USB3RN1_JUSB2_R
DI5
USB3RP1_JUSB2_R 2 9 USB3RP1_JUSB2_R
L30ESDL5V0C3-2_SOT23-3
USB3TN1_JUSB2_R 4 7 USB3TN1_JUSB2_R
ESD@
EMI@ USB3TP1_JUSB2_R 5 6 USB3TP1_JUSB2_R
LI5
1
USB20_JUSB2_N0 1 2 USB20_JUSB2_N0_R 3
<12> USB20_JUSB2_N0 1 2
8
USB20_JUSB2_P0 4 3 USB20_JUSB2_P0_R
<12> USB20_JUSB2_P0 4 3 IP4292CZ10-TBR_XSON10_2.5X1~D
WCM-2012HS-900T_4P
A A
+5VALW
1 1 1
D CI27 CI23 CI22 D
47U_0805_6.3V4Z
2
4.7U_0805_10V4Z
2 2
0.1U_0402_16V7K 2.0A +5V_USB_PWR3
1
UI4
8
USB connector3
GND VOUT 80mil
2
3 VIN VOUT
7
6 USB20 port2
VIN VOUT
EPAD
USB_EN# 4 5 USB_OC1#
<24,30> USB_EN# EN FLG
1 1
CI16 CI24
9
AP2301MPG-13_MSOP8
0.1U_0402_16V7K
0.1U_0402_16V7K
2 2
+5V_USB_PWR3
+5V_USB_PWR3
JUSB3
1
USB20_JUSB3_N2_R 2 VBUS
D-
0.1U_0402_16V7K
10U_0603_6.3V6M
USB20_JUSB3_P2_R 3
4 D+
GND 1
5 1 1
GND
3
6 CI20 +
GND
CI19
CI44
7
DI7 8 GND 220U_6.3V_M
GND 2 2 2
L30ESDL5V0C3-2_SOT23-3 ACON_UARBG-4K1926
CONN@
WCM-2012HS-900T_4P ESD@
USB20_JUSB3_P2 4 3 USB20_JUSB3_P2_R
<12> USB20_JUSB3_P2 4 3
1
USB20_JUSB3_N2 1 2 USB20_JUSB3_N2_R
<12> USB20_JUSB3_N2 1 2 Place close to JUSB3
LI7
EMI@
C C
+5VALW
1 1 1
CI21 CI31 CI30
47U_0805_6.3V4Z
2
4.7U_0805_10V4Z
2 2
0.1U_0402_16V7K 2.0A +5V_USB_PWR4
B B
UI5
1 8 80mil
2
3
GND
VIN
VOUT
VOUT
7
6
USB connector4
VIN EPAD VOUT
USB_EN# 4
EN FLG
5 USB_OC1#
USB_OC1# <12> USB20 port3
1 1
CI25 CI32
9
AP2301MPG-13_MSOP8
0.1U_0402_16V7K
0.1U_0402_16V7K
2 2 +5V_USB_PWR4
WCM-2012HS-900T_4P JDB
USB20_USBDB_P3 4 3 USB20_USBDB_P3_R 1
<12> USB20_USBDB_P3 4 3 1
2
3 2
USB20_USBDB_N3 1 2 USB20_USBDB_N3_R USB20_USBDB_P3_R 4 3
<12> USB20_USBDB_N3 1 2 4
USB20_USBDB_N3_R 5
LI10 6 5 9
EMI@ 7 6 G1 10
8 7 G2
8
JESS_UCNR2210M008-0
CONN@
2nd: SP01001EX00
Main: SP01001AA00
Change CONN symbol for DFB
A A
0.047U_0402_16V4Z
0.1U_0402_10V7K
0.1U_0402_10V7K
4.7U_0603_6.3V6K
0.1U_0402_10V7K
@ CM47
1 1 2 2 1
CM40
CM46
CM48
CM43
2 2 1 1 2
D
Mini WLAN/WIMAX H=6.7 D
+3V_WLAN +3V_WLAN
JMINI +1.5VS
WLAN_WAKE# 1 2 +3VS
<30> WLAN_WAKE# 1 2
3 4
5 3 4 6 +3VS
5 6
1
WLAN_CLKREQ# 7 8
<9> WLAN_CLKREQ# 7 8
9 10 RM110
CLK_PCIE_WLAN# 11 9 10 12 QM30
<9> CLK_PCIE_WLAN# 10K_0402_5%
2
CLK_PCIE_WLAN 13 11 12 14 2N7002K_SOT23-3
<9> CLK_PCIE_WLAN 13 14
15 16
G
2
17 15 16 18
19 17 18 20 WLAN_RADIO_DIS#_R 1 3 WL_OFF#
19 20 WL_OFF# <11>
21 22 PLT_RST#
S
21 22 PLT_RST# <10,21,30,48,6>
23 24
<12> PCIE_PRX_WLANTX_N4 23 24
25 26
<12> PCIE_PRX_WLANTX_P4 25 26
27 28
29 27 28 30 DDR_XDP_WLAN_TP_SMBCLK
29 30 DDR_XDP_WLAN_TP_SMBCLK <17,18,19,27,6,9>
<12> PCIE_PTX_WLANRX_N4
CM49 1 2 0.1U_0402_10V7K PCIE_PTX_WLANRX_N4_C 31 32 DDR_XDP_WLAN_TP_SMBDAT
31 32 DDR_XDP_WLAN_TP_SMBDAT <17,18,19,27,6,9>
<12> PCIE_PTX_WLANRX_P4 CM44 1 2 0.1U_0402_10V7K PCIE_PTX_WLANRX_P4_C 33 34
35 33 34 36 USB20_MINI1_N4
35 36 USB20_MINI1_N4 <12>
37 38 USB20_MINI1_P4
37 38 USB20_MINI1_P4 <12>
39 40
41 39 40 42
43 41 42 44 WL_BT_LED#
45 43 44 46
47 45 46 48
EC_TX 49 47 48 50
<30> EC_TX 49 50
EC_RX 51 52
<30> EC_RX 51 52
+3VS
1 2 +3V_WLAN
BT_ON# RM13 2 1 1K_0402_1% 53 54
<11> BT_ON#
2
GND1 GND2 @
C C
RM11 RM25
CONCR_525B01BE17A 0_0805_1%
100K_0402_5% CONN@
1 2
1
@
RM26
0_0805_1%
+3VS +CPU_CORE
CM45
1 2
22U_0603_6.3V6M
ESD@
ESD solution
RD15 1 +5VALW
3
390_0402_5%
<30> BATT_LOW_LED# BATT_LOW_LED# 1 2 3
LED2
B 12-21C-T3D-CM2P1B18X-2C_WHITE RD17 B
390_0402_5% Amber
LED3
HT-210UD5-BP5_AMBER-WHITE
Wireless LED
1
<30> PWR_PWM_LED# 1 2 1 2 +5VALW
RD45 @ RD46
2
RD14 100K_0402_5% 100K_0402_5%
3
G
390_0402_5%
2
LED1
12-21C-T3D-CM2P1B18X-2C_WHITE WL_BT_LED# 3 1 1 2 1 2 +5VALW
D
RD18
3
QD18 680_0402_1%
2N7002K_SOT23-3 LED4
12-21C-T3D-CM2P1B18X-2C_WHITE
A A
+FAN_POWER
D D
40mil
FAN Control circuit
POWER/B
2.2U_0603_6.3V6K
1000P_0402_50V7K
1 1
CE22 CE23
+5VS
+3VALW 2 2 CE25
2.2U_0603_6.3V6K
JPWR 1 2
1
LID_SW# 2 1
<30> LID_SW# 2
ON/OFFBTN# 3 UE3
4 3 1 8
4 2 VEN GND 7
5 3 VIN GND 6
GND 6 EN_DFAN1 4 VO GND 5
GND <30> EN_DFAN1 VSET GND
HB_A090420-SAHR21 APE8873M SOP 8P
CONN@
+3VS
1
+FAN_POWER
40mil JFAN
2
+3VLP 1
2 1
ON/OFF switch <30> FAN_SPEED1
3 2
3
2
1 4
RE49 5 GND
C TOP Side 100K_0402_5% CE24 GND C
0.01U_0402_16V7K ACES_85204-0300N
SW1 2 CONN@
1
SMT1-05-A_4P
1 3
ON/OFFBTN# <30>
2 4 1
CE20
6
5
0.1U_0402_16V7K
2
Bottom Side
SW2
SMT1-05-A_4P
1 3
2 4
INT_KBD Connector
6
5
JKB CONN@
HB_A823020-SBHR21
2nd: SP01001BG00
Main: SP01000R910
Change CONN symbol for DFB
A A
1
2 VIN1 VOUT1 13 2 1
VIN1 VOUT1
C2307
10U_0805_10V4Z
C2308
10U_0603_6.3V6M
R2313 @ JUMP_43X79
1 2 82K_0402_5% 5VS_GATE 3 12 1 1 R10
<30,39,40> SUSP# ON1 CT1 100K_0402_5%
4 11
VBIAS GND
2
R2318 @ SUSP
1 2 470K_0402_5% 3VS_GATE 5 10 2 2
10mil ON2 CT2
1
6 9 3VS D
VIN2 VOUT2
1
1
C2322 C2309 +3VALW 7 8 SUSP# 2 Q8
VIN2 VOUT2
0.01U_0603_25V7K
0.01U_0603_25V7K
G 2N7002K_SOT23-3
15 +3VS S
2
1
GPAD
3
TPS22966DPUR_SON14_2X3 J511 R16
2 1 100K_0402_5%
2 1
C2324
10U_0603_6.3V6M
C2323
10U_0603_6.3V6M
@ JUMP_43X79
2
+3VALW +5VALW
1 1
SHORT DEFAULT @
2 2
C2316
10U_0603_6.3V6M
C2318
10U_0603_6.3V6M
C2306
10U_0603_6.3V6M
C2305
10U_0603_6.3V6M
1 1 1 1
2 2 2 2
2 2
+3VALW_PCH switch
3 3
+3VALW +3VALW_PCH
SHORT DEFAULT
U2304 J513
1 14 3VALW_PCH 2 1
2 VIN1 VOUT1 13 2 1
VIN1 VOUT1
C2310
10U_0805_10V4Z
C2312
10U_0603_6.3V6M
@ JUMP_43X79
PCH_PWR_EN 1 2 +3VALW_PCH_GATE 3 12 1 1
<30> PCH_PWR_EN ON1 CT1 +0.675VS +1.05VS
R416 4 11
0_0402_5% VBIAS GND @
1
5 10 2 2
10mil ON2 CT2 R2314 R2315
6 9 22_0603_5% 470_0603_5%
VIN2 VOUT2
1
C2314 7 8 @
VIN2 VOUT2
0.01U_0603_25V7K
1 2
1 2
15
2
GPAD
TPS22966DPUR_SON14_2X3 D D
2 SUSP 2 SUSP
G G
S Q2307 S Q2308
+3VALW 2N7002K_SOT23-3 2N7002K_SOT23-3
3
@
C2311
10U_0603_6.3V6M
C2313
10U_0603_6.3V6M
1 1
D D
SLG3NB244VTR TQFN 16P CLK GEN SLG3NB244VTR TQFN 16P CLK GEN
+RTCVCC
1
RG1 GCLK@
1
330_0402_5%
+1.8VGS +1.05VS +LAN_IO +3VLP +3VALW RG2 @
0_0402_5%
2
GCLKDIS@ 1 1 GCLK@ 1 GCLK@ 1 GCLK@ 1 GCLK@
2
Depop if GCLK
2.2U_0603_6.3V6K
CG1 CG2 CG3 CG4 CG10
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
CG6
GCLK@
GCLK@ 2
UG1 2
GCLK_VRTC 10 14 RTC_VOUT
VBAT VDD_RTC_OUT
Place close +3VLP 15 CPU_RTC 32.768k(P.8)
+V3.3A
to UG1.8 2 0_0402_5%
Place RG3 close to YC1
+3VALW VDD 9 PCH_RTCX1_R RG3 1 2 VGA 27M(P.29)
32kHz PCH_RTCX1 <8>
GCLK@
GCLKDIS@
Place RG7 close to YV1
+1.8VGS
11 12 VGA_X1_R RG4 1 2 10_0402_1% XTALIN_R 1 2
VDDIO_27M 27MHz XTALIN <49>
GCLKDIS@ RG7 0_0402_5%
+LAN_IO
8 6 LAN_X1_R RG5 1 2 33_0402_5% XTLI_R 1 2
VDDIO_25M_A 25MHz_A XTLI <21>
GCLK@ RG8 GCLK@ 0_0402_5%
+1.05VS
3 5 PCH_X1_R RG6 1 2 0_0402_5%
VDDIO_25M_B 25MHz_B XTAL24_IN <9>
GCLK@ 1 LAN 25M(P.21)
CLK_X1 1 GCLK@
16 XTAL_IN Place RG8 close to YL2
CLK_X2 CPU_CLK 24M(P.9) CG7
XTAL_OUT
GND1
GND2
GND3
GND4
CLK_X1 5P_0402_50V8C
CG8 GCLK@
Place RG6 close to YC2 2
2 1
SLG3NB274VTR_TQFN16_2X3 RG3, RG7,RG8, RG6 0ohm_0402
4
7
13
17
12P_0402_50V8J~D YG1 GCLK@
1 2
for isolated CLK tail
@
OSC GND
3 4
OSC GND
CG9 GCLK@ 25MHZ_10PF_7V25000014
2 1
XTALIN_R
12P_0402_50V8J~D CLK_X2
1
B @ B
CG11
5P_0402_50V8C
2
A A
SD034120280 12K_0402_1%
SD034100300 27K_0402_1%
SD034430280 33K_0402_1%
+3VALW
Board ID SD034430280 43K_0402_1%
Venus DIS@ SD034560280 56K_0402_1%
2
EMI@ UMA UMA@ RE3
LE1 +EC_VCCA
Ra 100K_0402_1% SD034750280 75K_0402_1%
+3VALW FBMA-L11-160808-800LMT_0603
SD034100380 100K_0402_1%
1
+3VALW 1 2 +EC_VCCA RE5 UMA@ AD_BID0
1 1 2 2
CE1 CE2 @EMI@ @EMI@ 1
2
0.1U_0402_10V7K 0.1U_0402_10V7K CE5 CE6 +3VLP CE7
D 1 D
1000P_0402_50V7K 1000P_0402_50V7K 0.1U_0402_10V7K Rb RE5
2 2 1 1 33K_0402_1% CE8
2 DIS@ 0.1U_0402_10V7K
75K_0402_1% 2
ECAGND
ECAGND <36>
1
SD034750280
111
125
+3VS
22
33
96
67
9
UE1
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/AVCC
EC_VDD0
TP_CLK 2 1
"KB_LED_PWM" for OAK 17 only 4.7K_0402_5% RE9
TP_DATA 2 1
1 21 KB_LED_PWM 4.7K_0402_5% RE10
GATEA20/GPIO00 GPIO0F KB_LED_PWM
KB_RST# 2 23 BEEP#
<11> KB_RST# KBRST#/GPIO01 BEEP#/GPIO10 BEEP# <22>
SERIRQ 3 26 USB_EN#
<11> SERIRQ SERIRQ GPIO12 USB_EN# <24,25>
LPC_LFRAME# 4 27 ACOFF
<9> LPC_LFRAME# LPC_FRAME# ACOFF/GPIO13 ACOFF <37>
LPC_LAD3 5
<9> LPC_LAD3 LPC_AD3
@EMI@ @EMI@ LPC_LAD2 7 PWM Output CE9 2 1 100P_0402_50V8J ECAGND
<9> LPC_LAD2 LPC_AD2
CE12 R2354 LPC_LAD1 8 63 BATT_TEMP
<9> LPC_LAD1 LPC_AD1 BATT_TEMP/GPIO38 BATT_TEMP <36,37>
0.1U_0402_10V7K 0_0402_5% LPC_LAD0 10 LPC & MISC 64
<9> LPC_LAD0 LPC_AD0 GPIO39
2 1 1 2 65 ADP_I
ADP_I/GPIO3A ADP_I <36,37>
CLK_PCI_LPC 12 AD Input 66 2 1 PCH_HOT#
<9> CLK_PCI_LPC CLK_PCI_EC GPIO3B PCH_HOT# <9>
PLT_RST# 13 75 AD_BID0
<10,21,26,48,6> PLT_RST# PCIRST#/GPIO05 GPIO42
+3VALW RE8 2 1 47K_0402_5% EC_RST# 37 76 PANEL_BKLEN PANEL_BKLEN <10> @
EC_SCI# 20 EC_RST# IMON/GPIO43 RE7
<11> EC_SCI# EC_SCII#/GPIO0E
CE11 2 1 0.1U_0402_10V7K TOUCH_RST 38 0_0402_5%
<31> TOUCH_RST GPIO1D 68 EN_INVPWR
DAC_BRIG/GPIO3C EN_INVPWR <31>
"TOUCH_RST" for OAK 15 only 70 EN_DFAN1
EN_DFAN1/GPIO3D EN_DFAN1 <27>
DA Output 71 EC_ENVDD
IREF/GPIO3E EC_ENVDD <31>
KSI0 55 72 LCD_TEST
KSI0/GPIO30 CHGVADJ/GPIO3F LCD_TEST <31>
KSI1 56
KSI[0..7] KSI2 57 KSI1/GPIO31
<27> KSI[0..7] KSI2/GPIO32
KSI3 58 83 EC_MUTE#
+3VALW KSI3/GPIO33 EC_MUTE#/GPIO4A EC_MUTE# <22>
KSO[0..16] KSI4 59 84 SIO_SLP_S4#
<27> KSO[0..16] KSI4/GPIO34 USB_EN#/GPIO4B SIO_SLP_S4# <10>
KSI5 60 85 IMVP_PWRGD VR_ON VR_ON
KSI5/GPIO35 CAP_INT#/GPIO4C IMVP_PWRGD <42>
C KSI6 61 PS2 Interface 86 SYS_PWROK C
KSI6/GPIO36 EAPD/GPIO4D SYS_PWROK <10,6>
KSI7 62 87 TP_CLK TP_CLK <27> 1 VCCST_PG_EC
1 2 LID_SW# KSO0 39 KSI7/GPIO37 TP_CLK/GPIO4E 88 TP_DATA CE34 ESD@
KSO0/GPIO20 TP_DATA/GPIO4F TP_DATA <27>
RE71 10K_0402_5% KSO1 40
KSO2 41 KSO1/GPIO21 0.1U_0402_10V7K
KSO2/GPIO22
2
1 2 WLAN_WAKE# KSO3 42 97 SUSACK# 2
KSO3/GPIO23 CPU1.5V_S3_GATE/GPXIOA00 SUSACK# <10>
RE70 10K_0402_5% KSO4 43 98 WOL_EN
2
KSO4/GPIO24 WOL_EN/GPXIOA01 WOL_EN <21>
KSO5 44 99 ME_EN Place CE34
KSO6 45 KSO5/GPIO25 Int. K/B ME_EN/GPXIOA02 109 VCIN0_PH
ME_EN <8>
KSO7 46 KSO6/GPIO26 Matrix VCIN0_PH/GPXIOD00 VCIN0_PH <36> between DE1 and RE12 DE1
+3VALW KSO7/GPIO27 SPI Device Interface
KSO8 47
KSO9 48 KSO8/GPIO28 119 EC_SPI_MOSI_1 ESD@
KSO9/GPIO29 SPIDI/GPIO5B EC_SPI_MOSI_1 <9>
1
RP36 KSO10 49 120 EC_SPI_MISO_1
KSO10/GPIO2A SPIDO/GPIO5C EC_SPI_MISO_1 <9>
5 4 EC_SMB_CK1 KSO11 50 SPI Flash ROM 126 EC_SPI_CLK_R EC_SPI_CLK_R <9>
1
6 3 EC_SMB_DA1 KSO12 51 KSO11/GPIO2B SPICLK/GPIO58 128 EC_SPI_CS0# L03ESDL5V0CG3-2_SOT-523-3
KSO12/GPIO2C SPICS#/GPIO5A EC_SPI_CS0# <9>
7 2 EC_SMB_CK2 KSO13 52
8 1 EC_SMB_DA2 KSO14 53 KSO13/GPIO2D
KSO15 54 KSO14/GPIO2E 73
2.2K_0804_8P4R_5% KSO16 81 KSO15/GPIO2F ENBKL/GPIO40 74 WLAN_WAKE#
1 2 82 KSO16/GPIO48 PECI_KB930/GPIO41 89
WLAN_WAKE# <26> Place DE1 close to UE1
<10> PCH_DPWROK SIO_SLP_S0# SIO_SLP_S0# <10>
RE37 KSO17/GPIO49 FSTCHG/GPIO50 90 BATT_CHG_LED#
BATT_CHG_LED#/GPIO52 BATT_CHG_LED# <26>
0_0402_5% 91 CAPS_LED
CAPS_LED#/GPIO53 CAPS_LED <27>
EC_SMB_CK1 77 GPIO 92 PWR_PWM_LED#
<36,37> EC_SMB_CK1 EC_SMB_CK1/GPIO44 PWR_LED#/GPIO54 PWR_PWM_LED# <26>
EC_SMB_DA1 78 93 BATT_LOW_LED# BATT_LOW_LED# <26>
<36,37> EC_SMB_DA1 EC_SMB_DA1/GPIO45 BATT_LOW_LED#/GPIO55
Reserve for ESD EC_SMB_CK2 79 SM Bus 95 SYSON
<19,49,9> EC_SMB_CK2 EC_SMB_CK2/GPIO46 SYSON/GPIO56 SYSON <41>
EC_SMB_DA2 80 121 VR_ON_EC 1 @ 2 VR_ON
<19,49,9> EC_SMB_DA2 EC_SMB_DA2/GPIO47 VR_ON/GPIO57 VR_ON <13,42>
127 CPU_DETECT# 1
PM_SLP_S4#/GPIO59 CPU_DETECT# <6>
2
2 1 SIO_SLP_S3# 1 2 +3VALW RE12 0_0402_5% @
RE11 100K_0402_5% RE1 CE26
CE27 ESD@ SIO_SLP_S3# 6 100 EC_RSMRST# 10K_0402_5% 0.1U_0402_10V7K
<10>SIO_SLP_S3# PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXIOA03 EC_RSMRST# <10> 2
0.1U_0402_10V7K SIO_SLP_S5# 14 101 EC_LID_OUT#
<10>SIO_SLP_S5# PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXIOA04 EC_LID_OUT# <11>
2
EC_SMI# 15 102 VCIN1_PH
<8> EC_SMI# VCIN1_PH <36>
1
2 1 SIO_SLP_S5# PS_ID 16 EC_SMI#/GPIO08 PROCHOT_IN/GPXIOA05 103 VCOUT1_PH RE2
<36> PS_ID GPIO0A H_PROCHOT#_EC/GPXIOA06 VCOUT1_PH <36>
CE_EN 17 104 VCOUT0_PH# 10K_0402_5%
<31> CE_EN GPIO0B VCOUT0_PH/GPXIOA07 VCOUT0_PH# <38>
CE28 ESD@ DGPU_PWROK 18 GPO 105 BKOFF#
<10,44> DGPU_PWROK GPIO0C BKOFF#/GPXIOA08 BKOFF# <19>
0.1U_0402_10V7K ENVDD_PCH 19 GPIO 106 PBTN_OUT#
<10,19> ENVDD_PCH PBTN_OUT# <10,6>
1
DBC_EN 25 GPIO0D PBTN_OUT#/GPXIOA09 107 2 1
Please close to EC <31> DBC_EN
28 EC_INVT_PWM/GPIO11 PCH_APWROK/GPXIOA10 108 RE36 43_0402_1%
PCH_PWR_EN <28>
B FAN_SPEED1 ACIN_65W B
<27> FAN_SPEED1 FAN_SPEED1/GPIO14 SA_PGOOD/GPXIOA11 ACIN_65W <49>
PCIE_WAKE# 29
<10,21> PCIE_WAKE# EC_PME#/GPIO15
<26> EC_TX EC_TX 30
2 1 PCH_PWROK EC_RX 31 EC_TX/GPIO16 110 ACIN ESD@
<26> EC_RX EC_RX/GPIO17 AC_IN/GPXIOD01 ACIN <10,36,37,49>
PCH_PWROK 32 112 EC_ON LID_SW# 1 2
<10> PCH_PWROK PCH_PWROK/GPIO18 EC_ON/GPXIOD02 EC_ON <38>
RE18 ME_SUS_PWR_ACK 34 114 ON/OFFBTN# CE30 0.1U_0402_10V7K
<10> ME_SUS_PWR_ACK SUSP_LED#/GPIO19 ON/OFF/GPXIOD03 ON/OFFBTN# <27>
10K_0402_5% RUNPWROK 36 GPI 115 LID_SW# ESD@
<6> RUNPWROK NUM_LED#/GPIO1A LID_SW#/GPXIOD04 LID_SW# <27>
116 SUSP# PCH_PWROK 1 2
SUSP#/GPXIOD05 SUSP# <28,39,40>
117 65W/90W# CE31 0.1U_0402_10V7K
GPXIOD06 65W#/90W <36>
118 PECI_KB9012 1 2 ESD@
PECI_KB9012/GPXIOD07
AGND/AGND PECI_EC <6>
+1.05V_PGOOD 122 SYS_PWROK 1 2
<40> +1.05V_PGOOD XCLKI/GPIO5D
123 124
GND/GND
GND/GND
GND/GND
GND/GND
69
<42> VR_HOT#
VR_HOT# 1 ME_FWP PCH has internal 20K PD. CE18
CE15
ACIN 2 1 100P_0402_50V8J
1
1
KB9012A4 SA00004OB30 @
2
UE2 RE326
P
2
G
2
A SN74LVC1G06DCKR_SC70-5
1 RE47 A
1
100K_0402_5%
CE19
47P_0402_50V8J
1
eDP@
EDP_HPD_PANEL RX53 1 2 0_0402_5% CE_EN_R
<19> EDP_HPD_PANEL
Close to JLVDS
For eDP co-layout
LCD PWR CTRL LVDS Connector
D D
JLVDS
<19> LVDS_A0- LVDS_A0- 1
LVDS_A0+ 2 1 41
+LCDVDD +LCDVDD_CONN DX1 <19> LVDS_A0+ 2 G1
3 42
+3VS 2 1 4 3 G2 43
W=60mils <19> TL_BKOFF# DISPOFF# <19> LVDS_A1- LVDS_A1-
5 4 G3 44
UX1 <19> LVDS_A1+ LVDS_A1+
5 G4
1
W=60mils 1 1 2 6 45
5 VOUT FBMA-L11-201209-221LMA30T_0805 RB751V-40_SOD323-2 LVDS_A2- 7 6 G5 46
VIN 10K_0402_5% <19> LVDS_A2- 7 G6
LX1
<19> LVDS_A2+ LVDS_A2+ 8
RX9 8
0.1U_0402_10V7K
CX11
4.7U_0805_10V4Z
CX8
1 2 9
4 GND LVDS_ACLK- 10 9
1 1 1 <19> LVDS_ACLK-
2
SS 10
0.1U_0402_10V7K
CX9
CX7 @ <19> LVDS_ACLK+ LVDS_ACLK+ 11
4.7U_0805_10V4Z 3 12 11
2 EN LVDS_B0- 13 12
<19> LVDS_B0- 13
2 APL3512ABI-TRG_SOT23-5 2 2 LVDS_B0+ 14
<19> LVDS_B0+ 14
15
WCM-2012HS-900T_4P LVDS_B1- 16 15
<19> LVDS_B1- 16
4 3 USB20_CAM_P7_R <19> LVDS_B1+ LVDS_B1+ 17
<12> USB20_CAM_P7 4 3 17
2 1 ENVDD_R CE_EN_R 18
<19> TL_ENVDD 18
RX7 0_0402_5% <19> LVDS_B2- LVDS_B2- 19
2 1 1 2 USB20_CAM_N7_R LVDS_B2+ 20 19
<30> EC_ENVDD <12> USB20_CAM_N7 1 2 <19> LVDS_B2+ 20
RX8 @ 0_0402_5% DBC_EN_R 21
LX6 LVDS_BCLK- 22 21
Css Tss <19> LVDS_BCLK- 22
EMI@ <19> LVDS_BCLK+ LVDS_BCLK+ 23
24 23
0.1uF 100mS 24
1 2 W=60mils 25
10nF 10mS SS table RX22 0_0402_5%
+LCDVDD_CONN
+3VS 26
27
25
26
@EMI@ USB20_CAM_P7_R
1 2 USB20_CAM_N7_R 28 27
1nF 1mS 28
RX21 0_0402_5% +3VS_CAM
29
@EMI@ MIC_CLK 30 29
Open or 1mS <22> MIC_CLK 30
tied to 31
MIC_DATA 32 31
VIN <22> MIC_DATA 32
<30> LCD_TEST LCD_TEST 33
34 33
<19> EDID_CLK 34
C <19> EDID_DATA 35 C
36 35
CE_EN_R only for reserve. <19> TL_INVT_PWM
DISPOFF# 37
38
36
37
1
@ 39 38
+INV_PWR_SRC 39
RX18 RX26 40
0_0402_5% 100K_0402_5% 40
1 2
W=60mils STARC_107K40-000001-G2
CE_EN CE_EN_R
<30> CE_EN
CONN@
2
DBC_EN 1 2 DBC_EN_R
<30> DBC_EN
@
1
RX19
0_0402_1% @ @
RX20 RX23
0_0402_1% 0_0402_5%
2
2
+3VS +LCDVDD
0.1U_0402_10V7K
0.1U_0402_10V7K
10U_0805_10V6K
1 1 1
CX1
CX2
CX3
QX2
60mil SI3457CDV-T1-GE3_TSOP6 60mil
+INV_PWR_SRC 2 2 2
+INV_PWR_SRC
B+ 6
5
2
4 1
S
100K_0402_5%
RX2
1
CX5
G
1
0.1U_0603_25V7K
3
2
2
B B
PWR_SRC_ON
1
RX3
100K_0402_5%
D +5VS +5VS_TOUCH
<30> EN_INVPWR 2 QX1
G 2N7002KW_SOT323-3 1 2 +5VS_TOUCH
S @
3
RX28
0_0603_1% 1 2
CX6
0.1U_0402_16V7K
JTOUCH
ACES_88460-00601-P01
1
USB20_TOUCH_N5 2 1
+5VS_TOUCH <12> USB20_TOUCH_N5 2
USB20_TOUCH_P5 3
Webcam PWR CTRL <12> USB20_TOUCH_P5
4
5
3
4 7
1 2 TOUCH_RST_R 6 5 G1 8
6 G2
RX24 CONN@
+3VS +3VS_CAM 100K_0402_5%
1 2
<30> TOUCH_RST SP010013W00
1 2 RX1
A 0_0402_5% A
@
RX27
0_0603_1% OAK 15 only
+5V_HDD
1000P_0402_50V7K
0.1U_0402_25V6K
10U_0805_10V6K
1 1 1
CS5 CS6 CS7
2 2
2 2 2
1000P_0402_50V7K
0.1U_0402_25V6K
10U_0805_10V6K
+5VS
QS2 +5VS_ODD 1 1 1
D
CS11
CS10
CS12
6
S
5 4
1U_0402_6.3V6K
3 3
2 2 2 2
1
1
CS13 SI3456BDV-T1-E3 1N TSOP6
G
3
B+ 2 JODD
1
GND
2
ODD_EN 7 B+
GND
8
1
<8> ODD_DETECT# 9 DP
D 1
2 QS3 CS16 10 +5V 14
<11> ODD_EN# +5V GND
G 2N7002KW_SOT323-3 0.1U_0603_25V7K 11 15
<11> ODD_DA# MD GND
12 16
S 2 13 GND NPTH1 17
GND NPTH2
3
1
CS17 SANTA_202801-1
0.1U_0402_25V6K CONN@
ESD@
2
4 4
D D
Screw Hole
H2 H4 H5 H8 H9 H11 H12
H_2P8 H_2P8 H_2P8 H_2P8 H_2P8 H_2P8 H_2P8
@ @ @ @ @ @ @
1
1
C C
H16 H17 H18 H35
H_2P8 H_2P8 H_3P3 H_3P7X3P2N
@ @ @ @
1
1
H31 H32 H33 H34
H_3P7 H_3P7 H_3P7 H_3P7
@ @ @ @ CPU bracket
1
H6 H7
H_3P3 H_3P3
@ @ VGA stand-off
1
H10
H_3P3
@ FAN stand-off
1
A A
D D
3
10
11
12
13
14
C 15 C
16
17
18
19
20
21
22
23
24
25
26
27
B B
28
29
30
31
32
33
34
35
36
37
38
A A
39
40
41
41
D D
42
43
44
45
46
47
48
49
50
51
52
53
C 54 C
B B
A A
PL1 EMI@
VIN PR4 PSID@
C8B BPH 853025_2P 33_0402_5%
ADPIN 1 2 1 3 PSID-3 1 2 PS_ID <30>
S
PQ6 PSID@
FDV301N_G 1N SOT23-3
1000P_0402_50V7K
1000P_0402_50V7K
G
2
1
PJPDC
100K_0402_1%
100P_0402_50V8J
100P_0402_50V8J
PR8
2
1 EMI@ PL4 PSID@ PR3 PSID@
1 2 C8B BPH 853025_2P 2 1
PC1
PC2
PC3
PC4
PR6
PSID-2
PSID@
+5VALW 2.2K_0402_5%
2 3 1 2
3
2
4
2
4 5 10K_0402_1%
EMI@
EMI@
EMI@
EMI@
5 +3VALW
1
1 C 1
15K_0402_1%
B
2
GND E
3
ACES_50299-00501-003
PR9
PSID@
CONN@
PL2
C8B BPH 853025_2P
1
PSID 1 2
EMI@
BATT+ BATT++
EMI@
BATT+
PL3
SMB3025500YA_2P
1 2 BATT++
1
1000P_0402_50V7K
0.01U_0402_25V7K
1
PC8
PC7
2
2
EMI@
EMI@
PD1
EMI@
4 3
V I/O V I/O
5 2
SMART V BUS Ground
Battery: 6 1
PBATT V I/O V I/O BATT_TEMP <30,37>
01.GND1 1
02.GND2 1 2 AZC099-04S.R7G_SOT23
2
2 3 BAT_ALERT PR15 PR16
2
2
PR24
1
12.1K_0402_1%
6
PR30
2
1
160K_0402_1%
L2N7002DW1T1G_SC88-6
1
@.1U_0402_16V7K
2
1
PC15
2
3 3
PR26
1
D
2
2
PC13
499K_0402_1% PH1
1
2
G 65W#/90W <30> VCOUT1_PH <30> 100K_0402_1%_TSM0B104F4251RZ
1
S
3
3.3K_1206_5%~D
keep @ in BOM since battery can not till SW PROCHOT# is issued by EC
1
be removed by end user
PR5
H_PROCHOT#
VIN +3VALW PR7
2
ACIN <10,30,37,49>
10K_0402_1%
1
3 2
H_PROCHOT# 1M_0402_1%
PR28
PR31 PC16 2 1
+RTCBATT
L2N7002DW1T1G_SC88-6
- +
2
.1U_0402_16V7K
PQ1B
L2N7002DW1T1G_SC88-6
5
PQ2A
1M_0402_1%
3
3 2
PC14 1 2 2 PR1
6
.1U_0402_16V7K
L2N7002DW1T1G_SC88-6
L2N7002DW1T1G_SC88-6
200K_0402_1%
PQ3B
PQ2B
100K_0402_1%
L2N7002DW1T1G_SC88-6
1
BATT_PRS 1 2 5
PQ1A
PR10 JRTC
2
5 2 LOTES_AAA-BAT-054-K01
PR29
PC5
4
1
PR32
1M_0402_1%
2
0.1U_0402_25V6
2
4 4
2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR_DCIN/BATT CONN/OTP
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9981P
Date: Saturday, March 09, 2013 Sheet 36 of 55
A B C D
A B C D
Iada=0~3.33A(65W)
Iada=0~4.62A(90W)
CHG_B+
ADP_I = 40*Iadapter*Rsense
1
VIN PQ701 PR702 EMI@ 1
CSIN
2200P_0402_25V7K
0.1U_0603_25V7K
EMI@
PC706 @EMI@
10U_0805_25V6K
10U_0805_25V6K
4
0.1U_0402_25V6
1
3.3K_1206_5%~D
CSIP
100U_25V_M
0.1U_0603_25V7K
1
1
PR721 + PR706
PC702
PC704
PC703
PC724
4.7_0402_1%
4.02K_0402_1%
PR720
PC701
PR701
PC705
4.02K_0402_1%
/BATDRV 2 1
2
2
VIN
2
2
PR717 PR704
0_0402_5% 0_0402_5%
1
1U_0603_25V6K
1
2 PQ706
<30> ACOFF
G 2N7002KW_SOT323-3
0.1U_0402_25V6
1
S
3
PR703
2
4.02K_0402_1% PR705
For DT Mode
2
10_1206_5%
PC707
PC708
2
1 2 PC717
1
0.1U_0402_25V6 PC709
1
1 2 1U_0603_10V6K
1U_0603_25V6K
1
1
PC710
PD701
2
BAT54HT1G_SOD323-2~D B+
2 1
1
PU701
MDU1516URH_POWERDFN56-8-5
MDU1516URH_POWERDFN56-8-5
PC718
ACN
ACP
2 2
VCC 20 16 REGN 10U_0805_25V5K~D
VCC REGN 1 2
PR709 PC721
5
2.2_0603_5% 0.047U_0603_25V7K PC714
3 17 1 2 1 2 Near PL701
PQ703
PQ704
CMSRC BST BST_CHGA 10U_0805_25V5K~D
VIN CMSRC BTST 1 2
324K_0402_1%
PC711
2
0.01UF_0402_25V7K @
1 2 4 18 4 4
PR723
ACDRV DH_CHG
ACDRV HIDRV
PR711
49.9K_0402_1%
1
3
2
1
3
2
1
ACDET PHASE PL701 0.01_1206_1%
REGN
2.2UH_FDVE1040-H-2R2M-P3_14.2A_20% +VCHGR
@ PR715 0_0402_5%~D 1 2 1 4
<30,36> EC_SMB_DA1 1 2 8 15 DL_CHG
SDA LODRV 2 3
1
1
100K_0402_1%
680P_0402_50V7K
5
@ PR714 0_0402_5%~D
PR707
SIRA14DP-T1GE3_POWERPAK-SO8-5
PC715
@EMI@
<30,36> EC_SMB_CK1 1 2 9 14
PQ705
2
SCL GND
10U_0805_25V5K~D
10U_0805_25V5K~D
10U_0805_25V5K~D
ACIN <10,30,36,49>
2
1
PR708 0_0402_5%
PC716
PC712
PC713
ACIN 5 13 1 2 4
ACOK SRP
1
2
@
158K_0402_1%
1
PR710 0_0402_5%
4.7_1206_5%
7 12 1 2
PR712
PR722
3
2
1
IOUT SRN
@EMI@
2
2
REGN 10 11 /BATDRV PC722
CELL /BATDRV 1 2
TP
BQ24717 0.1U_0402_25V6 @
1
21
PC719
10K_0402_1%
3
1 2 3
PR713
<30,36> ADP_I
0.1U_0402_25V6
2
PC720
100P_0402_50V8J
1
PC723
1
D
2 1 2
2N7002KW_SOT323-3
<30,36> BATT_TEMP
G
S
3
PQ708
0.01U_0402_25V7K
100K_0402_1%
2
PR724
(pulse)
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR_CHARGER
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9981P
Date: Saturday, March 09, 2013 Sheet 37 of 55
A B C D
A B C D E
1 1
+3VLP
PC109
1U_0603_10V6K
1 2
PR107 PR106
10K_0402_1% 10K_0402_1%
1 2 1 2
3/5V_B+
2 PR105 2
EMI@
1
PL102 1 2
1UH_PCMB053T-1R0MS_7A_20% PR108
B+ 1 2 3/5V_B+ 90.9K_0402_1%
10U_0805_25V6K
84.5K_0402_1%
PC112
FB_3V
FB_5V
2
CS2
CS1
2200P_0402_50V7K
10U_0805_25V6K
0.1U_0402_25V6
1
2
@EMI@ PC113
EMI@ PC114
PC115
MDV1528URH 1N PDFN33-8
5
will pull high on VS
2
MDV1528URH 1N PDFN33-8
CS2
VFB2
VREG3
VFB1
CS1
transfer circuit PAD
21
3V_EN 6
EN2 20
PQ101
PQ103
5V_EN
4 EN1 PR114 @ 4
7 200_0402_5%
PGOOD 19 1 2
VCLK
LX_3V 8 TPS51225CRUKR_QFN20_3X3
SW2
1
2
3
3
2
1
PL100 PC104 PR103 18 LX_5V
2.2UH_PCMB063T-2R2MS_8A_20% 0.1U_0402_10V7K 2.2_0402_5% SW1 PR111 PC110 PL101
2 1 1 2 1 2 BST_3V 9 2.2_0402_5% 0.1U_0402_10V7K 2.2UH_PCMB063T-2R2MS_8A_20%
+3VALWP VBST2 17 BST_5V 1 2 1 2 1 2
VBST1 +5VALWP
UG_3V 10
DRVH2
1
16 UG_5V
4.7_1206_5%
680P_0603_50V8J 4.7_1206_5%
VREG5
DRVL2
DRVL1
1
DRVH1
@EMI@ PR113
@EMI@ PR112
VO1
5
5
VIN
MDV1525URH 1N PDFN33-8
MDV1525URH 1N PDFN33-8
220U_6.3V_M
220U_6.3V_M
ESR=17m ohm
1 1
ESR=17m ohm
11
12
13
14
15
2
+
PQ102
PQ104
+
PC101
PC107
4 LG_3V LG_5V 4
680P_0603_50V8J
1
1
2 2
@EMI@ PC103
@EMI@ PC111
3 +5VALWP 3
2
1
2
3
3
2
1
2
3/5V_B+
VL
1U_0603_25V6K
1U_0603_10V6K
1
1
@ PC105
PC106
Change to 4.7u for TPS51285
@ PR100 0_0402_5%~D
3V_EN 1 2
3VALWP
TDC 5.95A @ PR101 0_0402_5%~D
Peak Current 8.5A 5V_EN 1 2
1 2 1 2
1
PC100
3
PD101
EMI@
Security Classification Compal Secret Data Compal Electronics, Inc.
1
L03ESDL5V0CG3-2_SOT-523-3
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR_3.3VALWP/5VALWP
Place PD101 close to PU100 Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9981P
Date: Saturday, March 09, 2013 Sheet 38 of 55
A B C D E
A B C D
PJP401 @
1 2
+1.5VSP 1 2 +1.5VS
JUMP_43X79
PR401
0_0402_5%
+1.5VSP_ON 1 2 SUSP#
SUSP# <28,30,40>
0.1U_0402_16V7K
1
PC403
1
1 PR404 1
1M_0402_5%
@
Note:Iload(max)=2.5A
2
PU400
9
1 PGND 8
FB SGND
PJP400 @ 2 7 PL400
PG EN 1UH_PH041H-1R0MS_3.8A_20%
LX_1.5VSP
+3VALW 1
1 2
2 3
IN LX
6 1 2
+1.5VSP
1
4 5
68P_0402_50V8J
1
1
JUMP_43X79 PGND NC
PC405
4.7_0603_5%
1
22U_0805_6.3VAM
@EMI@ PR405
PC404
22U_0805_6.3VAM
22U_0805_6.3VAM
2
1
SY8003DFC_DFN8_2X2 PR403
15K_0402_1% Rup
PC402
PC400
2
2
2
FB_1.5VSP
1
1
FB=0.6V
680P_0402_50V7K
PR402
@EMI@ PC401
Note:Iload(max)=3A Rdown
10K_0402_1%
2
2 2
PJP601
@
1 2
+1.8VSP 1 2 +1.8VS
JUMP_43X79
PR601 VGA@
0_0402_5%
+1.8VSP_ON 1 2 PXS_PWREN PXS_PWREN <10,11,43,44,50>
0.1U_0402_16V7K
1
PC603
1
PR604 VGA@
1M_0402_5%
@
Note:Iload(max)=2.5A
2
VGA@
2
PU600
9
1 PGND 8
FB SGND
PJP600 @ 2 7 PL600
PG EN 1UH_PH041H-1R0MS_3.8A_20%
1 2 3 6 LX_1.8VSP 1 2
+3VALW 1 2 IN LX +1.8VSP
1
4 5
VGA@
68P_0402_50V8J
JUMP_43X79 PGND NC
1
PC605
4.7_0603_5%
1
22U_0805_6.3VAM VGA@
@EMI@ PR605
PC604
VGA@
22U_0805_6.3VAM
22U_0805_6.3VAM
2
1
VGA@ SY8003DFC_DFN8_2X2 PR603
20K_0402_1%
Rup
PC602
PC600
2
2
2
FB_1.8VSP
3 3
VGA@
VGA@
1
1
FB=0.6V VGA@
680P_0402_50V7K
PR602
@EMI@ PC601
Note:Iload(max)=3A Rdown
10K_0402_1%
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR_1.5VSP / 1.8VSP
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9981P
Date: Saturday, March 09, 2013 Sheet 39 of 55
A B C D
5 4 3 2 1
D D
1
@ PC300
1M_0402_1%
0.22U_0402_10V6K
2
PR301
2
@EMI@ PR302 @EMI@ PC301
4.7_1206_5% 680P_0603_50V7K
EMI@ PL302 1 2SNB_1.05V 1 2 +1.05VSP @ PJP300
SUPPRE_ FBMA-L11-453215-800LMA90T_1812 PU300 1 2 +1.05VS
1 2
B+ 1 2 B+_1.05V 8
IN EN
1 PR303 PC302
0_0603_5% 0.1U_0603_25V7K JUMP_43X118
10U_0805_25V6K
10U_0805_25V6K
6 BST_1.05V 1 2 1 2 PL301
2200P_0402_50V7K
0.1U_0402_25V6
BS
1
1
@EMI@ PC304
PC305
PC306
1UH_PCMB063T-1R0MS_12A_20%
LDO_3V 9 10 1 2
+1.05VSP
EMI@ PC303
LX_1.05V
GND LX
2
15K_0402_1%
47U_0805_6.3V6M
47U_0805_6.3V6M
22U_0805_6.3VAM
22U_0805_6.3VAM
1
330P_0402_50V7K
1
1
4
PR305
FB
PC307
PC308
PC309
PC310
PC311
@ PR304
0_0402_5% ILMT_1.05V 3 7 Rup
+3VALW
2
ILMT BYP
4.7U_0603_6.3V6K
2
2
ILMT_1.05V
+3VS 1 2 +1.05V_PGOOD 2 5 LDO_3V
4.7U_0603_6.3V6K
PG LDO
1
PC313
PR308
1
PC312
10K_0402_5% SY8206DQNC_QFN10_3X3
FB = 0.6V
2
1
@ PR306
2
0_0402_5% PR307
Rdown
2
20K_0402_1%
2
<30> +1.05V_PGOOD
Pin 7 BYP is for CS.
B The current limit is set to 6A, 8A or 12A when this pin Common NB can delete +3VALW and PC313 B
is pull low, floating or pull high
VFB=0.6V
Vout=0.6V* (1+Rup/Rdown)
Vout=1.05V
+1.05VSP
TDC 5A
Peak Current 6.6A
OCP current 8A
A A
D D
EMI@
0.675Volt +/- 5%
PL201
SUPPRE_ FBMA-L11-453215-800LMA90T_1812
TDC 0.7A
B+ 1 2 1.35V_B+ PR200 Peak Current 1A
2.2_0603_5%
BST_1.35V 1 2 BOOT_1.35V
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
+1.35VP
1
PC208
PC201
PC206
PC212
DH_1.35V +0.675VSP
2
EMI@
@EMI@
SW_1.35V
10U_0805_6.3V6K
10U_0805_6.3V6K
1
1
PC200
PC205
PC211
5
0.1U_0603_25V7K
16
17
18
19
20
2
PU200
2
VLDOIN
BOOT
VTT
PHASE
UGATE
21
PQ200 PAD
AON7408L 4 DL_1.35V 15 1
LGATE VTTGND
14 2
PL200 PR205 PGND VTTSNS
1
2
3
1UH_PCMB063T-1R0MS_12A_20% 11.8K_0402_1%
+1.35VP 1 2 1 2
CS_1.35V 13
CS GND
3
PC204 RT8207MZQW_WQFN20_3X3
1
1U_0603_10V6K
5
@EMI@ PC207 1 2 12 4 VTTREF_1.35V
680P_0402_50V7K PR206 VDDP VTTREF
2
5.1_0603_5%
330U_2.5V_M
C 1 C
1 2 VDD_1.35V 11 5
+5VALW +1.35VP
1
VDD VDDQ
PGOOD
+ PQ201
PC213
1
AON7702A 4 PC210
TON
1
0.033U_0402_16V7K
FB
S5
S3
2
2 @EMI@ PR203 PC209
4.7_1206_5% 1U_0603_10V6K +5VALW
10
6
2
1
2
3
FB_1.35V
EN_0.675VSP
TON_1.35V
EN_1.35V
PR207
54.9K_0402_1%
PR208 1 2 +1.35VP
1M_0402_1%
1.35V_B+ 1 2
1.35VP
1
TDC 6A
Peak Current 8A PR201
0_0402_5%
PR204
68.1K_0402_1%
OCP current 10A <30> SYSON
1 2
2
1
@ PC202
0.1U_0402_10V7K
2
PR202
0_0402_5%
1 2
<17> 0.675V_DDR_VTT_ON
1
@ PJP200
@ PC203 +1.35VP 1 2 +1.35V
0.1U_0402_10V7K 1 2
2
JUMP_43X118
B @ PJP201 B
1 2
1 2
JUMP_43X118
@ PJP203
2 1
+0.675VSP 2 1 +0.675VS
JUMP_43X39
A A
VREF_CPU
IMON_CPU
499K_0402_1%
9.31K_0402_1%
2
2
75_0402_1%
2
2
@ @
75_0402_1%
PR514
PR507
PR504
PR502
523K_0402_1%
4700P_0603_50V7K
1
PH502
PC508
PR501
100K_0402_1%_TSM0B104F4251RZ
Near PU502.
1
B value:4250K
1
1
EMI Part (47.1)
2
OCP_CPU B-RAMP O-USR
150K_0402_1%
75K_0402_1%
150K_0402_1%
F-IMAX
2
75K_0402_1%
1000P_0402_50V7K
PL501 EMI@ B+
PR503
PR509
PR505
PR506
10K_0402_5%~D
2
SUPPRE_ FBMA-L11-453215-800LMA90T_1812
39K_0402_5%
D D
2
1
+VCC_PWR_SRC 1 2
PR512
PR513
PC509
1
2
1
EMI@
PC519 @EMI@
1
10U_0805_25V6K
10U_0805_25V6K
2200P_0402_25V7K
0.1U_0402_25V6
100U_25V_M
100U_25V_M
1 1
1
+ +
PC517
PC518
PC521
PC515
PC516
2
2
2 2
THERM_CPU
PR522
SLEWA_CPU 0_0402_5%
VR_ENABLE 1 2
VR_ON <13,30>
PR508
CPU_CORE
1
+VCC_PWR_SRC
10K_0402_5%~D
1 2 VBAT_CPU
PC522 @ TDC 10A
1U_0402_6.3VX5R Peak Current 32A
2
16
15
14
13
12
11
10
9
OCP current 40A
IMON
OCP-I
O-USR
THERM
VBAT
B-RAMP
F-IMAX
SLEWA
Load line -2mV/A
CSP1_CPU 17 8 PR535 @
CSP1 VR_ON PU502
0_0402_5%~D
CSN1_CPU 18 7 SKIP# 1 2 SKIP#1 9 PL502
CSN1 SKIP# PWM1 8 PGND2 0.22UH_PCMB104T-R22MS_35A_20%
19 PU501 6 PWM1 PC502 1 2 7 PWM 4 SW_CPU2 1 4
CSN2 TPS51622RSM_QFN32_4X4 PWM1 BOOT VSW 3
C PC501 0.1U_0402_25V6 PGND1 C
20 5 1000P_0402_50V7K 2 1 6 2 2 3
CSP2 PWM2 1 2 PR536 2.2_0603_5% 5 BOOT_R VDD
VIN SKIP#
1 +CPU_CORE
1
21 4
680P_0402_50V7K
+3VS
1
PU3 N/C @
PC520
22 3 PR510 TI recommend 1nF CSD97374CQ4M_SON8_3P5X4P5
+3VS
2
N/C PGOOD
75_0402_1%
Check are there a pair 100Ω 23 2 SKIP#1
GFB VDD
VR_HOT#
1
at HW side and close to CPU.
ALERT#
DROOP
24 1
4.7_1206_5%
@EMI@
+5VS
COMP
VFB VDIO
VREF
<13,15> VSSSENSE
VCLK
PR534
GND
PAD
V5A
1
<13> VCCSENSE PC503
1U_0603_10V6K
25
26
27
28
29
30
31
32
33
2
@EMI@
PR540
2 @ 1 IMVP_PWRGD <30>
DROOP_CPU 0_0402_5%
V5A_CPU
COMP_CPU H_VR_READY <13>
PR518
PR524
@ PC513 PR531 PR516 2.32K_0402_1%
390P_0402_50V7K 3.65K_0402_1% 2 1 2 1
2 1 2 1
+3VS +3VS 1 2
VREF_CPU CSP1_CPU
VR_SVID_ALRT#
1_0603_5%
10K_0402_1%~D
VR_SVID_DAT
VR_SVID_CLK
PR532
1
10K_0402_1% PH501
1
2
PR529 PC514
2
1
5.76K_0402_1% 1500P_0402_50V7K
Near PL502.
2
PR517
2 1 1 2 PC510 PC511 16.5K_0402_1%
0.082U_0402_16V7K 0.082U_0402_16V7K
2
PR519
10_0603_1%
1 2
B +5VS PR515
B
3.01K_0402_1%
47P_0402_50V8J
1
2
2
PC505
PC506
1U_0603_10V6K
2
CSN1_CPU
1
+1.05VS
1 2
PR533
1
1
56_0402_1%
PR526 PR528 PR530 PC512
<30> VR_HOT# 54.9_0402_1% 75_0402_5% 130_0402_1% .1U_0402_16V7K
2
@ @
2
<13> VR_SVID_CLK
<13> VR_SVID_ALRT#
<13> VR_SVID_DAT
A A
VGA@_EMI@ PL1100
HCB2012KF-121T50_0805
+1.2VSP_B+ 1 2
B+
2200P_0402_50V7K
10U_0805_25V6K
0.1U_0402_25V6
1
1
@EMI@ PC1100
VGA@_EMI@ PC1101
VGA@ PC1102
+3VS
2
TDC=9A
5
1
D Peak Current=13A @ 1
@ PJP1100
2
D
+1.35VGPUP 1 2 +1.35VS_VGA
OCP=16A PR1110 VGA@
100K_0402_5% PQ1100 JUMP_43X118
4 AON7408L @ PJP1101
2
VGA@ VGA@ 1 2
PR1101 PC1103 1 2
PU1100 VGA@ 2.2_0603_5% 0.1U_0603_25V7K JUMP_43X118
PR1102 VGA@ 1 10 BST_+1.2VSP 1 2 1 2
3
2
1
154K_0402_1% PGOOD VBST
PR1103 VGA@ 1 2 TRIP_+1.2VSP 2 9 UG_+1.2VSP VGA@ PL1101
0_0402_5%~D TRIP DRVH 1UH_PCMB063T-1R0MS_12A_20%
PXS_PWREN 1 2 EN_+1.2VSP 3 8 SW_+1.2VSP 1 2
EN SW +1.35VGPUP
FB_+1.2VSP 4 7
VFB V5IN +5VALW
1
0.1U_0402_16V7K
RF_+1.2VSP 5 6 LG_+1.2VSP
TST DRVL
1
@ PC1104
PR1104 @EMI@
330U_2.5V_M
1
1
11 VGA@ 4.7_1206_5%
TP
1
VGA@ PQ1101 +
PC1108
2
2
4
VGA@
PR1105 VGA@ TPS51212DSCR_SON10_3X3 PC1105 AON7702A
470K_0402_1% 1U_0603_10V6K
1
PC1106 @EMI@ 2
2
680P_0402_50V7K
3
2
1
2
C C
PR1107 VGA@
9.09K_0402_1%
1 2
1
PR1108 VGA@
10K_0402_1%
VDDCI_VID (GPIO_6)
2
VGA@ PR1206
0_0402_5%
1 2 PXS_PWREN PXS_PWREN <10,11,39,44,50>
High 0.95V
1
@ PC1200
1M_0402_1%
0.22U_0402_10V6K Low 0.9V
2
PR1201
VGA@
2
+VDDCIP @ PJP1200 +VDDCI
@EMI@ PR1207 @EMI@ PC1212 1 2
4.7_1206_5% 680P_0603_50V7K 1 2
VGA@_EMI@ PL1201 1 2SNB_1.05V 1 2 JUMP_43X118
B B
SUPPRE_ FBMA-L11-453215-800LMA90T_1812 PU1200 VGA@ VGA@
B+ 1 2 B+_VDDCI 8
IN EN
1 PR1200 PC1210
0_0603_5% 0.1U_0603_25V7K
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
BS
1
1
@EMI@ PC1203
VGA@ PC1202
VGA@ PC1204
1UH_PCMB063T-1R0MS_12A_20%
LDO_3V_VDDCI 9 10 1 2
+VDDCIP
VGA@_EMI@ PC1209
LX_VDDCI
GND LX
2
47U_0805_6.3V6M
47U_0805_6.3V6M
22U_0805_6.3VAM
22U_0805_6.3VAM
1
10_0402_5%
1
1
4
FB
VGA@
VGA@ PR1203
PR1208
VGA@ PC1211
VGA@ PC1207
VGA@ PC1201
VGA@ PC1206
0_0402_5% ILMT_VDDCI 3 7
Rup +VDDCIP
+3VALW
2
ILMT BYP VGA@ PR1209 TDC 7A
4.7U_0603_6.3V6K
2
2
PG LDO
1
SY8208DQNC_QFN10_3X3
VGA@ PC1213
0_0402_5% 1 2 1 2
1
VDDCI_SEN <52>
2
1
0_0402_5%~D 10K_0402_5%
Pin 7 BYP is for CS. VGA@ PR1212 VGA@
Rdown
1
PR1204 D 10K_0402_5%
2
The current limit is set to 8A, 12A or 16A when this pin Common NB can delete +3VALW and PC1205 20K_0402_1% 2 2 1
G GPU_GPIO6 <49>
2
is pull low, floating or pull high
1
S
1
PQ1201 VGA@
VFB=0.6V 2N7002W-T/R7_SOT323-3 @ PC1214 PR1214 @
A A
4700P_0402_25V7K 100K_0402_5%
Vout=0.6V* (1+Rup/Rdown)
2
Vout=0.9V
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2013/03/09 Deciphered Date 2014/04/01 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR_+1.35VGPU/VDDCIP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-9981P
Date: Saturday, March 09, 2013 Sheet 43 of 55
5 4 3 2 1
5 4 3 2 1
PL800 VGA@_EMI@
B+ FBMA-L11-453215-800LMA90T_1812
1 2 GPU_B+
VGA@
VGA@
VGA@
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
VGA@_EMI@
2200P_0402_50V7K~D
0.1U_0402_25V6K~D
1
1
VGA@ PR822
PC831
PC832
PC804
PC805
PC808
@EMI@
+5VALW 2 1 62881_VDD GPU_B+
2
1_0603_5%
PR823 VGA@
0_0603_5%
SUN XT VENUS PRO/XT
2
PC811 VGA@
2
1U_0603_10V6K
Load line No need Need
0.22U_0603_25V7K
D D
GPU_B+
1
PR824 pop un-pop
25W 32W
1
+5VALW
VGA@ PC810
2
PR813 909 1.4K
1
PR824
PR833 @ 0_0402_5%
MDU1516URH 1N POWERDFN56-8
2 1
PR821 97.6K 143K
MDU1516URH 1N POWERDFN56-8
LL@
VGA@ PR802
2
10_0402_5% PR845 VGA@ PC816 VGA@ 0_0603_5% 32W@ VGA@ +VGA_CORE
12 62881_VIN
5
0_0402_5% 1 2 BST_VGA_CORE 1 2 1 2 PQ800 PQ803
ISUM+
ISUM-
2 1
PR825 976 1.5K
1
<52> VSSSENSE_VGA 1000P_0402_50V7K PC807 VGA@
2 1 PC809 @ 0.1U_0603_25V7K
<52> VCCSENSE_VGA PR846 VGA@ 1 2 330P_0402_50V7K
29
10
11
13
14
2
9
0_0402_5% 4 4
PR820 @ PC813 @
AGND
RTN
VDD
VIN
IMON
ISUM+
ISUM
BOOT
+VGA_CORE
2 1 330P_0402_50V7K
10_0402_5%
3
2
1
3
2
1
7 15 UG_VGA_CORE
VSEN UGATE 0.36UH_MMD-12CE-R36M-M1L_34A_20%
62881_FB 6 PU800 VGA@ 16 SW_VGA_CORE 1 2
FB ISL62881CHRTZ-T_QFN28_4X4 PHASE
62881_COMP 5 17 VGA@ VGA@ VGA@ PL802
680P_0603_50V7K
5
5
COMP VSSP PQ801 PQ802
MDU1511RH 1N POWERDFN56
MDU1511RH 1N POWERDFN56
1
62881_VW 4 18
@EMI@ PC815
VW LGATE
PR814 VGA@
VGA@ PR830
3
62881_RBIAS 19 62881_VCCP 1 2 +5VALW
2
RBIAS VCCP
0_0402_5%
PR813 25W@ PR821 25W@ PC818 VGA@ 0_0603_5%
PR829 VGA@
3.65K_0402_1%
1
1
909_0402_1% 97.6K_0402_1% 1000P_0402_50V7K 2 20 4 4
1
2 1 1 2GFX_FB-1
1 2 2 1 PGOOD VID0
1
1
1 21 PC803 VGA@
47K_0402_1%
4.7_1206_5%
DPRSLPVR
2
VGA@ PC806 CLK_EN# VID1 2.2U_0603_6.3V6K
VGA@ PR815
@EMI@ PR805
C C
390P_0402_50V7K
VR_ON
1
2
3
1
2
3
2
VID6
VID5
VID4
VID3
VID2
2
VGA@ PC814 1 2ISUM-2 1 2
2
2
62881_VID0
56P_0402_50V8 PR816 VGA@ PH800 VGA@
2 1GFX_FB-2
2 1 1 2 2 1 2.61K_0402_1% 10KB_0402_5%_ERTJ0ER103J
62881_VID1
28
27
26
25
24
23
22
VGA@ PC817 PR818 VGA@ PR817 VGA@
1000P_0402_50V7K 715_0402_1% 8.06K_0402_1%
62881_VR_ON
1 2
PR842 VGA@
62881_VID6
62881_VID5
62881_VID4
62881_VID3
62881_VID2
PR827 VGA@
1
11K_0402_1%
VGA@
1K_0402_1%
.1U_0402_16V7K
2
+3VS 1 2
VGA_CORE PC819 VGA@
PC821
2
1
ISUM-1
10K_0402_1%
TDC 23A(25W)/33A(32W)
1
PR808 @
0_0402_5%~D 2 1 PR811 @
0_0402_5%~D 2 1 PR810 @
GPU_VID1 <49>
Peak Current 30A(25W)/47A(32W) 1 2
0_0402_5%~D 2 1 PR812 @ PC820 VGA@
OCP current 36A(25W)/56A(32W)
2
2 1 GPU_VID2 <49>
0_0402_5%~D PR807 @ 0.033U_0402_16V7K
976_0402_1%
GPU_VID3 <49>
+3VS 0_0402_5%~D 2 1 PR809 @
25W@ PR825
TYP MAX
2
1
0_0402_5% 2 1 PR803 VGA@
L/S Rds(on) :2.75mohm , 3.5mohm ISUM+
ISUM-
GPU_VID5 GPU_VID4 GPU_VID3 GPU_VID2 GPU_VID1 PR813 32W@ PR821 32W@ PR825 32W@
2
4
0 1 1 1 1 1.125V PR819 VGA@ PU1300 0.47UH_FDVE0630-H-R47M=P3_17.7A_20%
+3VALW
1 2 2 1 PCIE_B+ 10 2 LX_PCIE 1 2
PG
2 1 PVIN LX
1 0 0 0 0 1.1V 10K_0402_1% 9 3
JUMP_43X79 PVIN LX
1
PR826 VENUS@ VGA@
4.7_1206_5%
1
1 2 GPU_VID2 PC1301 8
22U_0805_6.3VAM SVIN
PR1303
1 0 0 0 1 1.075V
10K_0402_1% 6 FB_PCIE
FB
2
PR834 SUN@ 5
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
2
1
1 2 EN
SS
1 0 0 1 0 1.05V
TP
LX
VGA@ PR1300 SY8036LDBC_DFN10_3x3
VGA@ PC1300
VGA@ PC1303
VGA@ PC1305
VGA@ PC1308
@EMI@
10K_0402_1%
11
2
PR835 @ 1 2EN_PCIE
PC1307 VGA@
1 0 0 1 1 1.025V PXS_PWREN
SNUB_PCIE
1 2 GPU_VID3
1
200K_0402_5% PR1302 VGA@
PC1302
0.1U_0402_10V7K
0.1U_0402_10V7K
1
1 0 1 0 0 1V 10K_0402_1%
1
PR836 VGA@ @ PR1304 5.9K_0402_1%
1 2 47K_0402_5% 2 1
VGA@
1 0 1 0 1 0.975V
2
10K_0402_1%
680P_0402_50V7K
PR837 VGA@
@EMI@ PC1304
1 0 1 1 0 0.95V PC1306
1 2 GPU_VID4 VGA@
2
2 1
1 0 1 1 1 0.925V 10K_0402_1%
PR838 @ VGA@ PR1301
+VGA_PCIEP
1 2 22P_0402_50V8J
10K_0402_1%
1 1 0 0 0 0.9V
+VGA_PCIE
A Vout=0.95V A
2
10K_0402_1%
PR839 VGA@
TDC 3A
1 1 0 0 1 0.875V 1 2 GPU_VID5 PJP1300
@ Peak Current 4.2A
10K_0402_1%
+VGA_PCIEP
2
2 1
1
+VGA_PCIE
OCP current 6A
1 1 0 1 0 0.85V PR840 @
1 2
JUMP_43X79
1 1 0 1 1 0.825V 10K_0402_1%
Security Classification Compal Secret Data Compal Electronics, Inc.
1 1 1 0 0 0.8V 2013/03/09 2014/04/01 Title
Initial voltage:0.85V(Venus) Issued Date Deciphered Date
0.9V(Sun) THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR_VGA_CORE/PCIE
1 1 1 0 1 0.775V Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9981P
Date: Saturday, March 09, 2013 Sheet 44 of 55
5 4 3 2 1
A
B
C
D
5
5
+CPU_CORE
2 1 2 1 2 1
2 1 2 1 2 1
2 1 2 1 2 1
2 1 2 1 2 1
4
4
2 1 2 1 2 1
2 1 2 1 2 1
2 1 2 1 2 1
2 1 2 1
PC916 PC908
22U_0805_6.3V6M 22U_0805_6.3V6M
3
3
Issued Date
Security Classification
+VGA_CORE
2013/03/09
VGA@ 10U_0603_6.3V6M VGA@ 1U_0402_6.3V6K VGA@ 1U_0402_6.3V6K VGA@ 1U_0402_6.3V6K
PC867 PC857 PC848 PC840
2
1
2
1
2
1
2
1
2
2
2014/04/01
PC836
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
330U_D2_2V_Y
2
1
+
32W@
PC837
470U_D2_2VM_R4.5M~D
PC836
Size
Title
Date:
2
1
+
32W@
25W@
470U_D2_2VM_R4.5M~D
330U_D2_2V_Y
PC837
2
1
+
32W@
470U_D2_2VM_R4.5M~D
PC838
PC838
Document Number
2
1
+
32W@
470U_D2_2VM_R4.5M~D
25W@
PC839
LA-9981P
330U_D2_2V_Y
PC839
25W@
Sheet
330U_D2_2V_Y
45
Compal Electronics, Inc.
of
55
PWR_PROCESSOR DECOUPLING
Rev
0.2
A
B
C
D
5 4 3 2 1
D Power block D
CPU OTP
Page 45
Turn Off
Input B+
DC IN +3VALWP: TDC:5.4A
Switch Page 46 +5VALWP: TDC:5.6A EC_ON
TPS51225CRUKR Page 47
SY8003DFC
Page 48
CHARGER
CC:0A~1A(4cell) or 2.1A(6cell)
CV:17.7V(4cell) / 13.3V(6cell)
+3VALW +1.5VSP: TDC:2.5A SUSP#
BQ24717
SY8003DFC
Page 46 Page 48
ISL62881CHRTZ-T
Page 53
+CPU_CORE
VR_ON
TDC: 14A +1.35VP/+0.675VSP: TDC:6A/0.7A SYSON
TPS51622RSM RT8207MZQW
Page 51
Page 50
A A
1 45 CHARGER 13/01/30 Morris adjust design parameter from vendor recommend delete PD702 0.2
change PC712 to unpop
change PQ704 to unpop
change PC707 from 0.1uF_0402 to 1uF_0603
change PC720 from 0.1uF to 100pF
change PC711 from 1000pF to 0.01uF
change PQ705 from SB00000SD00 to SB00000WY00
2 50 VCORE 13/01/30 Morris adjust design parameter from vendor recommend change PC509 from 0.1uF to 1000pF 0.2
change PR529 from 3.83K to 5.76K
change PR504 from 523K to 499K
3 44 DCIN/BATT CONN/OTP 13/01/30 Morris change from ESD request change PD1 from SC300002E00 to SC300001G00 0.2
4 46 3.3VALWP/5VALWP 13/02/01 Morris add ESD diode from ESD request add PD101(SCA00002A00) 0.2
5 50 VCORE 13/02/21 Morris adjust design parameter from fine tune result change PR501 from 422K to 523K 0.2
change PR503 from 56K to 75K
7 52 VGA_CORE/PCIE 13/03/05 Morris adjust output voltage from vender request unpop PR826 and pop PR834 (only for Sun XT) 0.2
C C
B B
A A
D
GFX PCIE LANE REVERSAL D
UV1A
<12> PEG_CTX_GRX_P0 PEG_CTX_GRX_P0 AA38 Y33 PCIE_CRX_C_GTX_P0 0.1U_0402_10V7K~D 2 1 CV43 DIS@ PEG_CRX_GTX_P0 PEG_CRX_GTX_P0 <12>
<12> PEG_CTX_GRX_N0 PEG_CTX_GRX_N0 Y37 PCIE_RX0P
PCIE_RX0N
PCIE_TX0P
PCIE_TX0N
Y32 PCIE_CRX_C_GTX_N0 0.1U_0402_10V7K~D 2 1 CV44 DIS@ PEG_CRX_GTX_N0 PEG_CRX_GTX_N0 <12>
LVDS Interface
<12> PEG_CTX_GRX_P1 PEG_CTX_GRX_P1 Y35 W33 PCIE_CRX_C_GTX_P1 0.1U_0402_10V7K~D 2 1 CV45 DIS@ PEG_CRX_GTX_P1 PEG_CRX_GTX_P1 <12>
PEG_CTX_GRX_N1 W36 PCIE_RX1P PCIE_TX1P W32 PCIE_CRX_C_GTX_N1 0.1U_0402_10V7K~D 2 1 CV46 DIS@ PEG_CRX_GTX_N1
<12> PEG_CTX_GRX_N1 PCIE_RX1N PCIE_TX1N PEG_CRX_GTX_N1 <12>
UV1G
<12> PEG_CTX_GRX_P2 PEG_CTX_GRX_P2 W38 U33 PCIE_CRX_C_GTX_P2 0.1U_0402_10V7K~D 2 1 CV47 DIS@ PEG_CRX_GTX_P2 PEG_CRX_GTX_P2 <12>
PEG_CTX_GRX_N2 V37 PCIE_RX2P PCIE_TX2P U32 PCIE_CRX_C_GTX_N2 0.1U_0402_10V7K~D 2 1 CV48 DIS@ PEG_CRX_GTX_N2
<12> PEG_CTX_GRX_N2 PCIE_RX2N PCIE_TX2N PEG_CRX_GTX_N2 <12>
LVDS CONTROL AK27
VARY_BL AJ27
PEG_CTX_GRX_P3 V35 U30 PCIE_CRX_C_GTX_P3 0.1U_0402_10V7K~D 2 1 CV49 DIS@ PEG_CRX_GTX_P3
DIGON
<12> PEG_CTX_GRX_P3 PCIE_RX3P PCIE_TX3P PEG_CRX_GTX_P3 <12>
<12> PEG_CTX_GRX_N3 PEG_CTX_GRX_N3 U36 U29 PCIE_CRX_C_GTX_N3 0.1U_0402_10V7K~D 2 1 CV50 DIS@ PEG_CRX_GTX_N3 PEG_CRX_GTX_N3 <12>
PCIE_RX3N PCIE_TX3N
G38 K30
F37 PCIE_RX14P PCIE_TX14P K29
PCIE_RX14N PCIE_TX14N
F35 H33
E37 PCIE_RX15P PCIE_TX15P H32
PCIE_RX15N PCIE_TX15N
B B
CLOCK
CLK_PEG_VGA AB35 +3VGS
<9> CLK_PEG_VGA PCIE_REFCLKP
CLK_PEG_VGA# AA36
<9> CLK_PEG_VGA# PCIE_REFCLKN DIS@ Place CV326 Close to UV13
RV198
CALIBRATION 1.69K_0402_1%~D
Y30 1 2 +VGA_PCIE 2 DIS@
DIS@ PCIE_CALRP CV326
1 2 AH16 Y29 1 2 +VGA_PCIE 0.1U_0402_25V6K
RV64 1K_0402_5% PWRGOOD PCIE_CALRN
5
DIS@ 1
GPU_RST# AA30 RV203
VCC
PERSTB 1K_0402_1% 1
<10> DGPU_HOLD_RST# IN1
1
4 GPU_RST#
DIS@ 216-0833000-A11-THAMES-XT-M2_FCBGA962~D 2 OUT
GND
<10,21,26,30,6> PLT_RST# IN2
RV66 THAMES XT M2
100K_0402_5% UV13
VENUS@ MC74VHC1G08DFT2G_SC70-5
2
3
DIS@
A A
1
AU1 AV31 chg to @
DVPDATA_0 TX3P_DPB2P
1
D AU3 AU30 RV73 RSVD GPIO8 RESERVED 0 D
AW3 DVPDATA_1 TX3M_DPB2N
DPB RV74 @
AP6 DVPDATA_2 AR32 DIS@ 10K_0402_5%
AW5 DVPDATA_3 TX4P_DPB1P AT31 4.7K_0402_5% BIF_VGA DIS GPIO9 VGA ENABLED 0
2
AU5 DVPDATA_4 TX4M_DPB1N AC_BATT
2
AR6 DVPDATA_5 AT33 QV14A
AW6 DVPDATA_6 TX5P_DPB0P AU32 DMN66D0LDW-7_SOT363-6 RSVD GPIO21 RESERVED 0
AU6 DVPDATA_7 TX5M_DPB0N DIS@
DVPDATA_8
3
AT7 AU14 0: disable
AV7 DVPDATA_9 TXCCP_DPC3P AV13 PACIN# 5 D
G
BIOS_ROM_EN GPIO_22_ROMCSB ENABLE EXTERNAL BIOS ROM 1: enable X
AN7 DVPDATA_10 TXCCM_DPC3N S
4
AT9 DVPDATA_12 TX0P_DPC2P AR14 QV14B ROMIDCFG(2:0) GPIO[13:11] SERIAL ROM TYPE OR MEMORY APERTURE SIZE SELECT XXX
DVPDATA_13 TX0M_DPC2N
6
AR10 DMN66D0LDW-7_SOT363-6
AW10 DVPDATA_14 AU16 1 2 2
D
1
AV11 DVPDATA_17 AT17
GPIO1 GPU_GPIO1 AT11 DVPDATA_18 TX2P_DPC0P AR16
0_0402_5%
@ RSVD H2SYNC 0
AR12 DVPDATA_19 TX2M_DPC0N
GPIO2 GPU_GPIO2 AW12 DVPDATA_20 AU20
AU12 DVPDATA_21 TXCDP_DPD3P AT19 <30> ACIN_65W
GPIO7 N.C AP12 DVPDATA_22 TXCDM_DPD3N
RSVD GENERICC 0
DVPDATA_23
GPIO11 GPU_GPIO11 AJ21 TX3P_DPD2P
AT21
AR20 AUD[1] HSYNC
AUD[1] AUD[0]
0 0 No audio function 11
SWAPLOCKA TX3M_DPD2N
GPIO12 GPU_GPIO12 AK21
SWAPLOCKB DPD AU22 AUD[0] VSYNC
0 1 Audio for DisplayPort and HDMI if dongle is detected
TX4P_DPD1P 1 0 Audio for DisplayPort only
GPIO13 GPU_GPIO13 TX4M_DPD1N
AV21
1 1 Audio for both DisplayPort and HDMI
CV75
CV76
CV77
@ <44> GPU_VID3 10mil LV12
GPIO_15_PWRCNTL_0
0.1U_0402_16V7K
1U_0402_6.3V6K
10U_0603_6.3V6M
GPU_VID2 AK14 AC33 +VDD1DI (1.8V@100mA VDD1DI) 1 2 1 1 1 BLM15BD121SN1D_0402
<44> GPU_VID2 AG30 GPIO_16 VDD1DI AC34 +1.8VGS
@ THM_ALERT# SUN@
1 8 GPU_GPIO2 AN14 GPIO_17_THERMAL_INT VSS1DI
CV78
CV79
CV80
LV13
1U_0402_6.3V6K
10U_0603_6.3V6M
GPIO_18_HPD3
0.1U_0402_16V7K
2 7 RV89 1 @ 2 10K_0402_5% AM17 BLM15BD121SN1D_0402
VENUS@
VENUS@
VENUS@
GPIO_19_CTF 1 1 1
3 6 GPU_GPIO8 GPU_VID1 AL13 AC30 2 2 2
4 5 GPU_GPIO9 <44> GPU_VID1 GPIO21_BBEN AJ14 GPIO_20_PWRCNTL_1 R2/NC AC31 +1.8VGS +1.8VGS +1.8VGS
T78 AK13 GPIO_21_BB_EN R2B/NC
VENUS@
VENUS@
VENUS@
VGA_CLKREQ#_R AN13 GPIO_22_ROMCSB AD30 2 2 2
RP60
10K_8P4R_5% GPIO24_TRSTB AM23 GPIO_23_CLKREQB G2/NC AD31 PS_1
JTAG_TRSTB G2B/NC
1
GPIO25_TDI AN23
10K_0402_5% 1 @ 2 RV81 GPU_GPIO11 GPIO26_TCK AK23 JTAG_TDI AF30 RV237 RV239 RV241
10K_0402_5% 1 @ 2 RV82 GPU_GPIO12 GPIO27_TMS AL24 JTAG_TCK B2/NC AF31 8.45K_0402_1% 10K_0402_1% 8.45K_0402_1%
10K_0402_5% 1 @ 2 RV83 GPU_GPIO13 T79 GPIO28_TDO AM24 JTAG_TMS B2B/NC RV246 @ @ @
10K_0402_5% 1 @ 2 RV85 AC_BATT AJ19 JTAG_TDO 1 2 +DPLL_PVDD
2
AK19 GENERICA AC32 @ 0_0402_5% PS_1 PS_2 PS_3
@ AJ20 GENERICB C/NC AD32 RV247
GENERICC Y/NC
1
1 8 GPIO24_TRSTB AK20 AF32 1 2 DPLL_PVSS
2 7 GPIO25_TDI AJ24 GENERICD COMP/NC
@ 0_0402_5% 1 RV238 1 RV240 1 RV242
GENERICE_HPD4
0.68U_0402_10V
0.68U_0402_10V
0.68U_0402_10V
3 6 GPIO27_TMS AH26 DAC2 4.75K_0402_1% 4.75K_0402_1% 4.75K_0402_1%
4 5 GPIO26_TCK AH24 GENERICF_HPD5 AD29 GENLK_CLK T80 CV329 SUN@ CV331 SUN@ CV333 SUN@
GENERICG_HPD6 H2SYNC/GENLK_CLK AC29 GENLK_VSYNC T81
2
RP47 V2SYNC/GENLK_VSYNC @ 2 SUN@ 2 @ 2
10K_8P4R_5% AK24
HPD1 AG31 PS_2
VDD2DI/NC AG32 GPU_GPIO6
0.60 V level, Please GPU_GPIO6 <43>
VSS2DI/NC
VREFG Divider ans
cap close to ASIC AG33
+1.8VGS A2VDD/NC
SUN@
20mil AD33 PS_3
+1.8VGS 2 RV93 1 499_0402_1% AH13 A2VDDQ/NC
+VREFG_GPU
VREFG AF33 1
SUN@
2 Vendor RV241 RV242 Bits [3:1]
(75mA) SUN@
2 RV95 1 249_0402_1% A2VSSQ/TSVSSQ
DIS@ RV207 0_0402_5% H5TC2G63FFR-11C
2 1 +DPLL_PVDD
2 1 20mil AA29
* 128MX16 (1GB) Hynix 2Gb
BLM15BD121SN1D_0402
NC_TSVSSQ should be tied to GND DDR3 NC 4.75K 000
+DPLL_PVDD AM32 R2SET/NC SA00006H40L(R1)
CV82
CV83
CV84
0.1U_0402_16V7K
10U_0603_6.3V6M
DIS@
DIS@
DDR3
AUX1P
AM27 SA00005SH0L(R1)
XTALIN XTALIN AV33 AL27
XTALIN AUX1N SA00005SH1L(R3)
1
XTALOUT AU34
Voltage Swing: 1.8 V XTALOUT
(125mA) RV235 AM19 MT41K128M16JT-107G:K
+VGA_PCIE DDC2CLK AL19
10K_0402_5%
AW34 DDC2DATA 128MX16 (1GB) Micron 2Gb
DIS@ 0.95V@Venus @ DDR3 4.75K NC 111
2 1 +DPLL_VDDC XO_IN AN20 SA00005XB0L(R1)
2
CV87
CV88
LV15
1U_0402_6.3V6K
0.1U_0402_16V7K
10U_0603_6.3V6M
1 1 1 AL30
RV236 DDCCLK_AUX3P AM30
DDCDATA_AUX3N
10K_0402_5%
AL29
2 2 2 DIS@ DDCCLK_AUX4P
GPU_THERMAL_D+ AF29 AM29
DIS@
DIS@
DIS@
TSVSS
0.1U_0402_16V7K
DIS@ CV91
DIS@ CV92
DIS@ CV93
YV1 DIS@ 1 1 1
27MHZ_10PF_7V27000050
216-0833000-A11-THAMES-XT-M2_FCBGA962~D SUN Internal VGA Thermal Sensor
3 1
3 1 2 2 2
VENUS@
Address 0x714
GND GND
1
CV94 CV95
10P_0402_50V8J 10P_0402_50V8J
4 2
2
DIS@ DIS@
+3VGS
A For GCLK +3VGS A
1
DIS@ DIS@
1
2.2K_0402_5%
2
2
G
G
2
VGA_SMB_CK2 1 6
EC_SMB_CK2 <19,30,9>
S
1 3 VGA_CLKREQ#_R
<9> PEG_CLKREQ#
5
DIS@ QV15B
D
DMN66D0LDW-7_SOT363-6
G
VGA_SMB_DA2 4 3
EC_SMB_DA2 <19,30,9>
S
QV28 @
2N7002K_SOT23-3 DIS@ QV15A
DMN66D0LDW-7_SOT363-6
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2013/03/09 Deciphered Date 2014/04/01 Title
ATI_Sun XT_M2_Main_MSIC
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Docum ent Num ber Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-9981P
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Saturday, March 09, 2013 Sheet 49 of 55
5 4 3 2 1
5 4 3 2 1
D D
+3VALW
1
+3VGS
DIS@
60mil 60mil
RV109
100K_0402_5% 1 2 1 2
1
2
@ VENUS@ SUN@
RV105 PXS_PWREN# for PX5.0
20K_0402_5%
1
1
2
D DIS@
PXS_PWREN 2 QV25 DIS@ CV97
<10,11,39,43,44> PXS_PWREN
G 2N7002K_SOT23-3 22U_0805_6.3V6M
S
2
C 3 C
JP8 @
@ 2 1
3 1 2 2
B
QV22 DIS@
+5VALW DIS@ DIS@ AP2301GN-HF_SOT23-3
2
RV107 RV108
+VDDCI(+VGA_PCIE) 1 2
20K_0402_5% 1K_0402_5%
+1.35V_MEM_GFX 1
1
DIS@
2
CV103
0.1U_0603_25V7K
S QV24 DIS@
3
+1.35VS_VGA +1.35V_MEM_GFX 2N7002K_SOT23-3
+1.8VGS <20ms
JP9 @
2 1
2MM
SHORT DEFAULT
A A
UV1F
AB39 A3
E39 PCIE_VSS#1 GND#1 A37
F34 PCIE_VSS#2 GND#2 AA16
F39 PCIE_VSS#3 GND#3 AA18
G33 PCIE_VSS#4 GND#4 AA2
G34 PCIE_VSS#5 GND#5 AA21
H31 PCIE_VSS#6 GND#6 AA23
H34 PCIE_VSS#7 GND#7 AA26
D D
H39 PCIE_VSS#8 GND#8 AA28
J31 PCIE_VSS#9 GND#9 AA6
J34 PCIE_VSS#10 GND#10 AB12
K31 PCIE_VSS#11 GND#11 AB15
K34 PCIE_VSS#12 GND#12 AB17
K39 PCIE_VSS#13 GND#13 AB20
(30mA) L31 PCIE_VSS#14 GND#14 AB22
+DPAB_VDD18 +1.8VGS L34 PCIE_VSS#15 GND#15 AB24
M34 PCIE_VSS#16 GND#16 AB27
1.8V@300mA DPAB_VDD18) PCIE_VSS#17 GND#17
+DPAB_VDD18 1 2 M39 AC11
N31 PCIE_VSS#18 GND#18 AC13
1 1 1 PCIE_VSS#19 GND#19
@ N34 AC16
VENUS@ CV108
VENUS@ CV109
VENUS@ CV110
10U_0603_6.3V6M
0.1U_0402_16V7K
1U_0402_6.3V6K
UV1H RV118 P31 PCIE_VSS#20 GND#20 AC18
(30mA) 20mil 0_0402_1% P34 PCIE_VSS#21 GND#21 AC2
+1.8VGS +DPCD_VDD18 2 2 2 P39 PCIE_VSS#22 GND#22 AC21
1.8V@300mA DPCD_VDD18) DP C/D POWER DP A/B POWER 20mil PCIE_VSS#23 GND#23
130mA R34 AC23
1 2 +DPCD_VDD18 AP20 AN24 T31 PCIE_VSS#24 GND#24 AC26
AP21 DPCD/DPC_VDD18#1 DPAB/DPA_VDD18#1 AP24 T34 PCIE_VSS#25 GND#25 AC28
@VENUS@ DPCD/DPC_VDD18#2 DPAB/DPA_VDD18#2 (330mA) T39 PCIE_VSS#26 GND#26 AC6
CV111
CV112
CV113
10U_0603_6.3V6M
1U_0402_6.3V6K
0.1U_0402_16V7K
RV119 +DPCD_VDD10 +DPAB_VDD10 +VGA_PCIE U31 PCIE_VSS#27 GND#27 AD15
1 1 1 20mil (1.0V@220mA DPAB_VDD10) PCIE_VSS#28 GND#28
0_0402_1% 20mil 110mA 0.95V@Venus U34 AD17
@ @ @ AP13 AP31 +DPAB_VDD10 1 2 V34 PCIE_VSS#29 GND#29 AD20
AT13 DPCD/DPC_VDD10#1 DPAB/DPA_VDD10#1 AP32 V39 PCIE_VSS#30 GND#30 AD22
10U_0603_6.3V6M
1U_0402_6.3V6K
0.1U_0402_16V7K
2 2 2 DPCD/DPC_VDD10#2 DPAB/DPA_VDD10#2 @ W31 PCIE_VSS#31 GND#31 AD24
VENUS@ CV114
VENUS@ CV115
VENUS@ CV116
RV120 W34 PCIE_VSS#32 GND#32 AD27
1 1 1 PCIE_VSS#33 GND#33
AN17 AN27 0_0402_1% Y34 AD9
AP16 DP/DPC_VSSR#1 DP/DPA_VSSR#1 AP27 Y39 PCIE_VSS#34 GND#34 AE2
AP17 DP/DPC_VSSR#2 DP/DPA_VSSR#2 AP28 PCIE_VSS#35 GND#35 AE6
AW14 DP/DPC_VSSR#3 DP/DPA_VSSR#3 AW24 2 2 2 GND#36 AF10
(220mA) +DPCD_VDD10 AW16 DP/DPC_VSSR#4 DP/DPA_VSSR#4 AW26 GND#37 AF16
+VGA_PCIE DP/DPC_VSSR#5 DP/DPA_VSSR#5 GND#38 AF18
1.0V@220mA DPCD_VDD10) GND#39
0.95V@Venus +DPCD_VDD18 +DPAB_VDD18 AF21
1 2 +DPCD_VDD10 20mil
AP22
DPCD/DPD_VDD18#1 DPAB/DPB_VDD18#1
20mil
AP25 130mA F15
GND#100
GND GND#40
GND#41
GND#42
AG17
AG2
@VENUS@ AP23 AP26 F17 AG20
@ CV117
@ CV118
@ CV119
10U_0603_6.3V6M
1U_0402_6.3V6K
0.1U_0402_16V7K
1
AJ34 DPEF/DPE_VDD18#1 DPAB_VDD18/DPA_PVDD AV27 L2 GND#122 GND#64 AL6
@VENUS@ DPEF/DPE_VDD18#2 DP_VSSR/DPA_PVSS L22 GND#123 GND#65 AL8 @
VENUS@ CV120
VENUS@ CV121
VENUS@ CV122
10U_0603_6.3V6M
1U_0402_6.3V6K
0.1U_0402_16V7K
2
AM33 AR28 M22 AN11
2 2 2 DPEF/DPE_VDD10#2 DP_VSSR/DPB_PVSS M24 GND#128 GND#70 AN2
+DPCD_VDD18 N16 GND#129 GND#71 AN30
N18 GND#130 GND#72 AN6
20mA 10mil GND#131 GND#73
AN34 AU18 N2 AN8
AP39 DP/DPE_VSSR#1 DPCD_VDD18/DPC_PVDD AV17 N21 GND#132 GND#74 AP11
+DPEF_VDD10 AR39 DP/DPE_VSSR#2 DP_VSSR/DPC_PVSS N23 GND#133 GND#75 AP7
(220mA) AU37 DP/DPE_VSSR#3 +DPCD_VDD18 N26 GND#134 GND#76 AP9
+VGA_PCIE DP/DPE_VSSR#4 N6 GND#135 GND#77 AR5
1.0V@240mA DPEF_VDD10) 20mA 10mil GND#136 GND#78
0.95V@Venus AV19 R15 B11
1 2 +DPEF_VDD10 +DPEF_VDD18 DPCD_VDD18/DPD_PVDD AR18 R17 GND#137 GND#79 B13
DP_VSSR/DPD_PVSS R2 GND#138 GND#80 B15
20mil GND#139 GND#81
@VENUS@ AF34 +DPEF_VDD18 R20 B17
@ CV123
@ CV124
@ CV125
10U_0603_6.3V6M
1U_0402_6.3V6K
0.1U_0402_16V7K
B B
RV126 AG34 DPEF/DPF_VDD18#1 R22 GND#140 GND#82 B19
1 1 1 DPEF/DPF_VDD18#2
20mA 10mil GND#141 GND#83
0_0402_1% AM37 R24 B21
+DPEF_VDD10 DPEF_VDD18/DPE_PVDD AN38 R27 GND#142 GND#84 B23
DP_VSSR/DPE_PVSS R6 GND#143 GND#85 B25
2 2 2
20mil GND#144 GND#86
AK33 +DPEF_VDD18 T11 B27
AK34 DPEF/DPF_VDD10#1 T13 GND#145 GND#87 B29
20mA 10mil
DPEF/DPF_VDD10#2 AL38 T16 GND#146 GND#88 B31
DPEF_VDD18/DPF_PVDD AM35 T18 GND#147 GND#89 B33
DP_VSSR/DPF_PVSS T21 GND#148 GND#90 B7
AF39 T23 GND#149 GND#91 B9
AH39 DP/DPF_VSSR#1 T26 GND#150 GND#92 C1
AK39 DP/DPF_VSSR#2 U15 GND#151 GND#93 C39
AL34 DP/DPF_VSSR#3 U17 GND#153 GND#94 E35
PS_0 AM34 DP/DPF_VSSR#4 U2 GND#154 GND#95 E5
DP/DPF_VSSR#5 U20 GND#155 GND#96 F11
U22 GND#156 GND#97 F13
+1.8VGS U24 GND#157 GND#98
AM39 U27 GND#158
DPEF_CALR U6 GND#159
V11 GND#160
1
W2
2
W6 GND#168
AMD recommended setting GND#169
PS_0 MLPS Bit Y15
Y17 GND#170
strap R_PU R_PD C GND#171
Y20
1
(440mA) +1.8VGS
(1.8V@504mA PCIE_VDDR) @ LV17
+PCIE_VDDR 2 1
MBK1608121YZF_0603
CV126
CV127
CV128
CV129
CV130
CV131
10U_0603_6.3V6M
0.1U_0402_16V7K
0.1U_0402_16V7K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1 1 1 1 1 1
2 2 2 2 2 2
@
UV1E 40mA +1.8VGS
For GDDR5 MVDDQ = 1.35V DIS@ LV18
+1.35V_MEM_GFX MEM I/O 2 1
D (1.7)A 40mil MBK1608121YZF_0603
(SUN) (VENUS) D
CV132
CV133
CV134
PCIE
10U_0603_6.3V6M
1U_0402_6.3V6K
0.1U_0402_16V7K
AC7 AA31 1 1 1 (PCIe 2.0 => 1.8V@50mA PCIE_PVDD)
AD11 VDDR1#1 PCIE_VDDR#1 AA32
VDDR1#2 PCIE_VDDR#2
220U_B2_2.5VM_R35
AF7 AA33 @ 1 2 +PCIE_VDDR
CV136
CV137
CV138
CV139
CV140
CV141
CV142
CV143
CV144
CV145
(PCIe 3.0 => 1.8V@80mA PCIE_PVDD)
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1 VDDR1#3 PCIE_VDDR#3
CV135
1 1 1 1 1 1 1 1 1 1 AG10 AA34 RV244 0_0402_5%
@ + AJ7 VDDR1#4 PCIE_VDDR#4 V28 2 2 2
DIS@
DIS@
DIS@
AK8 VDDR1#5 PCIE_VDDR#5 W29 @ 1 2
VDDR1#6 PCIE_VDDR#6 +BIF_VDDC
AL9 W30 RV245 0_0402_5%
2 2 2 2 2 2 2 2 2 2 2 G11 VDDR1#7 PCIE_VDDR#7 Y31
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
G14 VDDR1#8 PCIE_VDDR#8 AB37 +PCIE_PVDD +VGA_PCIE
G17 VDDR1#9 PCIE_VDDR/PCIE_PVDD
G20 VDDR1#10 G30
G23 VDDR1#11 PCIE_VDDC#1 G31
G26 VDDR1#12 PCIE_VDDC#2 H29
CV146
CV147
CV148
CV149
CV150
CV151
(SUN) (VENUS)
10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
G29 VDDR1#13 PCIE_VDDC#3 H30
VDDR1#14 PCIE_VDDC#4 1 1 1 1 1 1
H10 J29 (PCIe 2.0 => +0.95V@1920mA PCIE_VDDC)
+1.35V_MEM_GFX J7 VDDR1#15 PCIE_VDDC#5 J30
J9 VDDR1#16 PCIE_VDDC#6 L28
VDDR1#17 PCIE_VDDC#7 2 2 2 2 2 2
(PCIe 3.0 => +0.95V@2.5A PCIE_VDDC)
K11 M28
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
K13 VDDR1#18 PCIE_VDDC#8 N28
K8 VDDR1#19 PCIE_VDDC#9 R28
CV152
CV153
CV154
CV155
CV156
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
L12 VDDR1#20 PCIE_VDDC#10 T28
1 1 1 1 1 VDDR1#21 PCIE_VDDC#11
L16 U28
L21 VDDR1#22 PCIE_VDDC#12 +VGA_CORE
L23 VDDR1#23
2 2 2 2 2 L26 VDDR1#24 AA15
DIS@
DIS@
DIS@
DIS@
DIS@
L7 VDDR1#25 CORE VDDC#1 AA17 (20.5A)
M11 VDDR1#26 VDDC#2 AA20
N11 VDDR1#27 VDDC#3 AA22
P7 VDDR1#28 VDDC#4 AA24
VDDR1#29 VDDC#5 1
R11 AA27
U11 VDDR1#30 VDDC#6 AB16 CV327
+1.8VGS +VDDC_CT U7 VDDR1#31 VDDC#7 AB18 330U_D2_2.5V_R6M
(50mA) Y11 VDDR1#32 VDDC#8 AB21 2 X@
DIS@ LV19 Y7 VDDR1#33 VDDC#9 AB23
(1.8V@110mA VDD_CT) VDDR1#34 VDDC#10
1 2 AB26
BLM15BD121SN1D_0402 VDDC#11 AB28
C C
VDDC#12 AC17
CV170
CV171
CV172
CV173
CV174
10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
0.1U_0402_16V7K
VDDC#13 AC20
1 1 1 1 1 VDDC#14
LEVEL AC22
+3VGS 20mil TRANSLATION VDDC#15 AC24
VDDC#16
POWER
AF26 AC27
(60mA) 2 2 2 2 2 AF27 VDD_CT#1 VDDC#17 AD18
DIS@
DIS@
DIS@
DIS@
DIS@
AG26 VDD_CT#2 VDDC#18 AD21
AG27 VDD_CT#3 VDDC#19 AD23
CV187
CV188
CV189
CV190
10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
DIS@
DIS@
DIS@
CV194
1U_0402_6.3V6K
0.1U_0402_16V7K
VENUS@
CV195
CV196
1U_0402_6.3V6K
1U_0402_6.3V6K
1 2 M21 NC_VDDRHA VDDC#44 U21
NC_VSSRHA VDDC#45 U23
1 1 For non-BACO designs, connect BIF_VDDC to VDDC.
MCK1608471YZF 0603
+1.8VGS (50mA) VDDC#46 U26 For BACO designs - see BACO reference schematics
LV22 DIS@ V12 VDDC#47 V17
CV197
CV198
CV199
(1.8V@75mA SPV18)
10U_0603_6.3V6M
1U_0402_6.3V6K
0.1U_0402_16V7K
DIS@
DIS@
B 1 1 1 NC_VSSRHB VDDC#49 B
BLM15BD121SN1D_0402 V22
VDDC#50 V24
CV200
CV201
CV202
10U_0603_6.3V6M
1U_0402_6.3V6K
0.1U_0402_16V7K
VDDC#51 V27
1 1 1 VDDC#52
2 2 2 Y16
DIS@
DIS@
DIS@
DIS@
DIS@
CV203
CV204
CV205
CV206
CV207
CV208
CV209
CV210
CV211
CV212
CV213
CV214
10U_0603_6.3V6M
22U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
+VDDCI +VGA_CORE AN10 VDDCI#3 AC15 1 2
CV215
CV216
CV217
10U_0603_6.3V6M
1U_0402_6.3V6K
0.1U_0402_16V7K
SPVSS VDDCI#4 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 AD13 BLM15BD121SN1D_0402
VDDCI#5 AD16
1
VDDCI#6 M15
RV215 RV202 VDDCI#7 M16 2 2 2 2 2 2 2 2 2 2 2 2
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
2 2 2 10_0402_1% 10_0402_1% VDDCI#8 M18
DIS@
DIS@
DIS@
VOLTAGE
DIS@ DIS@ SENESE
VDDCI#9 M23
VDDCI#10 N13
10mil VDDCI#11
2
CV325
CV324
CV322
CV323
10mil
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
1U_0402_6.3V6K
VDDCI_SEN AG28 VDDCI#14 N22
<43> VDDCI_SEN FB_VDDCI 1 1 1 1
ISOLATED VDDCI#15 R12
CORE I/O VDDCI#16 R13
VSSSENSE_VGA AH29 VDDCI#17 R16
<44> VSSSENSE_VGA FB_GND VDDCI#18 2 2 2 2
T12
DIS@
DIS@
DIS@
DIS@
VDDCI#19
1
T15
RV204 VDDCI#20 V15
DIS@ 10_0402_1% VDDCI#21 Y13
VDDCI#22
VDDCI and VDDC should have seperate regulators with a merge option on PCB
2
A 216-0833000-A11-THAMES-XT-M2_FCBGA962~D A
VENUS@
For Madison, Park, Capilano, Robson, Seymour and Whistler, VDDCI and VDDC can share one common regulator
UV1C UV1D
DDR2 DDR2 DDR2 DDR2
GDDR3/GDDR5 GDDR5/GDDR3 GDDR3/GDDR5 GDDR5/GDDR3
DDR3 DDR3 DDR3 DDR3
MDA0 C37 G24 MAA0 MDB0 C5 P8 MAB0
MDA1 C35 DQA0_0/DQA_0 MAA0_0/MAA_0 J23 MAA1 MDB1 C3 DQB0_0/DQB_0 MAB0_0/MAB_0 T9 MAB1
MDA2 A35 DQA0_1/DQA_1 MAA0_1/MAA_1 H24 MAA2 MDB2 E3 DQB0_1/DQB_1 MAB0_1/MAB_1 P9 MAB2
MDA3 E34 DQA0_2/DQA_2 MAA0_2/MAA_2 J24 MAA3 MDA[0..63] MDB3 E1 DQB0_2/DQB_2 MAB0_2/MAB_2 N7 MAB3
DQA0_3/DQA_3 MAA0_3/MAA_3 <54> MDA[0..63] DQB0_3/DQB_3 MAB0_3/MAB_3
MDA4 G32 H26 MAA4 MDB4 F1 N8 MAB4
MEMORY INTERFACE A
MDA5 D33 DQA0_4/DQA_4 MAA0_4/MAA_4 J26 MAA5 MDB5 F3 DQB0_4/DQB_4 MAB0_4/MAB_4 N9 MAB5
MEMORY INTERFACE B
MDA6 F32 DQA0_5/DQA_5 MAA0_5/MAA_5 H21 MAA6 MAA[14..0] MDB6 F5 DQB0_5/DQB_5 MAB0_5/MAB_5 U9 MAB6
DQA0_6/DQA_6 MAA0_6/MAA_6 MAA[14..0] <54> DQB0_6/DQB_6 MAB0_6/MAB_6
MDA7 E32 G21 MAA7 MDB7 G4 U8 MAB7
MDA8 D31 DQA0_7/DQA_7 MAA0_7/MAA_7 H19 MAA8 A_BA[2..0] MDB8 H5 DQB0_7/DQB_7 MAB0_7/MAB_7 Y9 MAB8
DQA0_8/DQA_8 MAA1_0/MAA_8 A_BA[2..0] <54> DQB0_8/DQB_8 MAB1_0/MAB_8
MDA9 F30 H20 MAA9 MDB9 H6 W9 MAB9
MDA10 C30 DQA0_9/DQA_9 MAA1_1/MAA_9 L13 MAA10 MDB10 J4 DQB0_9/DQB_9 MAB1_1/MAB_9 AC8 MAB10
D D
MDA11 A30 DQA0_10/DQA_10 MAA1_2/MAA_10 G16 MAA11 MDB11 K6 DQB0_10/DQB_10 MAB1_2/MAB_10 AC9 MAB11
MDA12 F28 DQA0_11/DQA_11 MAA1_3/MAA_11 J16 MAA12 MDB12 K5 DQB0_11/DQB_11 MAB1_3/MAB_11 AA7 MAB12
MDA13 C28 DQA0_12/DQA_12 MAA1_4/MAA_12 H16 A_BA2 MDB13 L4 DQB0_12/DQB_12 MAB1_4/MAB_12 AA8 B_BA2
MDA14 A28 DQA0_13/DQA_13 MAA1_5/MAA_13_BA2 J17 A_BA0 MDB14 M6 DQB0_13/DQB_13 MAB1_5/BA2 Y8 B_BA0
MDA15 E28 DQA0_14/DQA_14 MAA1_6/MAA_14_BA0 H17 A_BA1 MDB15 M1 DQB0_14/DQB_14 MAB1_6/BA0 AA9 B_BA1
MDA16 D27 DQA0_15/DQA_15 MAA1_7/MAA_A15_BA1 MDB16 M3 DQB0_15/DQB_15 MAB1_7/BA1
DQA0_16/DQA_16 DQMA#[7..0] <54> DQB0_16/DQB_16 DQMB#[7..0] <55>
MDA17 F26 A32 DQMA#0 MDB17 M5 H3 DQMB#0
MDA18 C26 DQA0_17/DQA_17 WCKA0_0/DQMA_0 C32 DQMA#1 MDB18 N4 DQB0_17/DQB_17 WCKB0_0/DQMB_0 H1 DQMB#1
MDA19 A26 DQA0_18/DQA_18 WCKA0B_0/DQMA_1 D23 DQMA#2 MDB19 P6 DQB0_18/DQB_18 WCKB0B_0/DQMB_1 T3 DQMB#2
MDA20 F24 DQA0_19/DQA_19 WCKA0_1/DQMA_2 E22 DQMA#3 MDB20 P5 DQB0_19/DQB_19 WCKB0_1/DQMB_2 T5 DQMB#3
MDA21 C24 DQA0_20/DQA_20 WCKA0B_1/DQMA_3 C14 DQMA#4 MDB21 R4 DQB0_20/DQB_20 WCKB0B_1/DQMB_3 AE4 DQMB#4
MDA22 A24 DQA0_21/DQA_21 WCKA1_0/DQMA_4 A14 DQMA#5 MDB22 T6 DQB0_21/DQB_21 WCKB1_0/DQMB_4 AF5 DQMB#5
MDA23 E24 DQA0_22/DQA_22 WCKA1B_0/DQMA_5 E10 DQMA#6 MDB23 T1 DQB0_22/DQB_22 WCKB1B_0/DQMB_5 AK6 DQMB#6
MDA24 C22 DQA0_23/DQA_23 WCKA1_1/DQMA_6 D9 DQMA#7 MDB24 U4 DQB0_23/DQB_23 WCKB1_1/DQMB_6 AK5 DQMB#7
MDA25 A22 DQA0_24/DQA_24 WCKA1B_1/DQMA_7 MDB25 V6 DQB0_24/DQB_24 WCKB1B_1/DQMB_7
DQA0_25/DQA_25 GDDR5/DDR2/GDDR3 QSA[7..0] <54> DQB0_25/DQB_25 GDDR5/DDR2/GDDR3 QSB[7..0] <55>
MDA26 F22 C34 QSA0 MDB26 V1 F6 QSB0
MDA27 D21 DQA0_26/DQA_26 EDCA0_0/QSA_0/RDQSA_0 D29 QSA1 MDB27 V3 DQB0_26/DQB_26 EDCB0_0/QSB_0/RDQSB_0 K3 QSB1
MDA28 A20 DQA0_27/DQA_27 EDCA0_1/QSA_1/RDQSA_1 D25 QSA2 MDB28 Y6 DQB0_27/DQB_27 EDCB0_1/QSB_1/RDQSB_1 P3 QSB2
MDA29 F20 DQA0_28/DQA_28 EDCA0_2/QSA_2/RDQSA_2 E20 QSA3 MDB29 Y1 DQB0_28/DQB_28 EDCB0_2/QSB_2/RDQSB_2 V5 QSB3
MDA30 D19 DQA0_29/DQA_29 EDCA0_3/QSA_3/RDQSA_3 E16 QSA4 MDB30 Y3 DQB0_29/DQB_29 EDCB0_3/QSB_3/RDQSB_3 AB5 QSB4
MDA31 E18 DQA0_30/DQA_30 EDCA1_0/QSA_4/RDQSA_4 E12 QSA5 MDB31 Y5 DQB0_30/DQB_30 EDCB1_0/QSB_4/RDQSB_4 AH1 QSB5
MDA32 C18 DQA0_31/DQA_31 EDCA1_1/QSA_5/RDQSA_5 J10 QSA6 MDB32 AA4 DQB0_31/DQB_31 EDCB1_1/QSB_5/RDQSB_5 AJ9 QSB6
MDA33 A18 DQA1_0/DQA_32 EDCA1_2/QSA_6/RDQSA_6 D7 QSA7 MDB33 AB6 DQB1_0/DQB_32 EDCB1_2/QSB_6/RDQSB_6 AM5 QSB7
DQA1_1/DQA_33 EDCA1_3/QSA_7/RDQSA_7 QSA#[7..0] <54> DQB1_1/DQB_33 EDCB1_3/QSB_7/RDQSB_7 QSB#[7..0] <55>
MDA34 F18 MDB34 AB1
MDA35 D17 DQA1_2/DQA_34 A34 QSA#0 MDB35 AB3 DQB1_2/DQB_34 G7 QSB#0
MDA36 A16 DQA1_3/DQA_35 DDBIA0_0/QSA_0B/WDQSA_0 E30 QSA#1 MDB36 AD6 DQB1_3/DQB_35 DDBIB0_0/QSB_0B/WDQSB_0 K1 QSB#1
MDA37 F16 DQA1_4/DQA_36 DDBIA0_1/QSA_1B/WDQSA_1 E26 QSA#2 MDB37 AD1 DQB1_4/DQB_36 DDBIB0_1/QSB_1B/WDQSB_1 P1 QSB#2
MDA38 D15 DQA1_5/DQA_37 DDBIA0_2/QSA_2B/WDQSA_2 C20 QSA#3 MDB38 AD3 DQB1_5/DQB_37 DDBIB0_2/QSB_2B/WDQSB_2 W4 QSB#3
MDA39 E14 DQA1_6/DQA_38 DDBIA0_3/QSA_3B/WDQSA_3 C16 QSA#4 MDB39 AD5 DQB1_6/DQB_38 DDBIB0_3/QSB_3B/WDQSB_3 AC4 QSB#4
MDA40 F14 DQA1_7/DQA_39 DDBIA1_0/QSA_4B/WDQSA_4 C12 QSA#5 MDB40 AF1 DQB1_7/DQB_39 DDBIB1_0/QSB_4B/WDQSB_4 AH3 QSB#5
MDA41 D13 DQA1_8/DQA_40 DDBIA1_1/QSA_5B/WDQSA_5 J11 QSA#6 MDB41 AF3 DQB1_8/DQB_40 DDBIB1_1/QSB_5B/WDQSB_5 AJ8 QSB#6
MDA42 F12 DQA1_9/DQA_41 DDBIA1_2/QSA_6B/WDQSA_6 F8 QSA#7 MDB42 AF6 DQB1_9/DQB_41 DDBIB1_2/QSB_6B/WDQSB_6 AM3 QSB#7
MDA43 A12 DQA1_10/DQA_42 DDBIA1_3/QSA_7B/WDQSA_7 MDB43 AG4 DQB1_10/DQB_42 DDBIB1_3/QSB_7B/WDQSB_7
MDA44 D11 DQA1_11/DQA_43 J21 ODTA0 MDB44 AH5 DQB1_11/DQB_43 T7 ODTB0
DQA1_12/DQA_44 ADBIA0/ODTA0 ODTA0 <54> DQB1_12/DQB_44 ADBIB0/ODTB0 ODTB0 <55>
MDA45 F10 G19 ODTA1 MDB45 AH6 W7 ODTB1
DQA1_13/DQA_45 ADBIA1/ODTA1 ODTA1 <54> DQB1_13/DQB_45 ADBIB1/ODTB1 ODTB1 <55>
MDA46 A10 MDB46 AJ4
MDA47 C10 DQA1_14/DQA_46 H27 CLKA0 MDB[0..63] MDB47 AK3 DQB1_14/DQB_46 L9 CLKB0
C CLKA0 <54> <55> MDB[0..63] CLKB0 <55> C
MDA48 G13 DQA1_15/DQA_47 CLKA0 G27 CLKA0# MDB48 AF8 DQB1_15/DQB_47 CLKB0 L8 CLKB0#
DQA1_16/DQA_48 CLKA0B CLKA0# <54> DQB1_16/DQB_48 CLKB0B CLKB0# <55>
MDA49 H13 MDB49 AF9
MDA50 J13 DQA1_17/DQA_49 J14 CLKA1 MAB[14..0] MDB50 AG8 DQB1_17/DQB_49 AD8 CLKB1
DQA1_18/DQA_50 CLKA1 CLKA1 <54> MAB[14..0] <55> DQB1_18/DQB_50 CLKB1 CLKB1 <55>
MDA51 H11 H14 CLKA1# MDB51 AG7 AD7 CLKB1#
DQA1_19/DQA_51 CLKA1B CLKA1# <54> B_BA[2..0] DQB1_19/DQB_51 CLKB1B CLKB1# <55>
MDA52 G10 MDB52 AK9
DQA1_20/DQA_52 B_BA[2..0] <55> DQB1_20/DQB_52
MDA53 G8 K23 RASA0# MDB53 AL7 T10 RASB0#
DQA1_21/DQA_53 RASA0B RASA0# <54> DQB1_21/DQB_53 RASB0B RASB0# <55>
MDA54 K9 K19 RASA1# MDB54 AM8 Y10 RASB1#
DQA1_22/DQA_54 RASA1B RASA1# <54> DQB1_22/DQB_54 RASB1B RASB1# <55>
MDA55 K10 MDB55 AM7
MDA56 G9 DQA1_23/DQA_55 K20 CASA0# MDB56 AK1 DQB1_23/DQB_55 W10 CASB0#
DQA1_24/DQA_56 CASA0B CASA0# <54> DQB1_24/DQB_56 CASB0B CASB0# <55>
MDA57 A8 K17 CASA1# MDB57 AL4 AA10 CASB1#
DQA1_25/DQA_57 CASA1B CASA1# <54> DQB1_25/DQB_57 CASB1B CASB1# <55>
MDA58 C8 MDB58 AM6
MDA59 E8 DQA1_26/DQA_58 K24 CSA0#_0 MDB59 AM1 DQB1_26/DQB_58 P10 CSB0#_0
DQA1_27/DQA_59 CSA0B_0 CSA0#_0 <54> DQB1_27/DQB_59 CSB0B_0 CSB0#_0 <55>
MDA60 A6 K27 MDB60 AN4 L10
MDA61 C6 DQA1_28/DQA_60 CSA0B_1 MDB61 AP3 DQB1_28/DQB_60 CSB0B_1
MDA62 E6 DQA1_29/DQA_61 M13 CSA1#_0 MDB62 AP1 DQB1_29/DQB_61 AD10 CSB1#_0
DQA1_30/DQA_62 CSA1B_0 CSA1#_0 <54> DQB1_30/DQB_62 CSB1B_0 CSB1#_0 <55>
MDA63 A5 K16 MDB63 AP5 AC10
DQA1_31/DQA_63 CSA1B_1 DQB1_31/DQB_63 CSB1B_1
+VDD_MEM15_REFDA L18 K21 CKEA0 U10 CKEB0
MVREFDA CKEA0 CKEA0 <54> CKEB0 CKEB0 <55>
+VDD_MEM15_REFSA L20 J20 CKEA1 +VDD_MEM15_REFDB Y12 AA11 CKEB1
MVREFSA CKEA1 CKEA1 <54> MVREFDB CKEB1 CKEB1 <55>
+VDD_MEM15_REFSB AA12
L27 K26 WEA0# MVREFSB N10 WEB0#
MEM_CALRN0 WEA0B WEA0# <54> WEB0B WEB0# <55>
N12 L15 WEA1# AB11 WEB1#
MEM_CALRN1 WEA1B WEA1# <54> WEB1B WEB1# <55>
AG12
MEM_CALRN2 DIS@
M12 H23 MAA13 RV133 1 2 TESTEN AD28 T8 MAB13
RV206 1 DIS@ 2 120_0402_1% M27 MEM_CALRP1 MAA0_8 J19 MAA14 5.11K_0402_1% TESTEN MAB0_8 W8 MAB14
AH12 MEM_CALRP0 MAA1_8 AK10 MAB1_8
GDDR5
MEM_CALRP2 AL10 CLKTESTA AH11
GDDR5
DRAM_RST#_R
CLKTESTB DRAM_RST
216-0833000-A11-THAMES-XT-M2_FCBGA962~D
216-0833000-A11-THAMES-XT-M2_FCBGA962~D VENUS@
VENUS@
B B
1
This basic topology should be used for DRAM_RST for DDR3/GDDR5.These @ @
CV218 CV219
Capacitors and Resistor values are an example only. The Series R and 0.1U_0402_16V7K 0.1U_0402_16V7K
2
|| Cap values will depend on the DRAM load and will have to be route 50ohms single-ended/100ohms diff
calculated for different Memory ,DRAM Load and board to pass Reset and keep short
1
Signal Spec. Debug only, for clock observation, if not needed, DNI
Place all these components very close to GPU (Within @ @ 5mil 5mil
RV136 RV137
25mm) and keep all component close to each Other (within 51.1_0402_1% 51.1_0402_1%
5mm) except Rser2
2
+1.35V_MEM_GFX
1
RV138
4.7K_0402_5% +1.35V_MEM_GFX +1.35V_MEM_GFX
@
2
1
RV141 RV142
40.2_0402_1% 40.2_0402_1%
+1.35V_MEM_GFX +1.35V_MEM_GFX 1 RV143 2 1 RV144 2 DRAM_RST#_R DIS@ DIS@
<54,55> DRAM_RST#
51.1_0402_1% 10_0402_1%
2
DIS@ DIS@
1
+VDD_MEM15_REFDB +VDD_MEM15_REFSB
2
RV139 RV140
1
1
DIS@ DIS@ CV222 RV145 CV223 CV224
120P_0402_50V9 4.99K_0402_1% RV148 0.1U_0402_16V7K RV149 0.1U_0402_16V7K
2
2
A +VDD_MEM15_REFDA +VDD_MEM15_REFSA DIS@ A
DIS@
2
1
CV220 CV221
RV146 0.1U_0402_16V7K RV147 0.1U_0402_16V7K
100_0402_1% DIS@ 100_0402_1% DIS@
2
DIS@ DIS@
2
K1 A1 ODTA0 K1 A1 K1 A1 ODTA1 K1 A1
<53> ODTA0 ODT VDDQ ODT VDDQ <53> ODTA1 ODT VDDQ ODT VDDQ
L2 A8 CSA0#_0 L2 A8 L2 A8 CSA1#_0 L2 A8
<53> CSA0#_0 CS VDDQ CS VDDQ <53> CSA1#_0 CS VDDQ CS VDDQ
J3 C1 RASA0# J3 C1 J3 C1 RASA1# J3 C1
<53> RASA0# RAS VDDQ RAS VDDQ <53> RASA1# RAS VDDQ RAS VDDQ
K3 C9 CASA0# K3 C9 K3 C9 CASA1# K3 C9
<53> CASA0# CAS VDDQ CAS VDDQ <53> CASA1# CAS VDDQ CAS VDDQ
QSA#[7..0] L3 D2 WEA0# L3 D2 L3 D2 WEA1# L3 D2
<53> QSA#[7..0] <53> WEA0# WE VDDQ WE VDDQ <53> WEA1# WE VDDQ WE VDDQ
E9 E9 E9 E9
VDDQ F1 VDDQ F1 VDDQ F1 VDDQ F1
QSA3 F3 VDDQ H2 QSA2 F3 VDDQ H2 QSA5 F3 VDDQ H2 QSA4 F3 VDDQ H2
QSA0 C7 DQSL VDDQ H9 QSA1 C7 DQSL VDDQ H9 QSA6 C7 DQSL VDDQ H9 QSA7 C7 DQSL VDDQ H9
DQSU VDDQ DQSU VDDQ DQSU VDDQ DQSU VDDQ
C C
DQMA#3 E7 A9 DQMA#2 E7 A9 DQMA#5 E7 A9 DQMA#4 E7 A9
DQMA#0 D3 DML VSS B3 DQMA#1 D3 DML VSS B3 DQMA#6 D3 DML VSS B3 DQMA#7 D3 DML VSS B3
DMU VSS E1 DMU VSS E1 DMU VSS E1 DMU VSS E1
VSS G8 VSS G8 VSS G8 VSS G8
QSA#3 G3 VSS J2 QSA#2 G3 VSS J2 QSA#5 G3 VSS J2 QSA#4 G3 VSS J2
QSA#0 B7 DQSL VSS J8 QSA#1 B7 DQSL VSS J8 QSA#6 B7 DQSL VSS J8 QSA#7 B7 DQSL VSS J8
DQSU VSS M1 DQSU VSS M1 DQSU VSS M1 DQSU VSS M1
VSS M9 VSS M9 VSS M9 VSS M9
VSS P1 VSS P1 VSS P1 VSS P1
T2 VSS P9 DRAM_RST# T2 VSS P9 DRAM_RST# T2 VSS P9 DRAM_RST# T2 VSS P9
<53,55> DRAM_RST# RESET VSS RESET VSS RESET VSS RESET VSS
T1 T1 T1 T1
L8 VSS T9 L8 VSS T9 L8 VSS T9 L8 VSS T9
ZQ VSS ZQ VSS ZQ VSS ZQ VSS
1
1
J1 B1 J1 B1 J1 B1 J1 B1
RV150 L1 NC VSSQ B9 RV151 L1 NC VSSQ B9 RV152 L1 NC VSSQ B9 RV153 L1 NC VSSQ B9
J9 NC VSSQ D1 J9 NC VSSQ D1 J9 NC VSSQ D1 J9 NC VSSQ D1
240_0402_1% 240_0402_1% 240_0402_1% 240_0402_1%
VENUS@ L9 NC VSSQ D8 VENUS@ L9 NC VSSQ D8 VENUS@ L9 NC VSSQ D8 VENUS@ L9 NC VSSQ D8
M7 NC VSSQ E2 M7 NC VSSQ E2 M7 NC VSSQ E2 M7 NC VSSQ E2
2
2
NC VSSQ E8 NC VSSQ E8 NC VSSQ E8 NC VSSQ E8
VSSQ F9 VSSQ F9 VSSQ F9 VSSQ F9
VSSQ G1 VSSQ G1 VSSQ G1 VSSQ G1
VSSQ G9 VSSQ G9 VSSQ G9 VSSQ G9
VSSQ VSSQ VSSQ VSSQ
96-BALL 96-BALL 96-BALL 96-BALL
SDRAM DDR3L SDRAM DDR3L SDRAM DDR3L SDRAM DDR3L
VENUS@ K4W2G1646E-BC11_FBGA96~D K4W2G1646E-BC11_FBGA96~D K4W2G1646E-BC11_FBGA96~D K4W2G1646E-BC11_FBGA96~D
CLKA0 1 2
RV154 56_0402_1%
VENUS@
CLKA0# 1 2
RV155 56_0402_1%
1
CV225
0.01U_0402_16V7K
VENUS@ +1.35V_MEM_GFX +1.35V_MEM_GFX +1.35V_MEM_GFX +1.35V_MEM_GFX +1.35V_MEM_GFX +1.35V_MEM_GFX +1.35V_MEM_GFX +1.35V_MEM_GFX
B B
2
1
RV156 RV157 RV158 RV159 RV160 RV161 RV162 RV163
4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1%
VENUS@ VENUS@ VENUS@ VENUS@ VENUS@ VENUS@ VENUS@ VENUS@
VENUS@
15mil 15mil 15mil 15mil 15mil 15mil 15mil 15mil
2
2
CLKA1 1 2
RV164 56_0402_1% VREFD_Q1 VREFC_A1 VREFC_A2 VREFD_Q2 VREFC_A3 VREFD_Q3 VREFC_A4 VREFD_Q4
1
1
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
VENUS@
VENUS@
VENUS@
VENUS@
VENUS@
VENUS@
VENUS@
VENUS@
VENUS@
1
1
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
CLKA1# 1 2 RV166 RV167 RV168 RV169 RV170 RV171 RV172 RV173
CV226
CV227
CV228
CV229
CV230
CV231
CV232
CV233
RV165 56_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1%
1
2
0.01U_0402_16V7K
2
2
VENUS@
2
+1.35V_MEM_GFX
+1.35V_MEM_GFX
+1.35V_MEM_GFX +1.35V_MEM_GFX
CV235
CV236
CV237
CV238
CV239
CV240
CV241
CV242
CV243
CV244
CV245
CV246
CV247
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
CV248
CV249
CV250
CV251
CV252
CV253
CV254
CV255
CV256
CV257
CV258
CV259
CV260
CV261
CV262
CV263
CV264
CV265
CV266
CV267
CV268
CV269
CV270
CV271
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
2 2 2 2 2 2 2 2 2 2 2 2 2
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2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
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A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ATI_Sun XT_M2_VRAM_A
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-9981P
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Saturday, March 09, 2013 Sheet 54 of 55
5 4 3 2 1
5 4 3 2 1
K1 A1 ODTB0 K1 A1 K1 A1 ODTB1 K1 A1
<53> ODTB0 ODT VDDQ ODT VDDQ <53> ODTB1 ODT VDDQ ODT VDDQ
L2 A8 CSB0#_0 L2 A8 L2 A8 CSB1#_0 L2 A8
<53> CSB0#_0 CS VDDQ CS VDDQ <53> CSB1#_0 CS VDDQ CS VDDQ
J3 C1 RASB0# J3 C1 J3 C1 RASB1# J3 C1
<53> RASB0# RAS VDDQ RAS VDDQ <53> RASB1# RAS VDDQ RAS VDDQ
K3 C9 CASB0# K3 C9 K3 C9 CASB1# K3 C9
<53> CASB0# CAS VDDQ CAS VDDQ <53> CASB1# CAS VDDQ CAS VDDQ
L3 D2 WEB0# L3 D2 L3 D2 WEB1# L3 D2
<53> WEB0# WE VDDQ WE VDDQ <53> WEB1# WE VDDQ WE VDDQ
E9 E9 E9 E9
VDDQ F1 VDDQ F1 VDDQ F1 VDDQ F1
DIS@ QSB2 F3 VDDQ H2 QSB3 F3 VDDQ H2 QSB6 F3 VDDQ H2 QSB4 F3 VDDQ H2
CLKB0 1 2 QSB0 C7 DQSL VDDQ H9 QSB1 C7 DQSL VDDQ H9 QSB5 C7 DQSL VDDQ H9 QSB7 C7 DQSL VDDQ H9
RV174 56_0402_1% DQSU VDDQ DQSU VDDQ DQSU VDDQ DQSU VDDQ
C C
DIS@ DQMB#2 E7 A9 DQMB#3 E7 A9 DQMB#6 E7 A9 DQMB#4 E7 A9
CLKB0# 1 2 DQMB#0 D3 DML VSS B3 DQMB#1 D3 DML VSS B3 DQMB#5 D3 DML VSS B3 DQMB#7 D3 DML VSS B3
RV175 56_0402_1% DMU VSS E1 DMU VSS E1 DMU VSS E1 DMU VSS E1
VSS G8 VSS G8 VSS G8 VSS G8
VSS VSS VSS VSS
1
1
CLKB1 1 2 J1 B1 J1 B1 J1 B1 J1 B1
RV180 56_0402_1% RV176 L1 NC VSSQ B9 RV177 L1 NC VSSQ B9 RV178 L1 NC VSSQ B9 RV179 L1 NC VSSQ B9
J9 NC VSSQ D1 J9 NC VSSQ D1 J9 NC VSSQ D1 J9 NC VSSQ D1
240_0402_1% 240_0402_1% 240_0402_1% 240_0402_1%
DIS@ DIS@ L9 NC VSSQ D8 DIS@ L9 NC VSSQ D8 DIS@ L9 NC VSSQ D8 DIS@ L9 NC VSSQ D8
CLKB1# 1 2 M7 NC VSSQ E2 M7 NC VSSQ E2 M7 NC VSSQ E2 M7 NC VSSQ E2
2
2
RV181 56_0402_1% NC VSSQ E8 NC VSSQ E8 NC VSSQ E8 NC VSSQ E8
VSSQ VSSQ VSSQ VSSQ
1
CV273 F9 F9 F9 F9
0.01U_0402_16V7K VSSQ G1 VSSQ G1 VSSQ G1 VSSQ G1
DIS@ VSSQ G9 VSSQ G9 VSSQ G9 VSSQ G9
2
1
RV182 RV183 RV184 RV185 RV186 RV187 RV188 RV189
4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1%
DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@
15mil 15mil 15mil 15mil 15mil 15mil 15mil 15mil
2
2
VREFD_Q1_B VREFC_A1_B VREFC_A2_B VREFD_Q2_B VREFC_A3_B VREFD_Q3_B VREFC_A4_B VREFD_Q4_B
CV274
CV275
CV276
CV277
CV278
CV279
CV280
CV281
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
1
1
1 1 1 1 1 1 1 1
RV190 RV191 RV192 RV193 RV194 RV195 RV196 RV197
4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1%
DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@
2 2 2 2 2 2 2 2
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
2
2
+1.35V_MEM_GFX
+1.35V_MEM_GFX
+1.35V_MEM_GFX +1.35V_MEM_GFX
CV282
CV283
CV284
CV285
CV286
CV287
CV288
CV289
CV290
CV291
CV292
CV293
CV294
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
CV295
CV296
CV297
CV298
CV299
CV300
CV301
CV302
CV303
CV304
CV305
CV306
CV307
CV308
CV310
CV311
CV312
CV313
CV314
CV315
CV316
CV317
CV318
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
2 2 2 2 2 2 2 2 2 2 2 2 2
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ATI_Sun XT_M2_VRAM_B
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-9981P
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Saturday, March 09, 2013 Sheet 55 of 55
5 4 3 2 1
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