Pioc IEkh 1998 Int Confcieiice on Microelectionic Ieit S(riiLtuiei, Vol 1 I , M a c h 1998 13

New Method for Monitoring of Analogue Processes - Evaluation of the Impact of Metalisation on the Performance of

A. Pergoot, P. Cox, P. Vercruysse, 1. Wuyts, P. Raes*

Alcatel Mietec Campus BME - CTL*

Westerring 15 Scoonmeersstraat 52
9700 Oudenaarde 9000 Gent
Belgium Belgium

Phone : +32 55 33 27 75
Fax: +32 55 31 81 12
e-mail: pavercruysse@mietec.be

Abstract - The hi olycristalline (HIPO) resistor In submicron technologies, due to the decreased
thermal process budget, it becomes more difficult to control
the resistor parameters.

It appears also, that in difierent metalisation

schemes, the influence of metal lines in the neighbourhood
of tuned resistors on parameters such as matching and resis-
tance value, can vary. It’s one of the reasons that the values
of the parameters measured on dedicated test structures
drastically differ from those measured in the actual circuits.
It makes the design and process targeting very difficult.
This paper describes a new type of test structure
with information on the component parameters. This struc-
ture provides the possibility for accurate monitoring of the
analog performance of the production line and for evaluation
of the process and topology influence on resistor parame-
ters.

The most interesting and significant impact, that

of the metal, is reported for different metalisation schemes.
It’s shown that the process optiinisation towards analog
INTRODUCTION 1 performance can differ from the pure digital approach. A
brief physical explanation of the phenomenon is given at
the end.
of IC devices is critical for
lications. Most of the recent
performance of matched tran-
many applications such as
matching properties of high-
(HIPO) for obtaining a high-
eters, sheet resistance, match-
well characterised for obtaining
s. A constant process control in
arameters has to established.

0-7803-4348-4/98/$I O.(b001998 IEEE 98CH36157

 rate sense pad was used to connect the reference of the V-
TEST METHODOLOGY meter.

The floorplan in figure 2 illustrates that the same

To determine useful resistor parameters it is neces- basic test structure is used 4 times within a standard bond
sary to extract these from a test structure which is represen- pad layout.
tative of "real life conditions".
Therefore, a resistive bank is copied from an exist-
ing DAC. The classic way to measure a resistor is to force
a current Im through and to measure the voltage Vr across
the resistor. In this case a significant error will be made
Mm
because the measured Vr includes the voltage drop over the
interconnect. A solution for this is the use of the 4 points
measurement method. Assuming that the voltmeter imped-
ance is infinite there will be no voltage drop in the connec- c07-061
tion between V-meter and resistor. The permanent connec-
tion between resistor and current sourceholtmeter is
changed to a switch as shown in figure 1.

I r
I
I 1
I
I _- lwafer flat I
---vout

Figure 2
Test block - floor plan

The different test structures are adapted to evaluate

the influence of metal 1, metal 2, the distance to the scribe

bh 1 1 --
lane and the orientation of the resistors in respect to the
flat.

EXPERIMENTAL
Figure 1
Test structure - schematic view

A control signal derived fiom a shift register
closes the switches to probe the corresponding resistor.
This control signal is programmed by an ATE (automatic
test equipment) writing a single one in the first register.
After each clock pulse this "one" is further propagated.
After 30 pulses the last resistor is addressed.
The tester also supplies a current source that is
connected to the common current input pad. A high resolu-
tion V-meter is used to measure the voltage on the com-
mon output pad. The ground connection is common, but
care must be taken for the layout. Each resistor sees the
same number of metal squares used for the interconnect. T o
reduce the influence of the voltage drop due to the contact
resistance between probe needle and the probe pad, a sepa-
The process employed is the mixed signal ana-
logue-digital double level metal CMOS 0.7pm process,
providing HIP0 resistors with a nominal sheet resistance
value of 2 Kohm/sq.
A process matrix containing different metalisation
schemes is characterised. This matrix is based mainly on
the combination between metals with and without Ti bar-
rier layer. The impact of the last high-temperature annealing
step is also investigated.
Two process schemes, given in table 1 are evaluated.
 I 15

Table 1 This means that for parallel, equally designed re-

sistors with W/L=10/200ym a maximum mismatching of
0.1 1% is expected.
rocess
METAL 1 I From the design point of view the most interest-
barrier TiiTiNITi 1 bes yes ing question is - How close the metal routing line can be
placed from the matched couple or resistor, without influ-
encing the resistance value and the matching.
The process splits are compared using the follow-
ing criteria:

- matching and resistance of the resistor Nrl5,

considered as a reference
I SINTER I DO min I 90 min - minimum distance to resistor Nr 8(covered
with minimum width metal) where the match-
ing remains in the specifications
The following test majrix is explored. - minimum distance to resistor Nr 23(completely
covered with wide metal) where the matching re

P
Ex erimental matrix
mains in the specifications.

When the metal line can be placed on the adjacent

resistor or dummy, the distance is set at the minimum al-
split nr met41 1 metal 2 sinter lowed 2ym.
split 1 P1 PI P1
split 2 P2 P2 P1
I P2 RESULTS
split 3 I P2 I P2
split 4 I P2 I PI I PI

Table 3 shows the results for different process

Of the resistance and the
splits, including the matching values and the distances for
“matching on target” to metal 1 lines.
two next to each

i
other positioned resis ors, e.g. Rl/R2, R2IR3 etc.. The
matching is calculated as :

~
Table 3
Impact of metal 1 lines on resistance matching

I split I matching[%lof I distance to I distance to I

I3
The matchin values are normally distributed.
The mean and the sta dard deviation are used for evalua- I 0.03+0.06
tion of the systematic and the stochastic matching effects,
respectively. For the iven CMOS0.7yrr technology, the
following model is va id :
The same tendency is found for the resistance
value.
-
02Ry/o ‘1 = +0.073 It’s obvious that a Ti layer with a thickness of
Fe 20nm has no significant impact on the performance of the
HIP0 resistors. It means that it’s possible to use the metal
1 as a routing metal, placing it on top of the adjacent
dummy resistor. Placing the metal 1 on top of one the two
where s and p are esti standard deviation and resistors in the couple causes a significant shift in the
mean, W and L are th and length of the resis- matching performance which is not acceptable.
tor.
16

Metal2
The matching performance is affected by the pres-
The impact of metal-2 is much stronger if a thick ence of metal 2 containing the Ti barrier. This effect is
(1 OOnm) Ti layer is used as a barrier. shown in figures 5 and 6 for splits 1 and 4 respectively.
In table 4 the values of the sheet resistances are
given in the different splits. Metal 2 impact on r n a t c h i n g

Table 4
2.5
Impact of different metalisation on the sheet resistance val-
ues
1+ 0 . 3 5
*\
1.5

I Rsh Nr.15 I Rsh Nr.8 I Rsh Nr.23 I 1

O.I5 Matching [%I
I I I 0.1

II
0.5
rOhm1 [Ohm] [Ohm] 0.05
1 I 168Sk23 I 1683S3 I 1683+23 0 0

12 I 1617S4 I 1607f24 I 1727S9 1 1 0 9 0 70 5 0 3 0 1 0

3 I 1655+28 I 1643228 I 1735k27 Distance [urn]

4 I 1693f27 I 1694-127 I 1692+27

Figure 5
The influence is demonstrated also in figure 3 and Metal-2 impact on matching for split 1
4. The mean and the standard deviation over 324 resistors
per position are shown for split 1 and split 4 respectively.
Metal 2 impact on matching

Metal 2 impact on resistance value

0 45
34 _____________I 0.58 2.5
0 4
0.56
33.5 2 0.35
0.54

32.5
33 0.52
0.5
0.48
1- 1.5

1
:':5
02
1-
32
0.46 Rstdev[Kohml
0 5
0 15 Matching [%I
0.44
01
3 1 . 5 -k04.2 0
0 05
,1090 70 50 30 10
-0.5 0
distance [um]
Distance [um]

Figure 6
Metal-2 impact on matching for split 4
Figure 3
It was also found that by increasing the sinter an-
Metal-2 impact on HIPO resistance for split 1
neal time there is no significant improvement in the match-
ing performance and the resistance unifonnity.
Metal 2 impact on resistance value for The impact of metal 2 remains significant for dis-
split 4 tances up-to 10Opm which is intolerable for design pur-
nFi
Ir,
poses.
34.; 4
34 0.56
33.5 0.54
33
32.5
DISCUSSION
32
31 5 0.46
31 0.44 Rsldev [Kohm]
30.5 0.42 The metal 2 contains a thick layer of Ti/TiN as a
30 0.4 bottom barrier layer.
llaojO 8070605040302010 The hydrogen released during the final sinter an-
Distance [um] neal is intended to saturate interface states in the MOS tran-
sistors and dangling bonds in the grain boundaries in the
HIPO.
Figure 4
Metal-2 impact on HIPO resistance for split 4
 F:
By using th new test structure we are able , in a
very early phase, to ualifL the impact of new processes
and technologies on t e analogue performance. It allows us
to check the existing atching models as a function of the
circuit topology and eta1 surrounding the precision ana-
logue elements.

i
The impact of parallel to HIP0 metal lines is
characterised as a fun tion of the metalisation schemes and
the distance between he metal line and HIPO resistor.
The impact of the Ti arrier layer under metal-1 and metal-
2, and the duration o the last annealing step are extensively
characterised.

i is found to have the most sig-

logue performance of HIPO resis-
ant change of the carrier distribu-
ching performance and resistance
e a drastic yield drop on analogue

M CMOS technology
digital and analogue
combination of proc-

References: I

, 1995, pp. 376.

pp. 735