LECTUREX

6.
012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 2-1
Lecture 2 - Semiconductor Physics (I)
September 13, 2005
Contents:
1. Silicon bond model: electrons and holes

2. Generation and recombination
3. Thermal equilibrium
4. Intrinsic semiconductor
5. Doping; extrinsic semiconductor
Reading assignment:
Howe and Sodini, Ch. 2, §§2.1-2.3

6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 2-2
Key questions
• How do semiconductors conduct electricity?
• What is a ”hole”?
• How many electrons and holes are there in a semicon-
ductor in thermal equilibrium at a certain tempera-
ture?
• How can one engineer the conductivity of semicon-
ductors?
1. Silicon bond model: electrons and holes
Si is in Column IV of periodic table:
IIIA IVA VA VIA

5 6 7 8
B C N O
13 14 15 16
IIB Al Si P S
30 31 32 33 34
Zn Ga Ge As Se
48 49 50 51 52
Cd In Sn Sb Te
Electronic structure of Si atom:

• 10 core electrons (tightly bound)
• 4 valence electrons (loosely bound, responsible for most
chemical properties)
Other semiconductors:
• Ge, C (diamond form), SiGe
• GaAs, InP, InGaAs, InGaAsP, ZnSe, CdTe
(on average, 4 valence electrons per atom)
Silicon crystal structure:
°
5.43 A
°
2.35A
3sp tetrahedral bond
• Silicon is a crystalline material:

– long range atomic arrangement
• Diamond lattice:
– atoms tetrahedrally bonded by sharing valence elec-
trons (covalent bonding)
• Each atom shares 8 electrons:
– low energy and stable situation
• Si atomic density: 5 × 1022 cm−3
density:
Simple ”flattened” model of Si crystal:
4 valence electrons (– 4 q),
contributed by each ion
silicon ion (+ 4 q)
two electrons in bond
At 0K:
• all bonds satisfied → all valence electrons engaged in

bonding
• no ”free” electrons
At finite temperature:
+ mobile electron
incomplete bond (mobile hole)
• finite thermal energy

• some bonds are broken
6×110−
• ”free” electrons (mobile negative charge, −1.6
−1.6×10 −19
19
C
C)
• ”free” holes (mobile positive charge, 1.6 × 100−19
1
C)
”Free” electrons and holes are called carriers:
• mobile charged particles
Beware: picture is misleading!
• electrons and holes in semiconductors are ”fuzzier”:

they span many atomic sites.
A few definitions:
• in 6.012, ”electron” means free electron
• not concerned with bonding electrons or core electrons
• define:
n ≡ (free) electron concentration [cm−3 ]
p ≡ hole concentration [cm−3 ]

2. Generation and Recombination
Generation = break up of covalent bond to form elec-

tron and hole
• requires energy from thermal or optical sources (or
other external sources)

• generation rate: G = Gth + Gopt + ... [cm−3 · s
−1]
• in general, atomic density n, p ⇒
G = f (n, p)
– supply of breakable bonds virtually inexhaustible
Recombination = formation of bond by bringing to-

gether electron and hole
• releases energy in thermal or optical form
• recombination rate: R [cm−3 · s−1 ]
• a recombination event requires 1 electron + 1 hole ⇒

R ∝ n · p
Generation and recombination most likely at surfaces where

periodic crystalline structure is broken.
3. Thermal equilibrium
Thermal equilibrium =
steady state + absence of external energy sources
hυ
δ<θ>
=0
δt
• Generation rate in thermal equilibrium: Go = f (T )
• Recombination rate in thermal equilibrium: Ro ∝ no ·po
In thermal equilibrium:
Go = Ro ⇒ no po = f (T ) ≡ n2i (T )
Important consequence:
In thermal equilibrium and for a given semiconduc-

tor, np product is a constant that depends only on
temperature!
Electron-hole formation can be seen as chemical reaction:
e− + h+
bond
similar to water decomposition reaction:
H + + OH −
H2 O
Law-of-mass action relates concentration of reactants

and reaction products. For water:
[H +][OH − ]
K=
[H2 O]
Since:
[H2O] [H +], [OH − ]
Then:
[H2 O] constant
Hence:
[H +][OH − ] constant
4. Intrinsic semiconductor
Question: In a perfectly pure semiconductor in thermal

equilibrium at finite temperature, how many electrons
and holes are there?
Since when a bond breaks, an electron and a hole are

produced:
no = po
Also:
nopo = n2i
Then:
no = po = ni
ni ≡ intrinsic carrier concentration [cm−3 ]
×11010 cm−3
In Si at 300 K (”room temperature”): ni 11×
ni very strong function of temperature: T ↑ → ni ↑
Note: an intrinsic semiconductor need not be perfectly

pure [see next]
5. Doping: introduction of foreign atoms to engineer

semiconductor electrical properties
A. Donors: introduce electrons to the semiconductor

(but not holes)
• For Si, group-V atoms with 5 valence electrons (As,

P, Sb)
IIIA IVA VA VIA

5 6 7 8
B C N O
13 14 15 16
IIB Al Si P S
30 31 32 33 34
Zn Ga Ge As Se
48 49 50 51 52
Cd In Sn Sb Te
• 4 electrons of donor atom participate in bonding
• 5th electron easy to release

– at room temperature, each donor releases 1 elec-
tron that is available for conduction
• donor site become positively charged (fixed charge)
As+
mobile electron
immobile ionized donor
Define:
Nd ≡ donor concentration [cm−3 ]
• If Nd ni, doping irrelevant

(intrinsic semiconductor) → no = po = ni
• If Nd ni, doping controls carrier concentrations

(extrinsic semiconductor) →
n2i
no = Nd po =
Nd
Note: no po: n
n-typ
-type
- e semiconductor
Example:
Nd = 1017 cm−3 → no = 1017 cm−3 , po = 103 cm−3 .
In general: Nd ∼ 1015 − 1020 cm−3

log no
log po
electrons=
no majority carriers
ni
po holes=
minority carriers
ni
log Nd
intrinsic extrinsic
Chemical reaction analogy:

dissolve a bit of KOH into water ⇒ [OH − ] ↑, [H +] ↓
B. Acceptors: introduce holes to the semiconductor

(but not electrons)
• For Si, group-III atoms with 3 valence electrons (B)
IIIA IVA VA VIA

5 6 7 8
B C N O
13 14 15 16
IIB Al Si P S
30 31 32 33 34
Zn Ga Ge As Se
48 49 50 51 52
Cd In Sn Sb Te
• 3 electrons used in bonding to neighboring Si atoms
• 1 bonding site ”unsatisfied”:

– easy to ”accept” neighboring bonding electron to
complete all bonds
– at room temperature, each acceptor releases 1 hole
that is available to conduction
• acceptor site become negatively charged (fixed charge)
B–
mobile hole and later trajectory immobile negatively ionized acceptor
Define:
Na ≡ acceptor concentration [cm−3 ]
• If Na ni , doping irrelevant
(intrinsic semiconductor) → no = po = ni
• If Na ni , doping controls carrier concentrations

(extrinsic semiconductor) →
n2i
po = Na no =
Na
Note: po no: p-type
p-type semiconductor
Example:
Na = 1016 cm−3 → po = 1016 cm−3 , no = 104 cm−3 .
In general: Na ∼ 1015 − 1020 cm−3

log no
log po
holes=
po majority carriers
ni
no electrons=
minority
ty carr
ccarriers
arriers
ni
log Na
intrinsic extrinsic
Chemical reaction analogy:

dissolve a bit of H2SO4 into water ⇒ [H +] ↑, [OH − ] ↓
Summary
• In a semiconductor, there are two types of ”carriers”:

electrons and holes
• In thermal equilibrium and for a given semiconductor
nopo is a constant that only depends on temperature:
nopo = n2i
• For Si at room temperature:
ni 1010 cm−3
• Intrinsic semiconductor: ”pure” semiconductor.
no = po = ni
• Carrier concentrations can be engineered by addition
of ”dopants” (selected foreign atoms):
– n-type semiconductor:
n2i
no = Nd, po =
Nd
– p-type semiconductor:
n2i
po = Na, no =
Na
Lecture 3 - Semiconductor Physics (II)
Carrier Transport
September 15, 2005
Contents:
1. Thermal motion
2. Carrier drift
3. Carrier diffusion
Reading assignment:

Key questions
• What are the physical mechanisms responsible for cur-

rent flow in semiconductors?
• How do electrons and holes in a semiconductor behave
in an electric field?
• How do electrons and holes in a semiconductor behave
if their concentration is non-uniform in space?
1. Thermal Motion
In thermal equilibrium, carriers are not sitting still:
• undergo collisions with vibrating Si atoms (Brownian

motion)
• electrostatically interact with charged dopants and
with each other
Characteristic time constant of thermal motion - mean

free time between collisions:
τc ≡ collision time [s]
In between collisions, carriers acquire high velocity:
vth ≡ thermal velocity [cm/s]
...but get nowhere!

Characteristic length of thermal motion:
λ ≡ mean free path [cm]
λ = vthτc
Put numbers for Si at 300 K:
τc 10−14 ∼ 10−13 s
vth 107 cm/s
⇒ λ 1 ∼ 10 nm
For reference, state-of-the-art MOSFETs today:
Lg 0.1 µm
⇒ carriers undergo many collisions in modern devices
2. Carrier Drift
Apply electric field to semiconductor:
E ≡ electric field [V /cm]
⇒ net force on carrier
F = ±qE
Between collisions, carriers accelerate in direction of field:
v(t) = at = − m
qE
n
t for electrons
qE
v(t) = mp
t for holes
But velocity randomized every τc (on average):
net velocity
in direction τc
of field
average
net velocity
time
Then, average net velocity in direction of field:
qE qτc
v = vd = ± τc = ± E
2mn,p 2mn,p
velocity
This is called drift velocity [cm/s].
Define:
µn,p = qτc
2mn,p ≡ mobility [cm2 /V · s]
Then, for electrons:

vdn = −µnE
for holes:
vdp = µp E
Mobility is measure of ease of carrier drift:

• if τc ↑, longer time between collisions → µ ↑
• if m ↓, ”lighter” particle → µ ↑
Mobility depends on doping. For Si at 300K:
1400
1200
electrons
1000
mobility (cm2/Vs)
800
600
holes
400
200
0
1013 1014 1015 1016 1017 1018 1019 1020
Nd + Na total dopant concentration (cm−3)
• for low doping level, µ limited by collisions with lattice
• for medium and high doping level, µ limited by colli-

sions with ionized impurities
• holes ”heavier” than electrons:
→ for same doping level, µn > µp
Drift current
Net velocity of charged particles ⇒ electric current:
Drift current density ∝ carrier drift velocity

∝ carrier concentration
∝ carrier charge
Drift currents:
Jndrif t = −qnvdn = qnµn E
Jpdrif t = qpvdp = qpµp E
Check signs:
E E
vdn vdp
- +
Jndrift Jpdrift
x x
Total drift current:
J drif t = Jndrif t + Jpdrif t = q(nµn + pµp )E
Has the shape of Ohm’s Law:
E
J = σE =
ρ
Where:
σ ≡ conductivity [Ω−1 · cm−1 ]
ρ ≡ resistiviy [Ω · cm]
Then:
1 1
ρ= =
σ q(nµn + pµp )
Resistivity commonly used to specify doping level.
• In n-type semiconductor:
1
ρn
qNdµn
• In p-type semiconductor:
1
ρp
qNaµp
For Si at 300K:
1E+4
1E+3
1E+2
Resistivity (ohm.cm)
1E+1
p-Si
1E+0
n-Si
1E-1
1E-2
1E-3
1E-4
1E+12 1E+13 1E+14 1E+15 1E+16 1E+17 1E+18 1E+19 1E+20 1E+21
Doping (cm-3)
Numerical example:
• Si with Nd = 3 × 1016 cm−3 at 300 K
µn 1000 cm2/V · s
ρn 0.21 Ω · cm
• apply |E| = 1 kV /cm
|vdn| 106 cm/s vth
|Jndrif t | 4.8 × 103 A/cm2
• time to drift through L = 0.1 µm:
L
td = = 10 ps
vdn
fast!
3. Carrier diffusion
Diffusion: particle movement in response to concentration

gradient.
Elements of diffusion:
• a medium (Si crystal)
• a gradient of particles (electrons and holes) inside

the medium
• collisions between particles and medium send particles
off in random directions:
→ overall, particle movement down the gradient
Key diffusion relationship (Fick’s first law):
Diffusion flux ∝ - concentration gradient
Flux ≡ number of particles crossing unit area per unit

time [cm−2 · s−1]
For electrons:
dn
Fn = −Dn
dx
For holes:
dp
Fp = −Dp
dx
Dn ≡ electron diffusion coefficient [cm2 /s]

Dp ≡ hole diffusion coefficient [cm2 /s]
D measures the ease of carrier diffusion in response to a

concentration gradient: D ↑ ⇒ F dif f ↑.
D limited by vibrating lattice atoms and ionized dopants
Diffusion current density = charge × carrier flux
dn
Jndif f = qDn
dx
dp
Jpdif f = −qDp
dx
Check signs:
n p
Fn Fp
Jndiff Jpdiff
x x
Einstein relation
At the core of diffusion and drift is same physics: collisions

among particles and medium atoms
⇒ there should be a relationship between D and µ
Einstein relation [don’t derive in 6.012]:

D kT
=
µ q
In semiconductors:
Dn Dp kT
= =
µn µp q
kT
q
≡ thermal voltage [V ]
At 300 K:
kT
25 mV
q
For example: for Nd = 3 × 1016 cm−3 :
µn 1000 cm2/V · s → Dn 25 cm2/s

µp 400 cm2/V · s → Dp 10 cm2 /s
Total current
In general, current can flow by drift and diffusion sepa-

rately. Total current:
dn
Jn = Jndrif t + Jndif f = qnµn E + qDn
dx
dp
Jp = Jpdrif t + Jpdif f = qpµp E − qDp
dx
And
Jtotal = Jn + Jp
Summary: relationship between v, F , and J
In semiconductors: charged particles move

⇒ particle flux ⇒ electrical current density
Particle flux: number of particles that cross surface of
unit area placed normal to particle flow every unit time
Fn
vn dt
Relationship between particle flux and velocity:
Fn = nvn Fp = pvp
Current density: amount of charge that crosses surface

of unit area placed normal to particle flow every unit time
Jn = −qFn = −qnvn Jp = qFp = qpvp
whether carriers move by drift or diffusion.

Key conclusions
• Electrons and holes in semiconductors are mobile and

charged ⇒ carriers of electrical current!
• Drift current: produced by electric field
J drif t ∝ E
• Diffusion current: produced by concentration gradi-

ent
dn dp
J dif f ∝ ,
dx dx
• Carriers move fast in response to fields and gradients
• Diffusion and drift currents are sizable in modern de-

vices
Lecture 4 - PN Junction and MOS
Electrostatics (I)
Semiconductor Electrostatics
in Thermal Equilibrium
September 20, 2005
Contents:
1. Non-uniformly doped semiconductor in thermal equi-

librium
2. Quasi-neutral situation
3. Relationships between φ(x) and equilibrium carrier

concentrations (Boltzmann relations), ”60 mV Rule”
Reading assignment:
Key questions
• Is it possible to have an electric field inside a semicon-

ductor in thermal equilibrium?
• If there is a doping gradient in a semiconductor, what
is the resulting majority carrier concentration in ther-
mal equilibrium?
1. Non-uniformly doped semiconductor in ther-

mal equilibrium
Consider first uniformly doped n-type Si in thermal equi-

librium:
Nd
Nd(x)=Nd
n-type ⇒ lots of electrons, few holes
⇒ focus on electrons
no = Nd independent of x
Volume charge density [C/cm3 ]:
ρ = q(Nd − no) = 0
Next, consider piece of n-type Si in thermal equilibrium

with non-uniform dopant distribution:
Nd
Nd(x)
What is the resulting electron concentration in thermal

equilibrium?
Option 1: Every donor gives out one electron ⇒
no(x) = Nd(x)
no, Nd
Nd(x) no(x)=Nd(x)?
Gradient of electron concentration:
⇒ net electron diffusion

⇒ not thermal equilibrium!
Option 2: Electron concentration uniform in space:
f (x)
no = nave =
no, Nd
Nd(x)
no = f(x)?
Think about space charge density:
ρ(x) = q[Nd(x) − no(x)]
If Nd(x) = no(x) ⇒ ρ(x) = 0

⇒ electric field
⇒ net electron drift
⇒ not thermal equilibrium!
Option 3: Demand Je = 0 in thermal equilibrium (and

Jh = 0 too) at every x ⇒
Diffusion precisely balances drift:
Je(x) = Jedrif t (x) + Jedif f (x) = 0
What is no(x) that satisfies this condition?
partially uncompensated
donor charge
no, Nd
Nd(x) +
no(x)
-
net electron charge
In general, then:
no(x) = Nd(x)
What are the implications of this?

• Space charge density:
ρ(x) = q[Nd(x) − no(x)]
partially uncompensated
donor charge
no, Nd
Nd(x) +
no(x)
-
net electron charge
x
ρ
+
− x
• Electric field:
Gauss’ equation:
dE ρ
dx s
Integrate from x = 0 to x:
1 �x
E(x) − E(0) = 0 ρ(x)dx
s
no, Nd
Nd(x) +
no(x)
-
x
ρ
+
− x
E
x
• Electrostatic potential:
dφ
= −E
dx
Integrate from x = 0 to x:
�
x
φ(x) − φ(0) = − 0 E(x)dx
Need to select reference (physics is in potential difference,

not in absolute value!); select φ(x = 0) = φref :
no, Nd
Nd(x) +
no(x)
-
x
ρ
+
− x
E
x
φref
x
Given Nd(x), want to know no(x), ρ(x), E(x), and φ(x).
Equations that describe problem:

dno
Je = qµnno E + qDn =0
dx
dE q
= (Nd − no)
dx s
Express them in terms of φ:
dφ dno
−qµnno + qDn =0 (1)
dx dx
d2 φ q
2
= (no − Nd) (2)
dx s
Plug [1] into [2]:
d2(ln no ) q2
2
= (no − Nd) (3)
dx skT
One equation with one unknown. Given Nd(x), can solve
for no(x) and all the rest, but...
... no analytical solution for most situations!
2. Quasi-neutral situation
d2(ln no ) q2
2
= (no − Nd)
dx skT
If Nd(x) changes slowly with x:

⇒ no (x) also changes slowly with x
d2 (ln no)
⇒ dx2
small
=⇒ no(x) Nd(x)
no (x) tracks Nd(x) well ⇒ minimum space charge ⇒

semiconductor is quasi-neutral
no, Nd
Nd(x)
no(x) = Nd(x)
Quasi-neutrality good if:
no − Nd no − Nd
| | 1 or | |1
no Nd
3. Relationships between φ(x) and equilibrium

carrier concentrations (Boltzmann relations)
From [1]:
µn dφ 1 dno
=
Dn dx no dx
Using Einstein relation:
q dφ d(ln no )
=
kT dx dx
Integrate:
q no
(φ − φref ) = ln no − ln no (ref ) = ln
kT no(ref )
Then:
no = no (ref )eq(φ−φref )/kT

Any reference is good.
In 6.012, φref = 0 at no(ref ) = ni.
Then:
no = nieqφ/kT
If do same with holes (starting with Jh = 0 in thermal

equilibrium, or simply using no po = n2i ):
po = nie−qφ/kT
Can rewrite as:
kT no
φ= ln
q ni
and
kT po
φ=− ln
q ni
2 ”60 mV” Rule:
At room temperature for Si:
no no
φ = (25 mV ) ln = (25 mV ) ln(10) log
ni ni
Or
no
φ (60 mV ) log 10
10
For
For every decade of increase in no , φ incr
increases
eases by
60 mV at 300K.
• Example 1:
no = 1018 cm−3 ⇒ φ = (60 mV ) × 8 = 480 mV
With holes:
po po
φ = −(25 mV ) ln = −(25 mV ) ln(10) log
ni ni
Or
po
φ −(60 mV ) log
1010
• Example 2:
no = 1018 cm−3 ⇒ po = 102 cm−3
⇒ φ = −(60 mV ) × (−8) = 480 mV

Relationship between φ and no and po :
φ (mV) φmax=550 mV
480
360
240
120
-120
-240
-360
no=po=ni
-480
φmin=-550 mV
100 102 104 106 108 1010 1012 101410161018 1020 no (cm-3)
10201018 10161014 10121010 108 106 104 102 100 po (cm-3)
Note: φ cannot exceed 550 mV or be smaller than −550 mV

(beyond these points, different physics come into play).
• Example 3: Compute potential difference in thermal
equilibrium between region where no = 1017 cm−3 and

region where po = 1015 cm−3 :
φ(no = 1017 cm−3 ) = 60 × 7 = 420 mV
φ(po = 1015 cm−3 ) = −60 × 5 = −300 mV
φ(no = 1017 cm−3 ) − φ(po = 1015 cm−3 ) = 720 mV
• Example 4: Compute potential difference in thermal
equilibrium between region where no = 1020 cm−3 and

region where po = 1016 cm−3 :
φ(no = 1020 cm−3) = φmax = 550 mV
φ(po = 1016 cm−3 ) = −60 × 6 = −360 mV
φ(no = 1020 cm−3 ) − φ(po = 1016 cm−3 ) = 910 mV

Boltzmann relations readily seen in device behavior!
2 pn diode current-voltage characteristics:
2 Bipolar transistor transfer characteristics:
Key conclusions
• It is possible to have an electric field inside a semicon-

ductor in thermal equilibrium
⇒ non-uniform doping distribution.
• In a slowly varying doping profile, majority carrier

concentration tracks well doping concentration.
• In thermal equilibrium, there are fundamental rela-
tionships between φ(x) and the equilibrium carrier
concentrations
⇒ Boltzmann relations (or ”60
”60 mV Rule
Rule””).
Electrostatics (II)
pn Junction in Thermal Equilibrium
September 22, 2005
Contents:
1. Introduction to pn junction
2. Electrostatics of pn junction in thermal equilibrium
3. The depletion approximation

4. Contact potentials
Reading assignment:

Key questions
• What happens if the doping distribution in a semi

-
conductor abruptly changes from n-type to p-type?
• Is there a simple description of the electrostatics of a

pn junction?
1. Introduction to pn junction
• pn junction: p-region and n-region in intimate contact
• Why is the p-n junction worth studying?
It is present in virtually every semiconductor device!
Example: CMOS cross section
PMOS NMOS
n+ p+ p+ n+ n+ p+
n
p
Understanding p-n junction is essential to understanding

transistor operation.
2. Electrostatics of p-n junction in equilibrium
Focus on intrinsic region:
��
��
n type
p type
��
x
p type
�� (a)
��
metal contact
to p side
(Na) p
x=0
��(Nd) n
(b)
metal contact to
n side
Doping distribution of abrupt p-n junction:
p-region
n-region
Na
Nd
0 x
What is the carrier concentration distribution in thermal

equilibrium?
First think of two sides separately:
p-region n-region
majority log po, no
carrier majority
po carrier
Na no
Nd
minority minority
carrier carrier
po
no ni2
ni2 Nd
Na
x
Now bring them together. What happens?
Diffusion of electrons and holes from majority carrier side

to minority carrier side until drift balances diffusion.
Resulting carrier profile in thermal equilibrium:
log po, no
Na
Nd
po no
ni2
ni2 Nd
Na
0 x
• Far away from metallurgical junction: nothing hap-

pens
quasi-neutral
– two quasi-neutr regions
al regions
• Around metallurgical junction: carrier drift must can-
cel diffusion
space-charge
– sp region
ace-charge region
In a linear scale: po, no
Na
Nd
po
- +
no
0 x
E
Thermal equilibrium: balance between drift and diffusion
Jpdiff
Jpdrift
Jndiff
Jndrift
Can divide semiconductor in three regions:

• two quasi-neutral n- and p-regions (QNR’s)
• one space charge region (SCR)
Now, want to know no (x), po (x), ρ(x), E(x), and φ(x).
Solve electrostatics using simple, powerful approximation.

3. The depletion approximation
• Assume QNR’s perfectly charge neutral
• assume SCR depleted of carriers (depletion region)

• transition between SCR and QNR’s sharp
(must calculate where to place −xpo and xno)
po, no depletion
approximation
Na
Nd
exact
po
- +
no
-xpo 0 xno x
n2i
• x < −xpo po (x) = Na, no (x) = Na
• − xpo < x < 0 po (x), no (x) Na
• 0 < x < xno no (x), po (x) Nd

n2i
• xno < x no (x) = Nd, po(x) = Nd
• Space charge density
ρ
depletion approximation
qNd exact
-xpo
0
0 xno x
-qNa
ρ(x) = 0 x < −xpo

= −qNa − xpo < x < 0
= qNd 0 < x < xno
= 0 xno < x
• Electric field
Integrate Gauss’ equation:
1 � x2
E(x2 ) − E(x1 ) = ρ(x)dx
s x1
ρ
qNd
-xpo
0
0 xno x
-qNa
E
-xpo xno
0
0 x
Eo
• x < −xpo E(x) = 0
E(x) − E(−xpo ) = 1s −x

�
• − xpo < x < 0 x
po
−qNadx
= −qN
s
a
x|x
−xpo
= −qNa
s
(x + xpo)
• 0 < x < xno E(x) = qNd

s
(x − xno)
• xno < x E(x) = 0

• Electrostatic potential
(with φ = 0 @ no = po = ni):
kT no kT po
φ= ln φ=− ln
q ni q ni
In QNR’s, no , po known ⇒ can determine φ:
in p-QNR: po = Na ⇒ φp = − kTq ln Nnia
in n-QNR: no = Nd ⇒ φn = kT
q
ln Nnid
φn
0
φB -xpo 0 xno x
φp
Built-in potential:
kT NaNd
φB = φn − φp = ln 2
q ni
General expression: did not use depletion approximation.
To get φ(x) in between, integrate E(x):
�
x2
φ(x2) − φ(x1 ) = − x1 E(x)dx
ρ
qNd
-xpo
0
0 xno x
-qNa
E
-xpo xno
0
0 x
Eo
φn
0
φB -xpo 0 xno x
φp
φn
0
φB -xpo 0 xno x
φp
• x < −xpo φ(x) = φp
• − xpo < x < 0 φ(x) − φ(−xpo )

�x
= − −x po
− qNa
s
(x + xpo )dx
2
= qNa
2s
(x + x po )
2
φ(x) = φp + qNa
2s
(x + xpo )
• 0 < x < xno φ(x) = φn − qNd (x − x )2

2s no
• xno < x φ(x) = φn
Almost done...
Still don’t know xno and xpo ⇒ need two more equations
1. Require overall charge neutrality:
qNaxpo = qNdxno
2. Require φ(x) continuous at x = 0:
qNa 2 qNd 2
φp + xpo = φn − xno
2s 2s
Two equations with two unknowns. Solution:
� �
� �
� �
2sφB Na
�
�
�
�
2sφB Nd
xno = �
� xpo = �
�
q(Na + Nd)Nd q(Na + Nd)Na
Now problem completely solved.

Other results:
Total width of space charge region:
�
�
�
�
� 2sφB (Na + Nd)
xdo = xno + xpo = �
�
qNaNd
Field at metallurgical junction:

�
�
�
2qφB NaNd
�
|Eo | = �
�
�
s(Na + Nd)
Three cases:
• Symmetric junction: Na = Nd ⇒ xpo = xno
• Asymmetric junction: Na > Nd ⇒ xpo < xno
• Strongly asymmetric junction:

i.e. p+n junction: Na Nd
�
�
�
2sφB �1
xpo xno xdo ∝ √
�
�
�
qNd Nd
�
�
2qφB Nd √
�
�
|Eo| �
�
�∝ Nd
s
The lowly-doped side controls the electrostatics of the pn

junction.
ρ ρ ρ
qNd
qNd qNd
x x x
-qNa
-qNa
-qNa
4. Contact potentials
Potential distribution in thermal equilibrium so far:
p - + n
p-QNR SCR n-QNR

φ
0
φB -xpo 0 xno x
Question 1: If I apply a voltmeter across diode, do I

measure φB ?
2 yes 2 no 2 it depends
Question 2: If I short diode terminals, does current

flow on outside circuit?
2 yes 2 no 2 sometimes
We are missing contact potential at metal-semiconductor

contacts:
p - + n
p-QNR SCR n-QNR

φ
φmn
φmp φB -xpo 0 xno x
Metal-semiconductor contacts: junctions of dissimilar ma-

terials
⇒ built-in potentials: φmn, φmp
Potential difference across structure must be zero
⇒ cannot measure φB !
φB = φmn + φmp
Key conclusions
• Electrostatics of pn junction in equilibrium:
– a space-charge region
– surrounded by two quasi-neutral regions
⇒ built-in potential across p-n junction
• To first order, carrier concentrations in space-charge

region are much smaller than doping level
⇒ depletion approximation.
• Contact potential at metal-semiconductor junctions:
⇒ from contact to contact, there is no potential build-

up across pn junction
Electrostatics (III)
Electrostatics of pn Junction under Bias
September 27, 2005
Contents:
1. electrostatics of pn junction under bias

2. depletion capacitance
Reading assignment:

Key questions
• What happens to the electrostatics of a pn junction if

a voltage is applied across its terminals?
• Why does a pn junction behave in some way like a
capacitor?
1. Electrostatics of pn junction under bias
Bias convention for pn junction:
p n
+-
V > 0 forward bias
V < 0 reverse bias
• Potential distribution across pn junction in thermal

equilibrium:
p - + n
p-QNR SCR n-QNR

φ
φmn
φmp φB -xpo 0 xno x
• Apply voltage to p-side with respect to n-side:

V
+-
p - + n
p-QNR SCR n-QNR

φ
φB -xpo 0 xno x
Battery imposes a potential difference across diode
How does potential distribution inside junction change as

a result of bias?
V
+-
p - + n
p-QNR SCR n-QNR

φ
V>0 V=0
V
?
x
Five regions where V can drop:
• metal/p-QNR contact?
• p-QNR?
• SCR?
• n-QNR?
• metal/n-QNR contact?
In which region does V drop most?
Or, how is V distributed across diode?

Essentially, all applied voltage drops across SCR:
+-
p - + n
p-QNR SCR n-QNR
φ
V>0
V
V=0 φB-V
φB x
Potential difference across junction (potential ”barrier”):
• in equilibrium: φB
• in forward bias: φB − V < φB
• in reverse bias: φB − V > φB (since V < 0)
What happens to SCR electrostatics?

SCR electrostatics under bias:
φB-V φB φB-V V>0

x V=0
V<0
E(V)
ρ
qNd
-xp(V)
xn(V) x
-qNa
forward bias: built-in potential ↓ ⇒ |E| ↓ ⇒ xd ↓
reverse bias: built-in potential ↑ ⇒ |E| ↑ ⇒ xd ↑
Fundamentally,
• electrostatics of SCR under bias unchanged from ther-

mal equilibrium
• SCR dipole of charge modulated to accommodate mod-
ified potential build up across junction
Useful consequence:
• Analytical formulation of electrostatics of SCR iden-

tical to that of thermal equilibrium if:
φB −→ φB − V
Then, within depletion approximation:

� �
� �
�
�
� 2s (φB − V )Na �
�
� 2s (φB − V )Nd
xn(V ) = �
� xp(V ) = �
�
q(Na + Nd)Nd q(Na + Nd)Na
�
�
�
�
� 2s(φB − V )(Na + Nd)
xd(V ) = �
�
qNaNd
�
�
�
� 2q(φB − V )NaNd
|E|(V ) = �
�
�
s(Na + Nd)
Can all be rewritten as:

�
�
�
� V
xn(V ) = x �
no �
� 1−
φB
�
�
�
� V
xp (V ) = x �
po �
�1−
φB
�
�
�
� V
xd(V ) = x �
do �
� 1−
φB
�
�
�
� V
|E|(V ) = |Eo| 1 − �
�
�
φB
In strongly asymmetric junction, all changes take place

in lowly doped side:
φ E ρ
qNd
φB-V φB φB-V
V>0 x x xn(V) x
V=0
V<0 -qNa
E(V)
2. Depletion capacitance
smal l signal on top of bias:

Apply small
V ∆V
+-
p n
- - - + +
- -- + + ++ +
- -- +
- ++ +
- - -- +
+ + +
- - - - + + +
qNd
-∆Qj
+Qj
-xp(V)
xn(V) x
∆Qj -Qj
V
-qNa V+∆V
∆ρ
+∆Qj
xn(V)
-xp(V) x
−∆Qj
Change in ∆V across diode:
⇒ change of ∆Qj at −xp

⇒ change of −∆Qj at xn
Looks like parallel-plate capacitor:
V ∆V
+-
εs
tins
+∆Q
+Q
-Q
-∆Q
∆ρ
+∆Q
x
-∆Q
Capacitance per unit area:
s
C=
tins
In analogy, in pn junction:
V ∆V
+-
p n
- - - + +
- -- + + ++ +
- -- +
- ++ +
- - -- +
+ + +
- - - - + + +
qNd
-∆Qj
+Qj
-xp(V)
xn(V) x
∆Qj -Qj
V
-qNa V+∆V
∆ρ
+∆Qj
xn(V)
-xp(V) x
−∆Qj
Depletion capacitance per unit area (depletion approx.):
�
�
�
s qs NaNd �
�
Cjo
Cj (V ) = = �
� = �
xd(V ) 2(φB − V )(Na + Nd) 1 − φVB
�
�
�
s qs NaNd �
�
Cjo
Cj (V ) = = �
� = �
xd(V ) 2(φB − V )(Na + Nd) 1 − φVB
Key dependencies of Cj :
• Cj depends on bias (because xd depends on bias)
Cj
Cjo
0 φB V
• Cj depends on doping: Na, Nd ↑ ⇒ Cj ↑
• In strongly asymmetric junction (i.e. p+-n junction):

�
�
�
qsNd�
Cj (V ) �
�
�
2(φB − V )
capacitance dominated by lowly-doped side.

Relevance of capacitance-voltage characteristics of diode:
1. pn diode= variable capacitor (varactor):

⇒ useful for voltage-controlled oscillators (VCO)
2. Cj : important consideration in dynamics of pn diode
3. powerful characterization technique:

i.e. 1/Cj2 vs. V yields φB and Nd in strongly asym-
metric p+-n junction:
1 2(φB − V )

Cj2 qsNd
1
Cj2
- 2
εsqN d
φB V
0
Experimental data [from Fortini et al., IEEE Trans.

Electron Dev. ED-29, 1604 (1982)]:
Appears in Fortini, A., A. Hairie, and M. Gomina. "Analysis and capacitive measurement
of the built-in-field parameter in highly doped emitters." IEEE Trans on Electron Devices 29,
no. 10 (1982): 1604 (© 1982 IEEE). Used with permission.
Alternative view of capacitance: depletion charge
V ∆V
+-
p n
- - - + +
- -- + + ++ +
- -- +
- ++ +
- - -- +
+ + +
- - - - + + +
qNd
-∆Qj
+Qj
-xp(V)
xn(V) x
∆Qj -Qj
V
-qNa V+∆V
∆ρ
+∆Qj
xn(V)
-xp(V) x
−∆Qj
Within depletion approximation:

� �
� �
2qsNaNd(φB − V )
�
�
�
�
� V
Qj (V ) = �
� =Q �
jo �
�1−
Na + Nd φB
� �
� �
2qsNaNd(φB − V )
�
�
�
�
� V
Qj (V ) = �
� =Q 1−
�
jo �
�
Na + Nd φB
Qj
φB
0 V
Cj
Qjo
Cj is slope of Qj vs. V characteristics:
dQj
Cj =
dV
but not:
Qj
Cj =
V
Application of voltage to pn junction also results in cur-

rent: pn diode.
I log |I|
0.43 q
kT
IS
0
0 V 0 V
IS
linear scale semilogarithmic scale
Will study after MOSFET and CMOS digital circuits.
Key conclusions
• Voltage applied to pn junction drops across SCR:
⇒ SCR electrostatics modified

– in forward bias: xd ↓, |E| ↓
– in reverse bias: xd ↑, |E| ↑
• Analytical formulation for SCR electrostatics in ther-

mal equilibrium valid under bias if:
φB −→ φB − V
• As V changes, SCR charge changes too:

⇒ depletion capacitance
• pn junction depletion capacitance depends on bias
Electrostatics (IV)
Electrostatics of
Metal-Oxide-Semiconductor Structure
September 29, 2005
Contents:
1. Introduction to MOS structure

2. Electrostatics of MOS at zero bias
3. Electrostatics of MOS under bias
Reading assignment:
Key questions
• What is the big deal about the metal-oxide-semiconductor

structure?
• What do the electrostatics of the MOS structure look
like at zero bias?
• How do the electrostatics of the MOS structure get
modified if a voltage is applied across its terminals?
1. Introduction
Metal-Oxide-Semiconductor structure:
metal
interconnect to gate
gate oxide
εox = 3.9 εo n+ polysilicon gate
p-type x
εs = 11.7 εo
metal interconnect to bulk
MOS at the heart of the electronics revolution:

• Digital and analog functions: Metal-Oxide-Semiconductor
Field-Effect Transistor (MOSFET) is key element of
Complementary Metal-Oxide-Semiconductor (CMOS)
circuit family
• Memory function: Dynamic Random Access Mem-
ory (DRAM) and Flash Erasable Programmable Mem-
ory (EPROM)
• Imaging: Charge-Couple Device (CCD) camera
• Displays: Active-Matrix Liquid-Crystal Displays
• ...
2. MOS electrostatics at zero bias
Idealized 1D structure:
"metal"
(n+ polySi)
semiconductor
oxide (p type)
contact contact
-tox 0 x
• Metal: does not tolerate volume charge ⇒ charge can

only exist at its surface
• Oxide: insulator ⇒ no volume charge (no free carriers,
no dopants)
• Semiconductor: can have volume charge (SCR)
Thermal equilibrium can’t be established through oxide;

need wire to allow transfer of charge between metal and
semiconductor.
MOS structure: sandwich of dissimilar materials ⇒ car-

rier transfer ⇒ space-charge region at zero bias ⇒ built-in
potential
For most metals on p-Si, equilibrium achieved by elec-

trons diffusing from metal to semiconductor and holes
from semiconductor to metal:
log po, no
Na
po
no
ni2
Na
-tox 0 xdo x
Remember: no po = n2i
Fewer holes near Si/SiO2 interface ⇒ ionized acceptors

exposed (volume space charge)
2 Space charge density
log po, no
Na
po
no
ni2
Na
-tox 0 xdo x
ρο
QG
0 0 xdo
-tox x
-qNa
• In semiconductor: space-charge region close to Si/SiO2

interface ⇒ can do depletion approximation
approximation
• In metal: sheet of charge at metal/SiO2 interface
• Overall charge neutrality
x ≤ −tox ρo (x) = QG δ(−tox )

−tox < x<0 ρo (x) = 0
0 < x < xdo ρo (x) = −qNa
xdo < x ρo(x) = 0
2 Electric field
Integrate Gauss’ equation:
1 � x2
Eo(x2 ) − Eo(x1 ) = x1 ρo (x)dx

At interface between oxide and semiconductor:
change in permittivity ⇒ change in electric field
oxEox = sEs
Eox s
= 3
Es ox
Eox
Es
0
0 x
Start integrating from deep inside semiconductor:
ρο
0 xdo
0
-tox x
-qNa
Eο
Eox
Es
0
-tox 0 xdo x
xdo < x Eo(x) = 0
qNa
0 < x < xdo Eo (x) = − (x − xdo)
s
s + qNaxdo
−tox < x < 0 Eo (x) = Eo(x = 0 ) =
ox ox
x < −tox Eo(x) = 0

2 Electrostatic potential
(with φ = 0 @ no = po = ni)
kT no kT po
φ= ln
φ=− ln
q ni q ni
In QNR’s, no and po known ⇒ can determine φ:
in n+ gate: no = Nd
+ ⇒ φg = φn+
in p-QNR: po = Na ⇒ φp = − kT
q
ln Nnia
φο
φn+
φB
0
-tox 0 xdo x
φp
Built-in potential:
kT Na
φB = φg − φp = φn+ + ln
q ni
To get φo(x), integrate Eo(x); start from deep inside semi-

conductor bulk:
�
x2
φo(x2 ) − φo(x1) = − x1 Eo(x)dx
Eο
Eox
Es
0
-tox 0 xdo x
φο
φn+
Vox,o
φB 0 xdo
0 x
-tox
VB,o
φp
xdo < x φo(x) = φp
qNa
0 < x < xd φo(x) = φp + (x − xdo)2
2s
qNax2do qNaxdo
−tox < x < 0 φo (x) = φp + + (−x)
2s ox
x < −tox φo(x) = φn+
2 Still don’t know xdo ⇒ need one more equation:
Potential difference across structure has to add up to φB :
qNax2do qNaxdotox
φB = VB,o + Vox,o = +
2s ox
Solve quadratic equation:

� �
� �
s �
� 22ox φB s �
� 4φB
xdo = �
tox [ 1 +
�
� − 1] = �
�
�[ 1 + 2 − 1]
ox sqNat2ox Cox γ
where Cox is capacitance per unit area of oxide [units:

F/cm2]:
ox
Cox =
tox
and γ is body factor coefficient [units: V −1/2 ]:
1
�
γ= 2sqNa
Cox
2 Numerical example:
Nd = 1020 cm−3 , Na = 1017 cm−3 , tox = 8 nm
φB = 550 mV + 420 mV = 970 mV
Cox = 4.3 × 10−7 F/cm2
γ = 0.43 V 1/2
xdo = 91 nm
There are also contact potentials

⇒ total contact-to-contact potential difference is zero!
"metal"
semiconductor
contact oxide (p type) contact
φο
φn+
φB
0 0
x
-tox xdo
φp
3. MOS electrostatics under bias
Apply voltage to gate with respect to semiconductor:
VGB
+-
"metal"
(n+ polySi)
semiconductor
oxide (p type)
contact contact
-tox 0 x
Electrostatics of MOS structure affected ⇒ potential dif-

0.
ference across entire structure now =
How is potential difference accommodated?
Potential can drop in:
• gate contact
• n+-polysilicon gate
• oxide
• semiconductor SCR
• semiconductor QNR
• semiconductor contact
Potential difference shows up across oxide and SCR in

semiconductor:
VGB φB+VGB
? φB
0 -tox 0 xdo
x
Oxide is insulator ⇒ no current anywhere in structure
In SCR, quasi-equilibrium situation prevails

⇒ new balance between drift and diffusion
• electrostatics qualitatively identical to zero bias (but

amount of charge redistribution is different)
• np = n
2i
Apply VGB > 0: potential difference across structure in-

creases ⇒ need larger charge dipole ⇒ SCR expands into
semiconductor substrate:
ρ
xd
0
-tox 0 x
-qNa
Eox
Es
0
-tox 0 xd x
φ
VGB=0
VGB>0
φB+VGB
φB
0
-tox xd x
0
log p, n
Na
n
ni2
Na
-tox 0 xd x
Simple way to remember:
with VGB > 0, gate attracts electrons and repels holes.
Qualitatively, physics unchanged by applying VGB > 0.
Use mathematical formulation of zero bias, but:
φB → φB + VGB
For example,
�
�
�
s 4(φB + VGB )
�
xd(VGB ) = [ 1+ �
�
� − 1]
Cox γ2
VGB ↑ → xd ↑
Key conclusions
• Charge redistribution in MOS structure at zero bias:
– SCR in semiconductor
– built-in potential across MOS structure.
• In most cases, can do depletion approximation in semi-
conductor SCR.
• Application of voltage modulates depletion region width
in semiconductor. No current flows.
Electrostatics (V)
Electrostatics of
Metal-Oxide-Semiconductor Structure
(cont.)
October 4, 2005
Contents:
1. Overview of MOS electrostatics under bias
2. Depletion regime
3. Flatband
4. Accumulation regime
5. Threshold
6. Inversion regime
Reading assignment:
Announcements:
Quiz 1: 10/13, 7:30-9:30 PM,
(lectures #1-9); open book; must have calculator.
Key questions
• Is there more than one regime of operation of the MOS

structure under bias?
• What does ”carrier inversion” mean and what is the
big deal about it?
• How does the carrier inversion charge depend on the
gate voltage?
1. Overview of MOS electrostatics under bias

VGB
+-
"metal"
(n+ polySi)
semiconductor
oxide (p type)
contact contact
-tox 0 x
Application of bias:
• built-in potential across MOS structure increases from
φB to φB + VGB
• oxide forbids current flow ⇒
– J = 0 everywhere in semiconductor
– need drift=-diffusion in SCR
• must maintain boundary condition at Si/SiO2 inter-
face: Eox/Es 3
How can this be accommodated simultaneously? ⇒

quasi-equilibrium situation with potential build up across
MOS equal to φB + VGB
Important consequence of quasi-equilibrium:
⇒ Boltzmann relations apply in semiconductor
[they were derived starting from Je = Jh = 0]
n(x) = ni eqφ(x)/kT
p(x) = ni e−qφ(x)/kT
and
np = n2
i
at every x
[not the case in p-n junction or BJT under bias]
2. Depletion regime
For VGB > 0 gate ”attracts” electrons, ”repels” holes

⇒ depletion region widens
For VGB < 0 gate ”repels” electrons, ”attracts” holes

⇒ depletion region shrinks
ρ
xd(VGB)
0 0
-tox x
-qNa
Eox
Es
0
-tox 0 x VGB<0
xd(VGB)
φ
VGB=0
VGB>0
φB+VGB
φB
0
-tox xd(VGB) x
0
log p, n
Na
n
ni2
Na
-tox 0 x
xd(VGB)
In depletion regime, all results obtained for zero bias ap-

ply if φB → φB + VGB .
For example:
• depletion region thickness:
�
�
�
s � 4(φB + VGB )
xd(VGB ) = �
[ 1+
�
�
2
− 1]
Cox γ
• potential drop across semiconductor SCR:
qNax2d (VGB )
VB (VGB ) =
2s
• potential drop across oxide:
qNaxd (VGB )tox

Vox (VGB ) =
ox
3. Flatband
At a certain negative VGB , depletion region is wiped out

⇒ Flatband
ρ
ρ=0
0 0
-tox x
Eox=0
Es=0
0
-tox 0 x
φ VGB=0
VGB=VFB
VGB=-φB 0
0 x
-tox
log p, n
p
Na
n ni2
Na
x
-tox 0
Flatband voltage:
Flatband
VF B = −φB
4. Accumulation regime
If VGB < VF B accumulation of holes at Si/SiO2 interface
0
-tox 0 x
0 0
-tox Es x
Eox
0
-tox 0 x
VGB-VFB
log p, n
p
Na
n ni2
Na
-tox 0 x
5. Threshold
Back to VGB > 0.
For sufficiently large VGB > 0, electrostatics change when

n(0) = Na ⇒ threshold.
Beyond threshold, cannot neglect contributions of elec-

trons towards electrostatics.
n(0)=Na
log p, n
Na
p
n
ni2
Na
-tox 0 xdmax x
Let’s compute the voltage (threshold voltage

voltage)) that leads
to n(0) = Na.
Key assumption: use electrostatics of depletion (neglect

electron concentration at threshold).
2 Computation of threshold voltage.
Three-step process:
• First, compute potential drop in semiconductor at thresh-

old. Start from:
n(0) = nieqφ(0)/kT
Solve for φ(0) at VGB = VT :
kT n(0) kT Na
φ(0)|VT = ln |V = ln = −φp
q ni T q ni
φ
VT+φB -φp
0 VB=-2φp
-tox 0 xdmax x
φp
Hence:
VB (VT ) = −2φp
• Second, compute potential drop in oxide at threshold.
Obtain xd (VT ) using relationship between VB and xd in

depletion:
qNax2d(VT )
VB (VT ) = = −2φp
2s
Solve for xd (VT ):

�
�
�
2s(−2φp ) �
�
xd(VT ) = xdmax = �
�
qNa
Then:
qNaxd(VT ) �
Vox(VT ) = Eox (VT )tox = tox = γ −2φp
ox
φ
Vox
VT+φB -φp
0 VB=-2φp
-tox 0 xdmax x
φp
• Finally, sum potential drops across structure.
Vox
VT+φB -φp
0 VB=-2φp
-tox 0 xdmax x
φp
�
VT + φB = VB (VT ) + Vox (VT ) = −2φp + γ −2φp
Solve for VT :
�
VT = VF B − 2φp + γ −2φp
Key dependencies:
• If Na ↑ → VT ↑. The higher the doping level, the

more voltage required to produce n(0) = Na.
• If Cox ↑ (tox ↓) → VT ↓. The thinner the oxide, the
less voltage dropped across it.
6. Inversion
What happens for VGB > VT ?
More electrons at Si/SiO2 interface than acceptors
⇒ inversion.
inversion layer
log p, n
Na
n
p
ni2
Na
-tox 0 xdmax x
Electron concentration at Si/SiO2 interface modulated by
VGB ⇒ VGB ↑→ n(0) ↑→ |Qn| ↑

field-effect control of mobile ch charge!
arge!
[essence of MOSFET]
Want to compute Qn vs. VGB [charge-control relation]
Make sheet charge approximation: electron layer at semi-

conductor surface is much thinner than any other dimen-
sion in problem (tox , xd ).
2 Charge-control relation
Let us look at overall electrostatics:
xdmax
0
-tox 0 x
-qNa
Qn
E
Eox
Es
0
-tox 0 xdmax x
VGB+φB
0
-tox 0 xdmax x
log p, n
n Na
p
ni2
Na
-tox 0 xdmax x
Key realization:
|Qn| ∝ n(0) ∝ eqφ(0)/kT
�
|QB | ∝ φ(0)
Hence, as VGB ↑ and φ(0) ↑, |Qn| will change a lot, but

|QB | will change very little.
Several consequences:
• little change in φ(0) beyond threshold
• VB does not increase much beyond VB (VT ) = −2φp

(a thin sheet of electrons does not contribute much
to VB ):
VB (inv.) VB (VT ) = −2φp

• little change in QB beyond threshold
• xd does not increase much beyond threshold:
�
�
�
�
� 2s(−2φp )
xd(inv.) xd (VT ) = �
� = xdmax
qNa
• All extra voltage beyond VT used to increase inversion

charge Qn. Think of it as capacitor:
– top plate: metal gate
– bottom plate: inversion layer
Q = CV
⇒ Qn = −Cox (VGB − VT ) for VGB > VT
over Qn by VGB ⇒ key ttoo

Existence of Qn and control ov
MOS electronics
|Qn|
Cox
VT VGB
Key conclusions
M O S (p-type)
--- ++
- ++
VGB<VFB --- ++
++
accumulation
--
+
VGB=VFB flatband
+ -
++
-
VFB<VGB<0 - depletion
+ -
+ -
+ - --
+
VGB=0 +++ - -
- - zero bias
++ - - -
+++ - - -
- - -
++ depletion
0<VGB<VT ++ - - - --
++ - - -
++++ -
---- -- -- - -
- -
+++
VGB=VT + + --- - - - - threshold
+++
-
--- - - - -
+
++++ ----- - -- - - -
++ ---- - - inversion
VGB>VT +++ ---- - - -
+++
+ ----- - -
In inversion:
|Qn| = Cox (VGB − VT ) for VGB > VT

Lecture 9 - MOSFET (I)
MOSFET I-V Characteristics
October 6, 2005
Contents:
1. MOSFET: cross-section, layout, symbols
2. Qualitative operation
3. I-V characteristics
Reading assignment:
Announcements: Quiz 1: 10/13, 7:30-9:30 PM,

(lectures #1-9); open book; must have calculator.
Key questions
• How can carrier inversion be exploited to make a tran-

sistor?
• How does a MOSFET work?
• How does one construct a simple first-order model for
the current-voltage characteristics of a MOSFET?
1. MOSFET: layout, cross-section, symbols
polysilicon gate
body source drain
gate
n+
p+ n+ n+
inversion layer gate oxide

n
channel
gate length
gate width
p+ p n+ n+ n+
n+ STI edge
Key elements:
• inversion layer under gate (depending on gate voltage)
• heavily-doped regions reach underneath gate ⇒ in

-
version layer electrically connects source and drain
• 4-terminal device: body voltage important
Image removed due to copyright restrictions.

2 Circuit symbols
Two complementary devices:
• n-channel device (n-MOSFET) on p-Si substrate
(uses electron inversion layer)
• p-channel device (p-MOSFET) on n-Si substrate
(uses hole inversion layer)
D IDn D
IDn S
+ + S
+
VDS > 0 VSG
VSB
G G _ _
B B
+ + G B G B
VGS VBS VSD > 0
_ _
S−
S −IDp D− −IDp D
(a) n-channel MOSFET (b) p-channel MOSFET

2. Qualitative operation
Water analogy of MOSFET:

• Source: water reservoir
• Drain: water reservoir
• Gate: gate between source and drain reservoirs
VDS
VGS
ID
S n+ D
VGS
n+ n+ water
VDS
inversion
depletion
layer
region
B
source gate drain
Want to understand MOSFET operation as a function of:
• gate-to-source voltage (gate height over source water

level)
• drain-to-source voltage (water level difference between
reservoirs)
Initially consider source tied up to body (substrate or

back).
Three regimes of operation:
2 Cut-off regime:
regime:
• MOSFET: VGS < VT , VGD < VT with VDS > 0.
• Water analogy: gate closed; no water can flow regardless

of relative height of source and drain reservoirs.
VGS<VT VGD<VT
G
S n+ D
n+ n+
no inversion
layer
anywhere depletion
region
p
no water flow
ID = 0
2 Linear or Triode regime:
• MOSFET: VGS > VT , VGD > VT , with VDS > 0.
• Water analogy: gate open but small difference in height

between source and drain; water flows.
VGS>VT VGD>VT
G
S n+ D
n+ n+
inversion layer
everywhere
depletion
region
p
Electrons drift from source to drain ⇒ electrical current!
• VGS ↑ → |Qn| ↑ → ID ↑
• VDS ↑ → |Ey | ↑ → ID ↑
ID ID
small VDS small VDS
VGS>VT
VDS
0 0
0 VDS VT VGS
2 Satura
Saturation regime:
• MOSFET: VGS > VT , VGD < VT (VDS > 0).
• Water analogy: gate open; water flows from source to

drain, but free-drop on drain side ⇒ total flow indepen-
dent of relative reservoir height!
VGS>VT VGD<VT
G
S n+ D
n+ n+
inversion layer
depletion "pinched-off"
region at drain side
p
ID independent of VDS : ID = IDsat
VGDsat=VT
ID
saturation
linear
0
0 VDSsat=VGS-VT VDS
Geometry of problem:
y
0 L
VDS
VGS
ID
G
IS
-tox
S n+ D
0
n+ n+
xj inversion
depletion
VBS=0 layer
region
2 General expression of channel current
Current can only flow in y-direction:
Iy = W Qn(y)vy (y)
Drain terminal current is equal to minus channel current:
ID = −W Qn(y)vy (y)
ID = −W Qn(y)vy (y)
Rewrite in terms of voltage at channel location y, Vc(y):
• If electric field is not too big:
dVc (y)
vy (y) −µnEy (y) = µn
dy
• For Qn(y ) use charge-control relation at location y:
Qn(y) = −Cox [VGS − Vc(y) − VT ]
for VGS − Vc(y) ≥ VT .
All together:
dVc(y)
ID = W µnCox (VGS − Vc (y) − VT )
dy
Simple linear first-order differential equation with one un-

known, the channel voltage Vc(y).
Solve by separating variables:
ID dy = W µnCox (VGS − Vc − VT )dVc
Integrate along the channel in the linear regime:
-for y = 0, Vc(0) = 0
-for y = L, Vc(L) = VDS (linear regime)
Then:
� �
L VDS
ID 0 dy = W µnCox 0 (VGS − Vc − VT )dVc
or:
W VDS
ID = µnCox (VGS − − VT )VDS
L 2
For small VDS :
W
ID µnCox (VGS − VT )VDS
L
Key dependencies:
• VDS ↑ → ID ↑ (higher lateral electric field)

• VGS ↑→ ID ↑ (higher electron concentration)
• L ↑ → ID ↓ (lower lateral electric field)
• W ↑ → ID ↑ (wider conduction channel)
ID ID
small VDS small VDS
VGS>VT
VDS
0 0
0 VDS VT VGS
This is the linear or triode regime.

In general,
W VDS
L 2
Equation valid if VGS − Vc(y) ≥ VT at every y.
Worst point is y = L, where Vc (y) = VDS , hence, equa-

tion valid if VGS − VDS ≥ VT , or:
VDS ≤ VGS − VT
ID VDS=VGS-VT
VGS
VGS=VT
0
0 VDS
term responsible for bend over of ID : − VDS

2
To understand why ID bends over, must understand first

channel debiasing
debiasing::
|Qn(y)|
VDS=0
Cox(VGS-VT)
VDS>0
0
0 L y
|Ey(y)|
VDS>0
VDS=0
0
0 L y
Vc(y)
VDS
VDS>0
VDS=0
0
0 L y
VGS-Vc(y)
VDS=0
VGS
VDS
local gate
overdrive VDS>0
VT
0 L y
Along channel from source to drain:
y ↑ → Vc(y) ↑ → |Qn(y)| ↓ → |Ey (y)| ↑
Local ”channel overdrive” reduced closer to drain.

Impact of VDS :
|Qn(y)|
VDS=0
Cox(VGS-VT)
VDS
0
0 L y
|Ey(y)|
VDS
VDS=0
0
0 L y
Vc(y)
VDS
VDS
VDS=0
0
0 L y
VGS-Vc(y)
VDS VDS=0
VGS
VDS
local gate
overdrive
VT
0 L y
As VDS ↑, channel debiasing more prominent

⇒ ID rises more slowly with VDS
3µm n-channel MOSFET
Output characteristicss ((VGS = 0 − 4 V, ∆VGS = 0.5 V ):

Zoom close to origin (VGS = 0 − 2 V, ∆VGS = 0.25 V ):

Transfer characteristics (VDS = 0 − 100 mV, ∆VDS =

20 mV ):
Key conclusions
• The MOSFET is a field-effect transistor:
– the amount of charge in the inversion layer is con-

trolled by the field-effect action of the gate
– the charge in the inversion layer is mobile ⇒ con-
duction possible between source and drain
• In the linear regime:
– VGS ↑⇒ ID ↑: more electrons in the channel
– VDS ↑⇒ ID ↑: stronger field pulling electrons out
of the source
• Channel debiasing: inversion layer ”thins down” from
source to drain ⇒ current saturation as VDS approaches:
VDSsat = VGS − VT
Lecture 10 - MOSFET (II)
MOSFET I-V Characteristics (cont.)
October 13, 2005
Contents:
1. The saturation regime

2. Backgate characteristics
Reading assignment:
Howe and Sodini, Ch. 4, §4.4
Announcements:
Quiz 1: 10/13, 7:30-9:30 PM, (lectures #1-9); open book; must
have calculator.
have
Key questions
• How does the MOSFET work in saturation?
• Does the pinch-off point represent a block to current

flow?
• How come the MOSFET current still increases a bit
with VDS in saturation?
• How does the application of a back bias affect the
MOSFET I-V characteristics?
1. The saturation regime
Geometry of problem:
y
0 L
VDS
VGS
ID
G
IS
-tox
S n+ D
0
n+ n+
xj inversion
depletion
VBS=0 layer
region
Regimes of operation so far (VBS = 0):
• Cut-off: VGS < VT , VGD < VT :

no inversion layer anywhere underneath gate
ID = 0
• Linear: VGS > VT , VGD > VT (with VDS > 0):
inversion layer everywhere underneath gate
W VDS
L 2
Output characteristics:
ID VDS=VGS-VT
VGS
VGS=VT
0
0 VDS
2 Review of Qn, Ey , Vc , and VGS − Vc(y) in linear regime

as VDS increases:
|Qn(y)|
VDS=0
Cox(VGS-VT)
VDS
0
0 L y
|Ey(y)|
VDS
VDS=0
0
0 L y
Vc(y)
VDS
VDS
VDS=0
0
0 L y
VGS-Vc(y)
VDS VDS=0
VGS
VDS
local gate
overdrive
VT
0 L y
Ohmic drop along channel debiases inversion layer
⇒ ID rises more slowly with VDS

2 Drain current saturation
As VDS approaches:
VDSsat = VGS − VT
increase in |Ey | compensated by decrease in |Qn|

⇒ ID saturates to:
IDsat = IDlin(VDS = VDSsat = VGS − VT )
Then:
W
IDsat = µnCox(VGS − VT )2
2L
VDSsat=VGS-VT
ID
linear saturation
VGS
VGS=VT
0
0 VDS
cutoff
W
2L
Transfer characteristics in saturation:
ID
VDS>VDSsat=VGS-VT
0 VT
VGS
2 What happens when VDS = VGS − VT ?
Charge control relation at drain-end of channel:
Qn(L) = −Cox(VGS − VDS − VT ) = 0
No inversion layer at end of channel??!! ⇒ Pinch-off
At pinch-off:
• charge control equation inaccurate around VT

• electron concentration small but not zero
• electrons move fast because electric field is very high
• dominant electrostatic feature: acceptor charge

• there is no barrier to electron flow (on the contrary!)
G
D
- +
- - - - - - - - - ++ + ++
+++ + + n+ drain
-- - - -
-
inversion layer
p
depletion regions
L y
2 Key dependencies of IDsat
• IDsat ∝ (VGS − VT )2
Voltage at pinch-off point (Vc = 0 at source):
��
G
D
+
- - - -- -
-
-
- -+ n+
++++ +++++
-- - - -
-
p
Vc(L)=VDSsat=VGS-VT
Drain current at pinch-off:
∝ lateral electric field ∝ VDSsat = VGS − VT
∝ electron concentration ∝ VGS − VT
⇒ IDsat ∝ (VGS − VT )2
1
• IDsat ∝ L
L ↓ → |Ey | ↑
3µm n-channel MOSFET
Output characteristics (VGS = 0 − 4 V, ∆VGS = 0.5 V ):

Transfer characteristics in saturation (VDS = 3 V ):

2 What happens if VDS > VGS − VT ?
Depletion region separating pinch-off point and drain widens

(just like in reverse-biased pn junction)
G
D
- -+
- - - -
- + n+
- - - ++++ +++++
-- - - -
-
Vc(L-∆L)=VDSsat=VGS-VT
p
L-∆L L y
To first order, ID does not increase past pinchoff:
W
ID = IDsat = µnCox (VGS − VT )2
2L
To second order, electrical channel length affected

modulation”): VDS ↑⇒ Lchannel ↓⇒
”channel-length modulation”
(”channel-length
ID ↑
1 1 ∆L
ID ∝ (1 + )
L − ∆L L L
Experimental finding:
∆L ∝ VDS − VDSsat
Hence:
∆L
= λ(VDS − VDSsat)
L
Improved model in saturation:
W
IDsat = µnCox (VGS − VT )2 [1 + λ(VDS − VDSsat)]
2L
VDSsat
ID
VGS
VGS=Vth
0
0 VDS
Also, experimental finding:
1
λ∝
L
2. Backgate characteristics
There is a fourth terminal in a MOSFET: the body.
What does the body do?
VDS
VGS>VT ID
G
S D
n+ n+
inversion layer
VBS depletion region
p
0 y
L
Body contact allows application of bias to body with re

-
spect to inversion layer, VBS .
Only interested in VBS < 0 (pn diode in reverse bias).
Interested in effect on inversion layer
⇒ examine for VGS > VT (keep VGS constant).

Application of VBS < 0 increases potential build-up across

semiconductor:
−2φp ⇒ −2φp − VBS
Depletion region must widen to produce required extra

field:
ρ
0 xdmax(VBS)
0
-tox x
-qNa
Qn
E
Eox
VBS=0
Es VBS<0
0 x
-tox 0 xdmax(VBS)
φ
Vox
VGS+φB -φp
0
-tox 0 x VB=-2φp
VB=-2φp-VBS
VBS
Consequences of application of VBS < 0:
• −2φp ⇒ −2φp − VBS
• |QB | ↑⇒ xdmax ↑
• since VGS constant, Vox unchanged

⇒ Eox unchanged
⇒ |Qs| = |QG| unchanged
• |Qs| = |Qn| + |QB | unchanged, but |QB | ↑ ⇒ |Qn| ↓

⇒ inversion la
layer
yer charge is reduced!
Application of VBS < 0 with constant VGS reduces elec-

tron concentration in inversion layer ⇒ VT ↑
How does VT change with VBS ?
In VT formula change −2φp to −2φp − VBS :
VTGB (VBS ) = VF B − 2φp − VBS + γ (−2φp − VBS )
In MOSFETs, interested in VT between gate and source:
VGB = VGS − VBS ⇒ VTGB = VTGS − VBS
Then:
VTGS = VTGB + VBS
And:
�
VTGS (VBS ) = VF B − 2φp + γ (−2φp − VBS ) ≡ VT (VBS )
In the context of the MOSFET, VT is always defined in

terms of gate-to-source voltage.
Define:
VT o = VT (VBS = 0)
Then:
� �
VT (VBS ) = VT o + γ( −2φp − VBS − −2φp )
ID
VBS
saturation
0 cut-off
0 VT VGS
Backate characteristics (VBS = 0, −1, −2, −3 V, VDS =

3 V ):
Key conclusions
• MOSFET in saturation (VDS ≥ VDSsat): pinch-off

point at drain-end of channel
– electron concentration small, but
– electrons move very fast;

– pinch-off point does not represent a barrier to elec-
tron flow
• In saturation, ID saturates:
W
2L
• But..., due to channel-length modulation, IDsat in-

creases slightly with VDS
• Application of back bias shifts VT (back-gate effect)
Lecture 11 - MOSFET (III)
MOSFET Equivalent Circuit Models
October 18, 2005
Contents:
1. Low-frequency small-signal equivalent circuit model
2. High-frequency small-signal equivalent circuit model
Reading assignment:
Howe and Sodini, Ch. 4, §4.5-4.6

Key questions
• What is the topology of a small-signal equivalent cir-

cuit model of the MOSFET?
• What are the key dependencies of the leading model
elements in saturation?
1. Low-frequency small-signal equivalent cir-

cuit model
Regimes of operation of MOSFET:
VDSsat=VGS-VT
ID
linear saturation
ID
VDS VGS
VGS VBS
VGS=VT
0
0 VDS
cutoff
• Cut-off:
ID = 0
• Linear:
W VDS
L 2
• Saturation:
W
ID = IDsat = µnCox (VGS −VT )2 [1+λ(VDS −VDSsat)]
2L
Effect of back bias:
� �
Small-signal device modeling
In many applications, interested in response of device to

a small-signal applied on top of bias:
ID+id
+
v
- ds
+ VDS
vgs + v
- - bs
VGS VBS
Key points:
• Small-signal is small
⇒ response of non-linear components becomes linear
• Can separate response of MOSFET to bias and small
signal.
• Since response is linear, superposition can be used
⇒ effects of different small signals are independent

from each other
MOSFET
small-signal
equivalent
circuit model
ID+id ID id
+ +
v v
- ds - ds
+ VDS = VDS +
vgs + +
v vgs + v
- - bs - - bs
VGS VBS VGS VBS
Mathematically:
iD (VGS + vgs, VDS + vds, VBS + vbs)

∂ID ∂ID ∂ID
ID (VGS , VDS , VBS )+ | vgs + | vds + | vbs
∂VGS Q ∂VDS Q ∂VBS Q
where Q ≡ bias point (VGS , VDS , VBS )
Small-signal id:
id gm vgs + govds + gmb vbs
Define:
gm ≡ transconductance [S]
go ≡ output or drain conductance [S]
gmb ≡ backgate transconductance [S]
Then:
∂ID ∂ID ∂ID
gm |Q go |Q gmb |Q
∂VGS ∂VDS ∂VBS
2 Transconductance
In saturation regime:
W
ID = µnCox (VGS − VT )2 [1 + λ(VDS − VDSsat)]
2L
Then (neglecting channel length modulation):
∂ID W
gm = | µnCox (VGS − VT )
∂VGS Q L
Rewrite in terms of ID :
�
�
�
�
�
W
gm = 2 � µnCox ID
L
gm gm
saturation
saturation
cut-off
0 0
0 VT VGS 0 ID
Transconductance of 3 µm nMOSFET (VDS = 2 V ):
Equivalent circuit model representation of gm :

id
G D
+
vgs gmvgs
-
S
B
2 Output conductance
In saturation regime:
W
ID = µnCox (VGS − VT )2 [1 + λ(VDS − VDSsat)]
2L
Then:
∂ID W ID
go = |Q = µnCox (VGS − VT )2 λ λID ∝
∂VDS 2L L
Output resistance is inverse of output conductance:
1 L
ro = ∝
go ID
go go
saturation
saturation
cut-off
0 0
0 VT VGS 0 ID
Output conductance of 3 µm nMOSFET:
Equivalent circuit model representation of go:

id
G D
+
vgs ro
-
S
B
2 Backgate transconductance
In saturation regime (neglect channel-length modulation):
W
ID µnCox (VGS − VT )2
2L
Then:
∂ID W ∂VT
gmb = | = µnCox (VGS − VT )(− | )
∂VBS Q L ∂VBS Q
Since:
� �
Then:
∂VT −γ
| = �
∂VBS Q 2 −2φp − VBS
All together:
γgm
gmb = �
2 −2φp − VBS
gmb inherits all dependencies of gm

Body of MOSFET is a true gate: output characteristics

for different values of VBS (VBS = 0 − (−3) V, ∆VBS =
−0.5 V , VGS = 2 V ):
Equivalent circuit model representation of gmb :
id
G D
+
vgs gmbvbs
-
S
-
vbs
+
B
Complete MOSFET small-signal equivalent circuit model

for low frequency:
id
G D
+
vgs gmvgs gmbvbs ro

-
S
-
vbs
+
B
2. High-frequency small-signal equivalent cir-

cuit model
Need to add capacitances. In saturation:
Cfringe gate
Cfringe
source n+ drain
Cgs,i
n+ Cov Cov n+
Cjsw Csb,i Cjsw
Cj Cj
p
body
Cgs ≡ intrinsic gate capacitance

+ overlap capacitance, Cov (+fringe)
Cgd ≡ overlap capacitance, Cov

(+fringe)
Cgb ≡ (only parasitic capacitance)
Csb ≡ source junction depletion capacitance

+sidewall (+channel-substrate capacitance)
Cdb ≡ drain junction depletion capacitance

+sidewall
Complete MOSFET high-frequency small-signal equiva-

lent circuit model:
Cgd
id
G
D
+
vgs Cgs gmvgs gmbvbs ro

-
S
-
vbs Csb
+
B
Cdb
Plan for development of capacitance model:
• Start with Cgs,i

– compute gate charge QG = −(QN + QB )
– compute how QG changes with VGS
• Add pn junction capacitances
Inversion layer charge in saturation
�
L �
VGS −VT dy
QN (VGS ) = W 0 Qn (y)dy =W 0 Qn(Vc ) dVc
dVc
But:
dVc ID
=−
dy W µnQn(Vc )
Then:
W 2Lµn � VGS −VT 2

QN (VGS ) = − 0 Qn(Vc )dVc
ID
Remember:
Qn(Vc ) = −Cox (VGS − Vc − VT )
Then:
W 2Lµn Cox
2 �
VGS −VT 2
QN (VGS ) = − 0 (V GS − V c − V T ) dVc
ID
Do integral, substitute ID in saturation and get:
2
QN (VGS ) = − W LCox (VGS − VT )
3
Gate charge:
QG(VGS ) = −QN (VGS ) − QB,max
Intrinsic gate-to-source capacitance:
dQG 2
Cgs,i = = W LCox
dVGS 3
Must add overlap capacitance:
2
Cgs = W LCox + W Cov
3
Gate-to-drain capacitance - only overlap capacitance:
Cgd = W Cov
polysilicon gate
body source drain
gate
n+
p+ n+ n+

n
channel
gate length
gate width
p+ p n+ n+ n+
n+ STI edge
Body-to-source capacitance = source junction capacitance:
�
�
�
�
�
qsNa
Csb = Cj +Cjsw = W L dif f �
� +(2Ldif f +W )CJ SW
2(φB − VBS )
Body-to-drain capacitance = drain junction capacitance:

�
�
�
�
�
qs Na
Cdb = Cj +Cjsw = W L dif f �
� +(2Ldif f +W )CJ SW
2(φB − VBD )
Key conclusions
High-frequency small-signal equivalent circuit model of

MOSFET:
Cgd id
G D
+

-
S
-
vbs Csb
+
B
Cdb
In saturation:
�
�
�
W �
gm ∝ ID �
�
L
ID
go ∝
L
Cgs ∝ W LCox
Lecture 12 - Digital Circuits (I)
The inverter
October 20, 2005
Contents:
1. Introduction to digital electronics: the inverter
2. NMOS inverter with resistor pull up
Reading assignment:
Howe and Sodini, Ch. 5, §§5.1-5.3.2

Key questions
• What are the key figures of merit of logic circuits?
• How can one make a simple inverter using a single

MOSFET?
1. Introduction to digital electronics: the in-

verter
In digital electronics, digitally-encoded information is rep-

resented by means of two distinct voltage ranges:
VMAX
logic 1
VOH
undefined
region
VOL
logic 0
VMIN
• logic 0: VM IN ≤ V ≤ VOL
• logic 1: VOH ≤ V ≤ VM AX
• undefined logic value: VOL ≤ V ≤ VOH .
Logic operations are performed using logic gates.
Simplest logic operation of all: inversion ⇒ inverter

inverter
2 Ideal inverter:
IN OUT
OUT=IN 0 1
IN
1 0
Circuit representation and ideal transfer function:
VOUT
v+
V+ VOUT=VIN
V+
+ + 2
VIN VOUT
-
-
0
0 VM= V
+ V+ VIN
2
Define switching point or logic threshold:

threshold:
VM ≡ input voltage for which VOU T = VIN
-for 0 ≤ VIN ≤ VM ⇒ VOU T = V +
-for VM ≤ VIN ≤ V + ⇒ VOU T = 0

Key property of ideal inverter: signal re

regeneration
generation
VOUT
v+
V+ VOUT=VIN
V+
+ + 2
VIN VOUT
- -
0
0 VM = V
+ V+ VIN
2
Ideal inverter returns well defined logical outputs (0 or

V +) even in the presence of considerable noise in VIN
(from voltage spikes, crosstalk, etc.)
VIN VOUT
V+ V+
logic level
level restoration VM VM
0 0
VIN VOUT
V+ V+
noise suppression VM VM
0 0
VIN VOUT
V+ V+
pulse edge sharpening VM VM
0 0
2 ”Real” inverter:
VOUT
V+ slope=-1
VMAX v+
logic 1 VOH
|Av|>1
undefined + +
region VIN VOUT
- -
VOL
logic 0 VMIN
0
0 VIN
V+
In a real inverter, valid logic levels defined as follows:
• logic 0:
VM IN ≡ output voltage when VIN = V +
VOL ≡ smallest output voltage where slope=-1
• logic 1:
VOH ≡ largest output voltage where slope=-1
VM AX ≡ output voltage when VIN = 0

Two other important voltages:
|Av|<1
VOUT noise suppressed
VMAX
logic 1 slope=-1
VOH
|Av|>1
undefined edges sharpened
region
|Av|<1
VOL noise suppressed
logic 0 VMIN
0
0 VIL VIH V+ VIN
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VIL ≡ smallest input voltage where slope=-1
VIH ≡ highest input voltage where slope=-1
To have signal regeneration:
range of input values that produce acceptable logic output

> range of valid logic values
Key to signal regeneration in inverter: high voltage gain

Quantify signal regeneration through noise mar

margins.
gins.
Consider chain of two inverters:

noise
M N
VOUT VIN
VMAX VMAX
VOH
NMH
VIH
VIL
VOL NML
VMIN VMIN
inverter M inverter N
output input
Define noise margins:
N MH = VOH − VIH noise margin high

N ML = VIL − VOL noise margin low
When signal is within noise margins:
• logic 1 output from first inverter interpreted as logic

1 input by second inverter
• logic 0 output from first inverter interpreted as logic
0 input by second inverter
Simplifications for hand calculations
Hard to compute Av = −1 points in transfer function.
Approximate calculation:
VOUT
VOH=VMAX
slope= Av(VM)
VOUT=VIN
VM
VOL=VMIN
0
0 VIL VM VIH V+ VIN
• Assume VOL VM IN and VOH VM AX

• Trace tangent of transfer function at VM
(slope=small signal voltage gain at VM )
• VIL intersection of tangent with VOU T = VM AX

• VIH intersection of tangent with VOU T = VM IN
• to enhance noise margin: |Av (VM )| ↑
VOUT
VOH=VMAX
slope= Av(VM)
VOUT=VIN
VM
VOL=VMIN
0
0 VIL VM VIH V+ VIN
VMAX − VM VMAX − VM
|Av (VM )| ⇒ VIL VM −
VM − VIL |Av (VM )|
VM − VMIN 1 VMIN
|Av (VM )| ⇒ VIH VM (1 + )−
VIH − VM |Av (VM )| |Av (VM )|
Then:
1
NML = VIL −VOL (VMAX −VMIN )−(VMAX −VM )(1+ )
|Av (VM )|
1
NMH = VOH −VIH (VMAX −VMIN )−(VM −VMIN )(1+ )
|Av (VM )|
If |Av (VM )| → ∞:
N ML → VM − VM IN N MH → VM AX − VM
2 Transient characteristics
Look at inverter switching in the time domain:
VIN
VOH
90%
50%
10% VOL
0 t
tR tF
IN OUT
VOUT tPHL tPLH

VOH
90%
50%
10% VOL
0 tF tR t
tCYCLE
tR ≡ rise time between 10% and 90% of total swing
tF ≡ fall time between 90% and 10% of total swing
tP HL ≡ propagation delay from high-to-low between

50% points
tP LH ≡ propagation delay from low-to-high between

50% points
Propagation delay:
tP = 12 (tP HL + tP LH )
Propagation delay: simplification for hand calculations
• Input wavefunction = ideal square wave

• Propagation delay times = delay times to 50% point
VIN
VOH
tCYCLE
VOL
t
VOUT tPHL tPLH
VOH VOH
50% tCYCLE
VOL
t
• Hand calculations only approximate

• SPICE essential for accurate delay analysis
2. NMOS inverter with resistor pull up
V+=VDD
R IR
VOUT
ID
VIN CL
load capacitance
(from following
stages)
Features:
• VBS = 0 (typically not shown)

• CL summarizes capacitive loading of following stages
(other logic gates, interconnect lines)
Basic operation:
• if VIN < VT , MOSFET OFF ⇒ VOU T = VDD

• if VIN > VT , MOSFET ON ⇒ VOU T small (value set
by resistor/nMOS divider)
VDD
+
R IR VR
-
VOUT
ID
VIN
Transfer function obtained by solving:
IR = ID
Can solve graphically: I-V characteristics of pull-up re-

sistor on ID vs. VOU T transistor characteristics:
IR=ID IR=ID IR=ID
VDD VDD
R R
1/R 1/R 1/R
0 0
0 VR=VDD-VOUT -VDD VR-VDD=-VOUT 0 VDD VOUT
Overlap I-V characteristics of resistor pull-up on I-V char-

acteristics of transistor:
IR=ID load line
VDD VGS=VDD
R
VGS=VIN
VGS=VT
0
0 VDD VDS=VOUT
Transfer function:
VOUT=VDS
VDD
0
0 VT VDD VIN=VGS
Logic levels:
VOUT=VDS
VMAX=VDD
VOUT=VIN
VM
VMIN
0 VT VM VDD VIN=VGS
For VM AX , transistor is cut-off, ID = 0:
VM AX = VDD
For VM IN , transistor is in linear regime; solve:
W VM IN VDD − VM IN
ID = µnCox (VDD − −VT )VM IN = IR =
L 2 R
For VM , transistor is in saturation; solve:
W VDD − VM
ID = µnCox (VM − VT )2 = IR =
2L R
Will continue next lecture with analysis of noise margin

and dynamics...
Key conclusions
• Logic circuits must exhibit noise margins in which

they are inmune to noise in input signal.
• Logic circuits must be regenerative: able to restore
clean logic values even if input is noisy.
• Propagation delay: time for logic gate to perform its
function.
• Concept of load line: graphical technique to visualize
transfer characteristics of inverter.
• First-order solution (by hand) of inverter figures of
merit easy if regimes of operation of transistor are
correctly identified.
• For more accurate solutions, use SPICE (or other cir-
cuit CAD tool).
Lecture 13 - Digital Circuits (II)
MOS Inverter Circuits
October 25, 2005
Contents:
1. NMOS inverter with resistor pull-up (cont.)
2. NMOS inverter with current-source pull-up
3. Complementary MOS (CMOS) Inverter
Reading assignment:

Key questions
• What are the key design trade-offs of the NMOS in-

verter with resistor pull-up?
• How can one improve upon these trade-offs?
• What is special about a CMOS inverter?

1. NMOS inverter with resistor pull-up (cont.)
V+=VDD VOUT=VDS
VOH=VMAX=VDD
R IR
slope= Av(VM)
VOUT=VIN
VOUT
VM
ID
VIN
CL
VOL=VMIN
0
0 VT VM VDD VIN=VGS
VIL VIH
2 Noise margins:
VM AX − VM
N ML = VIL − VOL = VM − − VM IN
|Av (VM )|
1 VM IN
N MH = VOH −VIH = VM AX −VM (1+ )+
|Av (VM )| |Av (VM )|
Need to compute |Av (VM )|.

Small-signal equivalent circuit model at VM (transistor in

saturation):
R
D
G
+ + +
vin vgs gmvgs ro vout
- - S -
+ +
vin gmvin ro//R vout
- -
vout = −gm vin(ro//R)

Then:
vout
Av = = −gm(ro //R) −gm R
vin
Then:
|Av (VM )| = gm (VM )R
From here, get N ML and N MH using above formulae.
2 Dynamics
• CL pull-down limited by current through transistor

[will study in detail with CMOS]
• CL pull-up limited by resistor (tP LH ∼ RCL)
• pull-up slowest
VDD VDD
R R
VOUT: VOUT:
HI LO LO HI
VIN: VIN:
CL HI LO CL
LO HI
pull-down pull-up
2 Inverter design issues:
noise margins ↑ ⇒ |Av | ↑ ⇒
• R ↑ ⇒ RCL ↑ ⇒ slow switching

• gm ↑ ⇒ W ↑ ⇒ big transistor
(slow switching at input)
Trade-off
Trade-off between speed
speed and noise margin.
margin.
During pull-up, need:
• high current for fast switching,

• but also high resistance for high noise margin.
⇒ use current source as pull-up.

2. NMOS inverter with current-source pull-up
I-V characteristics of current source:
iSUP
ISUP 1
roc
vSUP iSUP
0
0 vSUP
Equivalent circuit models:
iSUP
ISUP roc roc

vSUP
large-signal model small-signal model
• high current throughout voltage range: iSU P ISU P

• high small-signal resistance, roc.
NMOS inverter with current-source pull-up:
VDD load line

iSUP=ID
VGS=VDD
iSUP
ISUP
VOUT VGS=VIN
VIN
CL
VGS=VT
0
0 VDD VDS
Transfer characteristics:
VOUT
VDD
0
0 VT VDD VIN
High roc ⇒ high noise margin

Dynamics:
VDD VDD
iSUP iSUP
VOUT: VOUT:
HI LO LO HI
VIN: VIN:
LO HI CL CL
HI LO
pull-down pull-up
Fas pull-up because capacitor charged at constant cur-

Faster
rent.
2 PMOS as current-source pull-up
I-V characteristics of PMOS:
IDp
-IDp -IDp
saturation
VSGp
VSGp=-VTp
0 0
0 VSDp 0 VSGp
-VTp
Note: enhancement-mode PMOS has VT p < 0.
In saturation:
−IDp ∝ (VSG + VT p )2
Circuit and load-line diagram of inverter with PMOS cur-

rent source pull-up:
VDD
PMOS load line for VSG=VDD-VB
-IDp=IDn
VDD
VB
VOUT
VIN
VIN
CL
0
0 VDD VOUT
Transfer function:
NMOS cutoff
PMOS triode
VOUT
NMOS saturation
PMOS triode
VDD
NMOS saturation
PMOS saturation
NMOS triode
PMOS saturation
0
0 VTn VDD VIN
Noise margin:
• compute VM = VIN = VOU T

• compute |Av (VM )|
At VM both transistors saturated:
Wn
IDn = µnCox (VM − VT n )2
2Ln
Wp
−IDp = µp Cox(VDD − VB + VT p )2
2Lp
And:
IDn = −IDp
Then:
�
�
µp W
� p
�
�
� Lp
VM = VT n + �
�
Wn (VDD − VB + VT p )
�
µn L n
Small-signal equivalent circuit model at VM :
S2
+
vsg2=0 gmpvsg2 rop

-
G2 D2
D1
+ +
G1
+
vin vgs1 gmnvgs1 ron vout
- - -
S1
+ +
vin gmnvin ron//rop vout
- -
Av = −gmn (ron//rop )
Screen shots of NMOS inverter transfer characteristics:
2 NMOS inverter with resistor pull-up
2 NMOS inverter with current source pull-up
NMOS inverter with current-source pull-up allows fast

switching with high noise margins.
But... when VIN = VDD , there is a direct current path

between supply and ground
⇒ power consumption even if inverter is idling.
VDD PMOS load line for VSG=VDD-VB

-IDp=IDn
VDD
VB
VOUT:LO VIN
VIN:HI
CL
0
0 VDD VOUT
Would like to have current source that is itself switchable,

i.e., it shuts off when input is high ⇒ CMOS!
Circuit schematic:
VDD
VIN VOUT
CL
Basic operation:
•VIN = 0 ⇒ VOU T = VDD
VGSn = 0 < VT n ⇒ NMOS OFF
VSGp = VDD > −VT p ⇒ PMOS ON
•VIN = VDD ⇒ VOU T = 0
VGSn = VDD > VT n ⇒ NMOS ON
VSGp = 0 < −VT p ⇒ PMOS OFF
power
No p ower consumption while idling in an
anyy logic state.
Output characteristics of both transistors:
IDn -IDp
VGSn VSGp
VGSn=VTn VSGp=-VTp
0 0
0 VDSn 0 VSDp
Note:
VIN = VGSn = VDD − VSGp ⇒ VSGp = VDD − VIN
VOU T = VDSn = VDD − VSDp ⇒ VSDp = VDD − VOU T
IDn = −IDp
Combine into single diagram of ID vs. VOU T with VIN as

parameter.
VDD
ID
VIN VOUT
VDD-VIN VIN
CL
0
0 VOUT
no current while idling in any logic state.
Transfer function:
NMOS cutoff
PMOS triode
VOUT NMOS saturation
PMOS triode
VDD
NMOS saturation
PMOS saturation
NMOS triode
PMOS saturation
NMOS triode
PMOS cutoff
0
0 VTn VDD+VTp VDD VIN
”r
”rail-to-rail”
ail-to-rail” lo
logic:
gic: logic levels are 0 and VDD
logic
highh |A
|Av | ar logic thresholdd ⇒ go
ound logic
around od noise margins
good
Transfer characteristics of CMOS inverter in WebLab:
Key conclusions
• In NMOS inverter with resistor pull-up: trade-off be-

tween noise margin and speed.
• Trade-off resolved using current-source pull-up: use
PMOS as current source.
• In NMOS inverter with current-source pull-up: if VIN =
HI, power consumption even if inverter is idling.
• Complementary MOS: NMOS and PMOS switch al-
ternatively ⇒
– no power consumption while idling
– ”rail-to-rail” logic: logic levels are 0 and VDD
– high |Av | around logic threshold ⇒ good noise
margins
Lecture 14 - Digital Circuits (III)
CMOS
October 27, 2005
Contents:
1. Complementary MOS (CMOS) inverter: introduction
2. CMOS inverter: noise margins

3. CMOS inverter: propagation delay
4. CMOS inverter: dynamic power
Reading assignment:
Announcements:
• Cadence tutorial by Kerwin Johnson in place of reg-

ular recitations on Friday 10/28
Key questions
• How does CMOS work?

• What is special about CMOS as a logic technology?
• What are the key design parameters of a CMOS in-

verter?
• How can one estimate the propagation delay of a
CMOS inverter?
• Does CMOS burn any power?
Circuit schematic:
VDD
VIN VOUT
CL
Basic operation:
•VIN = 0 ⇒ VOU T = VDD
VGSn = 0 < VT n ⇒ NMOS OFF
VSGp = VDD > −VT p ⇒ PMOS ON
•VIN = VDD ⇒ VOU T = 0
VGSn = VDD > VT n ⇒ NMOS ON
VSGp = 0 < −VT p ⇒ PMOS OFF

Output characteristics of both transistors:
IDn -IDp
VGSn VSGp
VGSn=VTn VSGp=-VTp
0 0
0 VDSn 0 VSDp
Note:
VIN = VGSn = VDD − VSGp ⇒ VSGp = VDD − VIN
VOU T = VDSn = VDD − VSDp ⇒ VSDp = VDD − VOU T
IDn = −IDp
Combine into single diagram of ID vs. VOU T with VIN as

parameter.
VDD
ID
VIN VOUT
VDD-VIN VIN
CL
0
0 VOUT
no current while id
idling
ling in any lo
logic
gic state
state..
Transfer function:
NMOS cutoff
PMOS triode
VOUT NMOS saturation
PMOS triode
VDD
NMOS saturation
PMOS saturation
NMOS triode
PMOS saturation
NMOS triode
PMOS cutoff
0
0 VTn VDD+VTp VDD VIN
”rail-to-rail” lo
”rail-to-rail” gic: lo
logic: gic levels are 0 and VDD
logic
high |Av | around logic threshold ⇒ good noise margins
Transfer characteristics of CMOS inverter in WebLab:
2. CMOS inverter: noise margins
VOUT
NML
VDD
Av(VM)
VM
0
0 VILVM VIH VDD VIN
NMH
• Calculate VM
• Calculate Av (VM )
• Calculate N ML and N MH
2 Calculate VM (VM = VIN = VOU T )
At VM both transistors saturated:

1 Wn
IDn = µnCox (VM − VT n)2
2 Ln
1 Wp
−IDp = µpCox (VDD − VM + VT p )2
2 Lp
Define:
Wn Wp
kn = µnCox, kp = µpCox
Ln Lp
Since:
IDn = −IDp
Then:
1 1
kn(VM − VT n )2 = kp(VDD − VM + VT p )2
2 2
Solve for VM :
�
�
� kp
�
VT n + kn
(VDD + VT p )
VM = �
�
� kp
�
1+ kn
Usually, VT n and VT p fixed and VT n = −VT p
⇒ VM engineered through kp/kn ratio

• Symmetric case: kn = kp
VDD
VM =
2
This implies:
Wp Wp
kp µC
Lp p ox
µ
Lp p Wp Wn
=1= Wn Wn ⇒ 2
kn Ln µn Cox Ln 2µp Lp Ln
Since usually Lp Ln ⇒ Wp 2Wn.
VOUT
VDD
VIN=VOUT
kn=kp
0
0 VTn VM VDD+VTp VDD VIN
Wp
• Asymmetric case: kn kp , or Wn
Ln
Lp
VM VT n
NMOS turns on as soon as VIN goes above VT n .
Wp
• Asymmetric case: kn kp , or Wn
Ln Lp
VM VDD + VT p
PMOS turns on as soon as VIN goes below VDD + VT p .
Can engineer VM anywhere between VT n and VDD + VT p .

between
VOUT
VDD
VIN=VOUT
kn>>kp
kn=kp
kn<<kp
0
0 VTn VM VDD+VTp VDD VIN
2 Calculate Av (VM ) VDD
Small-signal model:
VIN VOUT
S2
+
vsg2=-vin gmpvsg2 rop
-
G2 D2
D1
+ +
G1
+
vin vgs1 gmnvgs1 ron vout
- - -
S1
G1=G2 D1=D2
+ +
vin gmnvin gmpvin ron//rop vout
- -
S1=S2
Av = −(gmn + gmp )(ron //rop )
This can be rather large.

2 Noise margins
VOUT
NML
VDD
Av(VM)
VM
0
0 VILVM VIH VDD VIN
NMH
• Noise-margin-low:
VDD − VM
VIL = VM −
|Av |
Therefore:
VDD − VM
N ML = VIL − VOL = VIL = VM −
|Av |
In the limit of |Av | → ∞:
N ML → VM
• Noise-margin-high:
VOUT
NML
VDD
Av(VM)
VM
0
0 VILVM VIH VDD VIN
NMH
1
VIH = VM (1 + )
|Av |
and
1
N MH = VOH − VIH = VDD − VM (1 + )
|Av |
In the limit of |Av | → ∞:
N MH → VDD − VM
When VM = VDD
2
⇒ N ML = N MH = VDD
2
3. CMOS inverter: propagation delay
Inverter propagation delay: time delay between input and

output signals; key figure of merit of logic speed.
Typical propagation delays: < 1 ns.
Complex logic system has 20-50 propagation delays per
clock cycle.
Estimation of tp : use square-wave at input

VIN
VDD
tCYCLE
0
t
VOUT tPHL tPLH
VDD
50% tCYCLE
0
t
Average propagation delay:
1
tp = (tP HL + tP LH )
2
2 Propagation delay high-to-low:
VDD
VIN: VOUT:
LO HI HI LO
CL
VDD VDD VDD
VIN=0 VOUT=VDD VIN=VDD VOUT=0
VIN=VDD VOUT=VDD
CL CL CL
t=0- t=0+ t
During early phases of discharge, NMOS is saturated and

PMOS is cut-off.
Time to discharge half of CL:
1
2 charge of CL@t = 0−
tP HL
discharge current
Charge in CL at t = 0−:
QL(t = 0−) = CLVDD
Discharge current (NMOS in saturation):
Wn
IDn = µnCox (VDD − VT n )2
2Ln
Then:
CLVDD
tP HL
Ln µnCox (VDD − VT n )
Wn 2
ID
VDD-VIN VIN
0
0 VOUT
2 Propagation delay low-to-high:
VDD
VIN: VOUT:
HI LO LO HI
CL
VDD VDD VDD
VIN=VDD VOUT=0 VIN=0 VOUT=VDD
VIN=0 VOUT=0
CL CL CL
t=0- t=0+ t
During early phases of charge, PMOS is saturated and
NMOS is cut-off.
Time to charge half of CL:
1
2 charge of CL@t = ∞
tP LH
charge current
Charge in CL at t = ∞:
QL(t = ∞) = CLVDD
Charge current (PMOS in saturation):
Wp
−IDp = µp Cox(VDD + VT p )2
2Lp
Then:
CLVDD
tP LH Wp 2
Lp µ p Cox (V DD + V T p )
ID
VDD-VIN VIN
0
0 VOUT
Key dependencies of propagation delays:
• VDD ↑⇒ tp ↓
Reason: VDD ↑⇒ Q(CL) ↑, but also ID ↑
Trade-off: VDD ↑, more power usage.
• L ↓⇒ tp ↓
Reason: L ↓⇒ ID ↑
Trade-off: manufacturing costs!
Components of load capacitance CL:
• following logic gates: must add capacitance presented

by each gate of every transistor the output is con-
nected to
• interconnect wire that connects output to input of
following logic gates
• own drain-to-body capacitances
CL = CG + Cwire + CDBn + CDBp
VDD
VOUT
VIN
Cwire
[See details in Howe & Sodini §5.4.3]

4. CMOS inverter: dynamic power
• In any of the two logic states: one transistor always

OFF ⇒ zero static power dissipation.
• Dynamic power?
Every complete transient, CL is charged up to VDD and

then discharged to 0
⇒ energy dissipated
⇒ clock frequency ↑ ⇒ dissipated power ↑
2 Dynamic power dissipated while charging load
VDD
VOUT
iDD(t)=iC(t)
VDD
VIN=HI LO VOUT=LO HI
CL
0
0 t
1. Energy provided by battery during transient:
�
∞ �
∞ dvOU T
ES =
0
V i
DD C (t)dt = V DD 0
C L
dt =
�
dt
VDD 2
=
CLVDD 0
dvOU T = CLVDD
2. Energy stored in capacitor during transient:
1 2
∆EC = EC (t = ∞) − EC (t = 0) = CL VDD
2
3. Energy dissipated in PMOS during transient:
1 2
EP = ES − ∆EC = CLVDD
2
2 Dynamic power dissipated while discharging load
VDD
iDD(t)=0 VOUT
VDD
VIN=LO HI VOUT=HI LO
iC(t) CL
0
0 t
1. Energy provided by battery during transient:
�
∞
ES = 0 VDD iDD (t)dt =0
2. Energy removed from capacitor during transient:
1 2
∆EC = EC (t = 0) − EC (t = ∞) = CL VDD
2
3. Energy dissipated in NMOS during transient:
1 2
EN = ∆EC = CLVDD
2
2 Energy dissipated in complete cycle
2
ED = EP + EN = ΣES = CLVDD
2 Power dissipation
If complete switching cycle takes place f times per second:
2
PD = f ED = f CLVDD
Fundamental
Fundamental trade-off between switching
switching speed
speed ant power
power
dissipation!
Key dependencies in dynamic power:
• f ↑⇒ PD ↑, charge and discharge CL more frequently

• CL ↑⇒ PD ↑, more charge being shuttled around
• VDD ↑⇒ PD ↑, more charge being shuttled around
Key conclusions
• Key features of CMOS inverter:

– no current while idling in any logic state
– ”rail-to-rail” logic: logic levels are 0 and VDD

– high |Av | around logic threshold ⇒ good noise
margins
• CMOS inverter logic threshold and noise margins en-

gineered through Wn/Ln and Wp/Lp .
• Key dependences of propagation delay:
– VDD ↑ ⇒ tp ↓
– L ↓ ⇒ tp ↓
• Dynamic power dissipated in CMOS:
2
PD = f ED = f CLVDD
Fundamental trade-off between switching speed and

power dissipation.
Lecture 15 - The pn Junction Diode (I)
I-V Characteristics
November 1, 2005
Contents:
1. pn junction under bias

Reading assignment:

Key questions
• Why does the pn junction diode exhibit current rec-

tification?
• Why does the junction current in forward bias increase
as ∼ exp qV
kT ?
• What are the leading dependences of the saturation

current (the factor in front of the exponential)?
1. PN junction under bias
Focus on intrinsic region:
��
��
n type
p type
��
x
p type
�� (a)
��
metal contact
to p side
(Na) p
x=0
��
(Nd) n
(b)
metal contact to
n side
Upon application of voltage:
• electrostatics upset: depletion region widens or shrinks
• current flows (with rectifying behavior)

• carrier charge storage
Carrier profiles in thermal equilibrium:
log po, no
Na
Nd
po no
ni2
ni2 Nd
Na
0 x
Jhdiff
Jhdrift
Jediff
Jedrift
Inside SCR in thermal equilibrium: dynamic balance be-

tween drift and diffusion for electrons and holes.
|Jdrif t| = |Jdif f |
Carrier concentrations in pn junction under bias:
• for V > 0, φB − V ↓ ⇒ |ESCR | ↓⇒ |Jdrif t | ↓

log p, n
Na
Nd
po no
p
n
ni2
ni2 Nd
Na
0 x
Jhdiff
Jhdrift
Jh
Jediff
Jedrift
Je
Current balance in SCR broken:
|Jdrif t| < |Jdif f |
Net diffusion current in SCR

⇒ minority carrier injection
injection into QNR’s
⇒ exc ess minority carrier concentrations in QNR’s
excess
Lots of majority carriers in QNR’s ⇒ current can be high.
• for V < 0, φB − V ↑ ⇒ |ESCR | ↑⇒ |Jdrif t | ↑

log p, n
Na
po Nd
no
ni2
n i2 Nd
Na p
n
0 x
Jh Jhdiff
Jhdrift
Jediff
Je
Jedrift
Current balance in SCR broken:
|Jdrif t| > |Jdif f |
Net drift current in SCR

⇒ minority carrier extraction
extraction from QNR’s
⇒ deficit of minorit
minorityy carrier concentrations in QNR’s
Few minority carriers in QNR’s ⇒ current small.
What happens if minority carrier concentrations in QNR

change from equilibrium?
⇒ Balance between generation and recombination broken
• In thermal equilibrium: rate of break up of Si-Si bonds

balanced by rate of formation of bonds
generation
Si-Si bond no + p o
recombination
• If minority carrier injection:

⇒ carrier concentration above equilibrium
⇒ recom
recombination
bination prevails
Si-Si bond n+p

recombination
• If minority carrier extraction:

⇒ carrier concentrations below equilibrium
⇒ generation prevails
generation
Si-Si bond n+p
Where does generation and recombination take place?
In modern devices, recombination mainly takes place at

surfaces:
• perfect crystalline periodicity broken at a surface
⇒ lots of broken bonds: generation and recombina-

tion centers
• modern devices are very small
⇒ high area to volume ratio.
High generation and recombination activity at surfaces
⇒ carrier concentrations cannot deviate much from equi-

librium values:
n(s) no, p(s) po
Complete physical picture for pn diode under bias:
• Forward bias: injected minority carriers diffuse through

QNR ⇒ recombine at semiconductor surface
log p, n
Na
po Nd
no
p
n
ni2
ni2 Nd
Na
0 x
• Reverse bias: minority carriers extracted by SCR ⇒

generated at surface and diffuse through QNR
log p, n
Na
po Nd
no
ni2
ni2 Nd
Na p
n
0 x
The current view:
• Forward bias:
p n
hole injection
and recombination at surface
electron injection
and recombination at surface
I=In+Ip
• Reverse bias:
p n
hole generation at surface

and extraction
electron generation at surface

and extraction
I=In+Ip
What limits the magnitude of the diode current?
• not generation or recombination rate at surfaces
• not injection or extraction rates through SCR
• diffusion rate through QNR’s
p n
hole injection and

recombination at
surface
electron injection
and recombination
at surface
-Wp -xp xn Wn x
Development of analytical current model:
1. Calculate concentration of minority carriers at edges

of SCR, p(xn) and n(−xp )
2. calculate minority carrier diffusion current in each
QNR, In and Ip
3. sum electron and hole diffusion currents, I = In + Ip
2 Step 1: computation of minority carrier boundary

conditions at edges of SCR
In thermal equilibrium in SCR, |Jdrif t| = |Jdif f |, and
no(x1 ) q[φ(x1 ) − φ(x2)]

= exp
no(x2 ) kT
and
po (x1 ) −q[φ(x1 ) − φ(x2 )]
= exp
po (x2 ) kT
Under bias in SCR, |Jdrif t | = |Jdif f |, but if difference

small with respect to absolute values of current:
n(x1 ) q[φ(x1 ) − φ(x2 )]

exp
n(x2 ) kT
and
p(x1 ) −q[φ(x1 ) − φ(x2 )]
exp
p(x2 ) kT
This is called quasi-equilibrium.

p - + n
p-QNR SCR n-QNR

φ
-xp
0
φB-V φB 0 xn x
At edges of SCR, then:
n(xn) q[φ(xn ) − φ(−xp )] q(φB − V )

exp = exp
n(−xp ) kT kT
and
p(xn ) −q[φ(xn ) − φ(−xp )] −q(φB − V )
exp = exp
p(−xp ) kT kT
But:
p(−xp ) Na and n(xn) Nd
This is the low-level inje

injection
ction approximation
approximation [will discuss
in more detail next time].
Then:
q(V − φB )
n(−xp ) Nd exp
kT
and
q(V − φB )
p(xn) Na exp
kT
Built-in potential:
kT NdNa
φB = ln 2
q ni
Plug in above and get:
n2i qV
n(−xp ) exp
Na kT
and
n2i qV
p(xn) exp
Nd kT
Voltage dependence:
• Equilibrium (V = 0):
n2i n2i
n(−xp ) =
p(xn ) =
Na Nd
• Forward (V > 0):
n2i n2i
n(−xp )
p(xn )
Na Nd
Lots of carriers available for injection:
⇒ V ↑→ concentration of injected carriers ↑
⇒ forward current can be high.
• Reverse (V < 0):

n2i n2i
n(−xp )
p(xn )
Na Nd
Few carriers available for extraction:
⇒ reverse current is small.
Minority carrier concentration becomes vanishingly
small:
⇒ reverse current saturates.
Rectification property of pn diode arises from minority-

carrier boundary conditions at edges of SCR.
2 Step 2: Diffusion current in QNR:
Diffusion equation (for electrons in p-QNR):
dn
Jn = qDn
dx
Inside p-QNR, electrons diffuse to reach and recombine
at contact ⇒ Jn constant in p-QNR⇒ n(x) linear.

n
n(-xp)
n(x)
ni2
Na
-Wp -xp x
0
Boundary conditions:
n2i n2i qV
n(x = −Wp) = no =
n(−xp ) =
exp
Na Na kT
Electron profile:
np (−xp ) − np (−Wp )
np (x) = np (−xp) + (x + xp)
−xp + Wp
np (−xp ) − np (−Wp )
np (x) = np (−xp) + (x + xp)
−xp + Wp
Electron current density:
dn np(−xp ) − np (−Wp)
Jn = qDn = qDn
dx Wp − xp
n2i
n2i
Na
exp
kT
− Na
qV
= qDn
Wp − xp
or
n2i Dn qV
Jn = q (exp − 1)
Na Wp − xp kT
Similarly for hole flow in n-QNR:
p
p(xn)
p(x)
ni2
Nd
x
0 xn Wn
Hole current density:
n2i Dp qV
Jp = q (exp − 1)
Nd Wn − xn kT
2 Step 3: sum both current components:
1 Dn 1 Dp qV
J = Jn+Jp = qn2i ( + )(exp −1)
Na Wp − xp Nd Wn − xn
kT
Current:
1 Dn 1 Dp qV
I = qAn2i ( +
)(exp − 1)
Na Wp − xp Nd Wn − xn
kT
often written as:
qV
I = Io(exp − 1)
kT
with
Io ≡ saturation current [A]
B.C.’s contain both forward and reverse bias

⇒ equation valid in forward and reverse bias.
[will discuss this result in detail next time]

Key conclusions
• Application of voltage to pn junction results in disrup

-
tion of balance between drift and diffusion in SCR:
– in forward bias, minority carriers are injected into

quasi-neutral regions
– in reverse bias, minority carriers are extracted from
quasi-neutral regions
• In forward bias, injected minority carriers recombine
at surface.
• In reverse bias, extracted minority carriers are gener-
ated at surface.
• Computation of boundary conditions across SCR ex-
ploits quasi-equilibrium: balance between diffusion
and drift in SCR disturbed very little.
• Rate limiting step to current flow: diffusion through
quasi-neutral regions.
• I-V characteristics of p-n diode:
qV
I = Io(exp − 1)
kT
Lecture 16 - The pn Junction Diode (II)
Equivalent Circuit Model
November 3, 2005
Contents:
1. I-V characteristics (cont.)

2. Small-signal equivalent circuit model
3. Carrier charge storage: diffusion capacitance
Reading assignment:
Howe and Sodini, Ch. 6, §§6.4, 6.5, 6.9
Announcements:
Quiz 2: 11/16, 7:30-9:30 PM,

open book, must bring calculator; lectures #10-18.
Key questions
• How does a pn diode look like from a small-signal

point of view?
• What are the leading dependences of the small-signal
elements?
• In addition to the junction capacitance, are there any
other capacitive effects in a pn diode?
1. I-V characteristics (cont.)
Diode current equation:
qV
I = Io(exp − 1)
kT
Physics of forward bias:
Fp
p n
Fn
• potential difference across SCR reduced by V ⇒ mi-

nority carrier injection in QNR’s
• minority carrier diffusion through QNR’s
• minority carrier recombination at surface of QNR’s
• large supply of carriers available for injection
⇒ I ∝ eqV /kT
Fp
p n
Fn
Physics of reverse bias:
• potential difference across SCR increased by V

⇒ minority carrier extraction from QNR’s
• minority carrier diffusion through QNR’s
• minority carrier generation at surface of QNR’s
• very small supply of carriers available for extraction
⇒ I saturates to small value
I-V characteristics: I = Io(exp qV

kT
− 1)
I log |I|
0.43 q
kT
=60 mV/dec @ 300K
Io
0
0 V 0 V
Io
linear scale semilogarithmic scale
Source/drain-body pn diode of NMOSFET:

Key dependences of diode current:
1 Dn 1 Dp qV
I = qAn2i ( + )(exp − 1)
Na Wp − xp Nd Wn − xn kT
n2i
•I∝ N − 1) ≡ excess minority carrier concen-
(exp qV
kT
T
ratio at edges
tration ges of
o SCR
n2i
– in forward bias: I ∝ exp qV kT : the more carrier
N
are injected, the more current flows
n2i
– in reverse bias: I ∝ −N :
the minority carrier
concentration drops to negligible values and the
current saturates
• I ∝ D: faster diffusion ⇒ more current

1
• I ∝ WQNR : shorter region to diffuse through ⇒ more
urre
current
• I ∝ A: bigger diode ⇒ more current

2. Small-signal equivalent circuit model
Examine effect of small signal overlapping bias:
q(V + v)
I + i = Io[exp − 1]
kT
If v small enough, linearize exponential characteristics:
qV qv qV qv
I + i = Io(exp exp − 1) Io [exp (1 + ) − 1]
kT kT kT kT
qV qV qv
= Io(exp − 1) + Io(exp )
kT kT kT
Then:
q(I + Io)
i= v
kT
From small signal point of view, diode behaves as con-

ductance of value:
q(I + Io)
gd =
kT
Small-signal equivalent circuit model, so far:
gd
gd depends on bias. In forward bias:
qI
gd
kT
gd is linear in diode current.

Must add capacitance associated with depletion region:
gd Cj
Depletion or junction capacitance:
Cjo
Cj =
1 − φVB
3. Carrier charge storage: diffusion capaci-

tance
What happens to the majority carriers?
Carrier picture so far:
log p, n
Na
po Nd
no
p
n
ni2
ni2 Nd
Na
0 x
If in QNR minority carrier concentration ↑ but majority

carrier concentration unchanged
⇒ quasi-neutrality is violated.
Quasi-neutrality demands that at every point in QNR:

excess minority carrier concentration
= excess majority carrier concentration
n n-QNR
n(xn)
n(x)
qNn
Nd
p(xn)
p(x)
qPn
ni2
Nd
xn x
0 Wn
Mathematically:
p (x) = p(x) − po n (x) = n(x) − no
Define integrated carrier charge:
qP n = qA 12 p (xn)(Wn − xn) =
2
Wn −xn ni
= qA 2 Nd (exp qV
kT − 1) = −qNn
Now examine small increase in V :
n n-QNR V
+-
n(xn) -
∆qNn=-∆qPn I
n(x) p n
Nd
p
p(xn) + ∆qPn
p(x)
ni2
Nd
xn x
0 Wn
Small increase in V ⇒ small increase in qP n ⇒ small

increase in |qNn|
Behaves as capacitor of capacitance:
dqP n
Cdn = |V
dV
Can write qP n in terms of Ip (portion of diode current

due to holes in n-QNR):
(Wn − xn)2 n2i Dp qV

qP n = qA (exp − 1)
2Dp Nd Wn − xn kT
(Wn − xn)2
= Ip
2Dp
Define transit time of holes through n-QNR:
(Wn − xn)2
τT p =
2Dp
Transit time is average time for a hole to diffuse through

n-QNR [will discuss in more detail in BJT]
Then:
qP n = τT p Ip
and
q
Cdn τT pIp
kT
Similarly for p-QNR:
qNp = τT nIn
q
Cdp τT nIn
kT
where τT n is transit time of electrons through p-QNR:
(Wp − xp)2
τT n =
2Dn
Both capacitors sit in parallel ⇒ total diffusion capaci-

tance:
q q
Cd = Cdn + Cdp = (τT nIn + τT pIp ) = τT I
kT kT
with:
τT nIn + τT p Ip
τT =
I
Note that
qP n + qNp = τT nIn + τT p Ip = τT I
Complete small-signal equivalent circuit model for diode:
gd Cj Cd
Bias dependence of Cj and Cd:

C
Cd
C
Cj
2Cjo
0
0 φB/2 V
• Cd dominates in strong forward bias (∼ eqV /kT )
• Cj √
dominates in reverse bias and small forward bias
(∼ 1/ φB − V )
- For strong forward bias, model for Cj invalid (doesn’t

blow up)
- Common ”hack”, let Cj saturate at value corre-

sponding to V = φ2B
√
Cj,max = 2Cjo
Key conclusions
Small-signal behavior of diode:
• conductance: associated with current-voltage charac-

teristics
gd ∼ I in forward bias, negligible in reverse bias
• junction capacitance: associated with charge modu-

lation in depletion region

Cj ∼ 1/ φB − V
• diffusion capacitance: associated with charge storage

in QNR’s to keep quasi-neutrality
Cd ∼ eqV /kT
Cd ∼ I
Lecture 17 - The Bipolar Junction Transistor
(I)
Forward Active Regime
November 8, 2005
Contents:
1. BJT: structure and basic operation

2. I-V characteristics in forward active regime
Reading assignment:
Howe and Sodini, Ch. 7, §§7.1, 7.2
Announcements:
Quiz 2: 11/16, 7:30-9:30 PM,
Key questions
• What does a bipolar junction transistor look like?
• How does a bipolar junction transistor operate?

• What are the leading dependencies of the terminal
currents of a BJT in the forward active regime?
1. BJT: structure and basic operation
base emitter base collector

contact contact contact contact
n+ emitter
p base n+ plug
n collector
"intrinsic" BJT
n+ buried layer
p substrate
base-collector junction
base-emitter junction (area AE) collector-substrate junction
emitter-stripe length
emitter-stripe width
Uniqueness of BJT: high-current drivability per input ca-

pacitance ⇒ fast ⇒ excellent for analog and front-end
communications applications.
Simplified one-dimensional model of intrinsic device:
Emitter Base Collector
n p n
IE IC
NdE NaB NdC
- -
IB
VBE VBC
+ +
x
-WE-XBE -XBE 0 WB WB+XBC WB+XBC+WC
BJT = two neighbouring pn junctions back-to-back:
• close enough for minority carriers to interact
(can diffuse quickly through base)
• far apart enough for depletion regions not to interact

(prevent ”punchthrough”)
Regimes of operation:
collector
VBE
IC
- +
VBC forward saturation
active
IB +
base
VCE
+ VBC
VBE
- - cut-off reverse
IE
emitter
Basic operation in forward-active regime:
n-Emitter p-Base n-Collector
IC>0
IE<0
IB>0
VBE > 0 VBC < 0
VBE > 0 ⇒ injection of electrons from E to B

injection of holes from B to E
VBC < 0 ⇒ extraction of electrons from B to C

extraction of holes from C to B
Transistor effect:
electrons injected from E to B, extracted by C!
• Carrier profiles in thermal equilibrium:
log po, no
NdE NaB
po NdC
no
no po
ni2
NdC
ni2
ni2
NdE
NaB
x
• Carrier profiles in forward-active regime:
log p, n
NdE NaB
NdC
p n
ni2
NdC
ni2 ni2
NdE NaB
x
Dominant current paths in forward active regime:
IC>0
IE<0
IB>0
VBE > 0 VBC < 0
IC : electron injection from E to B and collection into C

IB : hole injection from B to E
IE = −IC − IB
Key dependencies (choose one):
qVBE /kT
√
IC on VBE : e , 1/ VBE , none, other
qVBC /kT
√
IC on VBC : e , 1/ VBC , none, other
qVBE /kT
√
IB on VBE : e , 1/ VBE , none, other
qVBC /kT
√
IB on VBC : e , 1/ VBC , none, other
IC on IB : exponential, quadratic, none, other

In forward-active regime:
• VBE controls IC (”transisto

”transistorr effect”)
effect”
• IC independent of VBC (”isolat ion”)
”isolation”
• price to pay for control: IB
Comparison with MOSFET:

ideal MOSFET
ideal BJT
feature in saturation
in FAR
controlling terminal gate

base
common terminal source

emitter
controlled terminal drain

collector
functional dependence
of controlled current quadratic
exponential
DC current in
controlling terminal 0
exponential
Figure of merit for BJT:
-common-emitter current gain:
βF = IC
IB
(want big enough, 100)
2. I-V characteristics in forward active regime
2 Collector current: focus on electron diffusion in base
n
npB(0)
npB(x)
JnB
ni2 npB(WB)=0
NaB
x
0 WB
qVBE
npB (0) = npBo exp , npB (WB ) = 0
kT
Electron profile:
x
npB (x) = npB (0)(1 − )
WB
Electron current density:
dnpB npB (0)

JnB = qDn = −qDn
dx WB
Collector current scales with area of base-emitter junction

AE :
B E B
IC AE
Collector terminal current:

Dn qVBE
IC = −JnB AE = qAE npBo exp
WB kT
or
qVBE
IC = IS exp
kT
IS ≡ collector saturation current [A]

2 Base current: focus on hole injection and recombina-

tion in emitter
p
pnE(-xBE)
pnE(x)
ni2
pnE(-WE-xBE)=
NdE
ni2
NdE
-WE-xBE -xBE x
qVBE
pnE (−xBE ) = pnEo exp , pnE (−WE −xBE ) = pnEo
kT
Hole profile:
x + xBE
pnE (x) = [pnE (−xBE ) − pnEo ](1 + ) + pnEo
WE
Hole current density:
dpnE pnE (−xBE ) − pnEo

JpE = −qDp = −qDp
dx WE
Base current scales with area of base-emitter junction AE :

B E B
IB AE
Base terminal current:

Dp qVBE
IB = −JpE AE = qAE pnEo(exp − 1)
WE kT
Then:
IS qVBE
IB =
(exp − 1)
βF kT
For VBE kT
q
:
IC
IB
βF
Gummel plot: semilog plot of IC and IB vs. VBE :
log IC, IB
IC
IB
60 mV/dec
at 300 K
IS
IS
VBC<0
βF
VBE
2 Current gain:
D
IC npBo WBn NdE DnWE
βF = = Dp =
IB pnEo W NaB DpWB
E
To maximize βF :
• NdE NaB
• WE WB
• want npn
npn,, rather than pnp design because Dn > Dp
State-of-the-art IC BJT’s today: IC ∼ 0.1−1 mA, βF ∼

50 − 300
βF hard to control in manufacturing environment ⇒ need

circuit techniques that are insensitive to variations in βF
βF dependence on IC :
βF
log IC
Gummel plot of BJT (VCE = 3 V ):

Key conclusions
npn BJT in forward active regime:
IC>0
IE<0
IB>0
VBE > 0 VBC < 0
• Emitter ”injects” electrons into Base,

Collector ”collects” electrons from Base.
⇒ IC controlled by VBE , independent of VBC
(transistor effect)
qVBE
IC ∝ exp
kT
• Base injects holes into Emitter ⇒ IB
IB ∝ IC
Lecture 18 - The Bipolar Junction Transistor
(II)
Regimes of Operation
November 10, 2005
Contents:
1. Regimes of operation.
2. Large-signal equivalent circuit model.
3. Output characteristics.
Reading assignment:
Howe and Sodini, Ch. 7, §§7.3, 7.4
Announcements:
Quiz 2: 11/16, 7:30-9:30 PM,
Key questions
• What other regimes of operation are there for the

BJT?
• What is unique about each regime?
• How do equivalent circuit models for the BJT look

like?
1. Regimes of operation
VBE
- +
VBC forward saturation

active
+
B
VCE
+
VBC
VBE
- - cut-off reverse
E
• forward active: device has good isolation and high

gain; most useful regime;
• saturation: device has no isolation and is flooded with
minority carriers ⇒ takes time to get out of satura-
tion; avoid
• reverse: poor gain; not useful;
• cut-off: negligible current: nearly an open circuit;

useful.
2 Forward-active regime: VBE > 0, VBC < 0
IC>0
IE<0
IB>0
VBE > 0 VBC < 0
Minority carrier profiles (not to scale):
emitter base collector
pnE npB pnC
pnCo
pnEo npBo
x
• Emitter injects electrons into base, collector collects

electrons from base:
qVBE
IC = IS exp
kT
• Base injects holes into emitter, recombine at emitter

contact:
IS qVBE
IB = (exp − 1)
βF kT
• Emitter current:
qVBE IS qVBE
IE = −IC − IB = −IS exp − (exp − 1)
kT βF kT
• State-of-the-art IC BJT’s today: IC ∼ 0.1 − 1 mA,

βF 50 − 300.
• βF hard to control tightly ⇒ circuit design techniques

required to be insensitive to variations in βF .
2 Reverse regime: VBE < 0, VBC > 0
IE>0 IC<0
IB>0
VBE < 0 VBC > 0
Minority carrier profiles:

pnE npB pnC
pnCo
pnEo npBo
x
• Collector injects electrons into base, emitter collects

electrons from base:
qVBC
IE = IS exp
kT
• Base injects holes into collector, recombine at collector

contact and buried layer:
IS qVBC
IB = (exp − 1)
βR kT
• Collector current:
qVBC IS qVBC
IC = −IE − IB = −IS exp − (exp − 1)
kT βR kT
• Typically, βR 0.1 − 5 βF .
B E B B E B
IE AE
IB AC
C C
Forward-active Gummel plot (VCE = 3 V ):
Reverse Gummel (VEC = 3 V ):

2 Cut-off: VBE < 0, VBC < 0
IE>0 IC>0
IB<0
VBE < 0 VBC < 0

pnE npB pnC
pnCo
pnEo npBo
x
• Base extracts holes from emitter:
IS
IB1 = − = −IE
βF
• Base extracts holes from collector:
IS
IB2 = − = −IC
βR
• These are tiny leakage currents (∼ 10−12 A).

2 Saturation: VBE > 0, VBC > 0
IE IC
IB<0
VBE > 0 VBC > 0

pnE npB pnC
pnCo
pnEo npBo
x
Saturation is superposition of forward active + reverse:
qVBE qVBC IS qVBC

IC = IS (exp − exp ) − (exp − 1)
kT kT βR kT
IS qVBE IS qVBC
IB = (exp − 1) + (exp − 1)
βF kT βR kT
IS qVBE qVBE qVBC
IE = − (exp − 1) − IS (exp − exp )
βF kT kT kT
• IC and IE can have either sign, depending on relative

magnitude of VBE and VBC , and βF and βR.
• In saturation, collector and base flooded with excess

minority carriers ⇒ takes lots of time to get transistor
out of saturation.
B E B
electrons
holes
2. Large-signal equivalent circuit model
System of equations that describes BJT operation:
qVBE qVBC IS qVBC

IC = IS (exp − exp ) − (exp − 1)
kT kT βR kT
IS qVBE IS qVBC
IB = (exp − 1) + (exp − 1)
βF kT βR kT
IS qVBE qVBE qVBC
IE = − (exp − 1) − IS (exp − exp )
βF kT kT kT
Equivalent-circuit model representation:

Non-Linear
Non-Line ar Hybrid-π MoModel
del
C
IS qVBC
(exp -1)
βR kT
qVBE qV
B IS (exp - exp BC )
kT kT
IS qVBE
(exp -1)
βF kT
Three parameters in this model: IS , βF , and βR.

Model equivalent to Ebers-Moll model in text.
Simplifications of equivalent-circuit model:
• Forward-active regime: VBE > 0, VBC < 0

C C
IB
qVBE B
B IS exp βFIB
kT
IS qVBE
(exp -1) VBE,on
βF kT
E E
For today’s technology: VBE,on 0.7 V .

IB depends on outside circuit.
• Reverse: VBE < 0, VBC > 0

C C
IS qVBC VBC,on
(exp -1)
βR kT
qVBC
B IS exp B βRIB
kT
IB
E
E
For today’s technology: VBC,on 0.5 V .

IB also depends on outside circuit.
IB vs. VBE for VCE = 3 V :
IB vs. VBC for VEC = 3 V :
• Saturation: VBE > 0, VBC > 0

C C C
VBC,on VBC,on
B B B
VCE,sat
VBE,on VBE,on
E E E
Today’s technology: VCE,sat = VBE,on − VBC,on 0.2 V .

IB and IC depend on outside circuit.
• Cut-off: VBE < 0, VBC < 0
Only negligible leakage currents.
3. Output characteristics
First, IC vs. VCB with IB as parameter:

IC
IB
IB=0
0
0 VCB
VBC,on
Next, common-emitter output characteristics

(IC vs. VCE with IB as parameter):
IC
IB
IB=0
0
0 VCE=VCB+VBE
VCE,sat
IC vs. VCB for 0 ≤ IB ≤ 100 µA:
IC vs. VCE for 0 ≤ IB ≤ 100 µA:
IC vs. VCE for 0 ≤ IB ≤ 100 µA:

Key conclusions
• Forward-active regime: most useful, device has gain

and isolation. For bias calculations:
IB
B C
VBE,on βFIB
• Saturation: device flooded with minority carriers. Not

useful. For bias calculations:
C
VBC,on
B
VCE,sat
VBE,on
• Cut-off: device open. Useful. For bias calculations:
E
Lecture 19 - Transistor Amplifiers (I)
Common-Source Amplifier
November 15, 2005
Contents:
1. Amplifier fundamentals
2. Common-source amplifier
3. Common-source amplifier with current-source supply
Reading assignment:
Announcements:
Quiz 2: 11/16, 7:30-9:30 PM,
Quiz 2 TA Review Session: 11/15, 7:30-9:30 PM,
Key questions
• What are the key figures of merit of an amplifier?
• How can one make a voltage amplifier with a single

MOSFET and a resistor?
• How can this amplifier be improved?
1. Amplifier fundamentals
Goal of amplifiers: signal amplification.
vOUT
+V
output
+ + signal
vIN RL vOUT
- - vIN
-V
input signal
Features of amplifier:
• Output signal is faithful replica of input signal but

amplified in magnitude.
• Active device is at the heart of amplifier.
• Need linear transfer characteristics for distortion

not to be introduced.
Signal could be represented by current or voltage
⇒ four broad types of amplifiers:
RS
voltage +
vs +
RL vout
− amplifier
−
RS iout
vs + transconductance RL
−
amplifier
+
is
transresistance vout
RS RL
amplifier −
iout
current
is RS RL
amplifier
More realistic transfer characteristics:
vOUT
Q output
signal
vIN
input signal
• Transfer characteristics linear over limited range of

voltages: amplifier saturation.
• Amplifier saturation limits signal swing.
• Signal swing also depends on choice of bias point, Q

(also called quiescent point or operating point).
Other features desired in amplifiers:

• Low power consumption.
• Wide frequency response [will discuss in a few days].
• Robust to process and temperature variations.

• Inexpensive: must minimize use of unusual compo-
nents, must be small (in Si area)
2. Common-Source Amplifier
Consider the following circuit:
V+=VDD
RD iR
signal source
signal
RS iD + load
RL
vs vOUT
VGG
-
V-=VSS
Consider it first unloaded by RL. How does it work?
• VGG, RD and W/L of MOSFET selected to bias tran-

sistor in saturation and obtain desired output bias
point (i.e. VOU T = 0).
• vGS ↑ ⇒ iD ↑ ⇒ iR ↑ ⇒ vout ↓
• Av = vvout
s
< 0; output out of phase from input, but if
amplifier well designed, |Av | > 1.
[watch notation: vOU T (t) = VOU T + vout(t)]

Load line view of amplifier:
IR=ID load line
VDD-VSS VGG-VSS=VDD-VSS
RD
VGG-VSS
VGG-VSS=VT
0
VSS VDD VOUT
Transfer characteristics of amplifier:
VOUT
VDD
VSS
0 VT VDD-VSS VGG-VSS
Want:
• Bias point calculation;
• small-signal gain;
• limits to signal swing
• frequency response [in a few days]
2 Bias point: choice of VGG, W/L, and RD to keep

transistor in saturation and to get proper quiescent VOU T .
Assume MOSFET is in saturation:
W
ID = µnCox (VGG − VSS − VT )2
2L
VDD − VOU T
IR =
RD
If we select VOU T = 0:
W 2 VDD
ID = IR = µnCox (VGG − VSS − VT ) =
2L RD
Then:
�
�
�
� 2VDD
VGG = �
�
W + VSS + VT
�
RD L µnCox
2 Small-signal voltage gain: draw small-signal equiva-

lent circuit model:
RD
D
G
+ + +
vin vgs gmvgs ro vout
- - S -
+ +
vin gmvin ro//RD vout
- -
vout = −gm vin(ro//RD )
unloaded
Then unloaded voltage gain:
vout
Avo = = −gm (ro//RD )
vin
2 Signal swing:
VDD
RD
signal source
+
RS
vs vOUT
VGG -
VSS
• Upswing: limited by transistor going into cut-off:
vout,max = VDD
• Downswing: limited by MOSFET entering linear regime:
VDS,sat = VGS − VT
or
vout,min − VSS = VGG − VSS − VT
Then:
vout,min = VGG − VT
2 Effect of input/output loading:

VDD
RD iR
signal source iL
RS iD +
RL
vs vOUT
VGG
-
VSS
• Bias point not affected because selected VOU T = 0.

• Signal swing:
– Upswing limited by resistive divider:
RL
vout,max = VDD
RL + RD
– Downswing not affected by loading
• Voltage gain:
– input loading (RS ): no effect because gate does
not draw current;
– output loading (RL ): RL detracts from voltage
gain because it draws current.
|Av | = gm(ro //RD //RL) < gm (ro //RD )
2 Generic view of loading effect on small-signal operation:
Two-port network view of small-signal equivalent circuit

model of voltage amplifier:
Rin is input resistance
Rout is output resistance
Avo is unloaded voltage gain
RS Rout
+ +
+ +
vs vin Rin Avovin vout RL
- -
- -
input output
unloaded circuit
loading loading
Voltage divider at input: vin = Rin Rinv+R

s
S
Voltage divider at output: vin

vout = RL RAoutvo+R L
Loaded voltage gain:
vout Rin RL
Av = = Avo
vs Rin + RS RL + Rout
• Calculation of input resistance, Rin:
- load amplifier with RL

- apply test voltage (or current) at input, measure test
current (or voltage)
For common-source amplifier:
it
+
+
vt vgs gmvgs ro//RD RL

-
-
vt
it = 0 ⇒ Rin = = ∞
it
No effect of loading at input.
• Calculation of output resistance, Rout :
- load amplifier at input with RS

- apply test voltage (or current) at output, measure
test current (or voltage)
it
+
+
RS vgs gmvgs ro//RD vt
-
-
vgs = 0 ⇒ gm vgs = 0 ⇒ vt = it(ro //RD )
vt
Rout = = ro//RD
it
Two-port network view of common-source amplifier:
RS Rout
+ +
+ +
vs vin Rin Avovin vout RL
- -
- -
input output
unloaded circuit
loading loading
vout
Av =
vs
Rin RL RL
= Avo = −gm(ro //RD )
Rin + RS RL + Rout RL + ro //RD
Or:
Av = −gm (ro //RD //RL )

2 Design issues of common-source amplifier (unloaded):
Examine bias dependence:
|Avo | = gm(ro //RD ) gm RD
Rewrite |Avo | in the following way:

�
�
W VDD �
� VDD
|Avo | gmRD = 2 µnCox ID ∝
�
� √
L ID ID
Then, to get high |Avo |:

⇒ VDD ↑
⇒ ID ↓
VDD
Both approaches imply ⇒ RD = ID
↑
Consequences of high RD :
• large RD consumes a lot of Si real state

• large RD eventually compromises frequency response
Also, it would be nice not to use any resistors at all!
⇒ Need better circuit.
3. Common-source amplifier with current-source

supply
VDD
iSUP
signal source
signal
RS iD + load
RL
vOUT
vs
VGG
-
VSS
Loadline view:
load line
iSUP=ID
VGG-VSS=VDD-VSS
ISUP VGG-VSS
VGG-VSS=VT
0
VSS VDD VOUT
Current source characterized by high output resistance:

roc.
Then, unloaded voltage gain of common-source stage:
|Avo | = gm (ro //roc )
significantly higher than amplifier with resistive supply.
Can implement current source supply by means of p-

channel MOSFET:
VDD
VB iSUP
signal source
RS iD +
vs vOUT
VGG
-
VSS
• Relationship between circuit figures of merit and device

parameters
Remember:
�
�
�
� W
gm = 2 �
� µnCox ID
L
1 L
ro ∝
λnID ID
Then:
Circuit Parameters
Device ∗ |Avo | Rin Rout
Parameters gm (ro//roc ) ∞ ro//roc
ISU P ↑ ↓ - ↓
W ↑ ↑ - -
µnCox ↑ ↑ - -
L↑ ↑ - ↑
∗
adjustments are made to VGG so
none of the other parameters change
CS amp with current supply source is good voltage am-

plifier (Rin high and |Av | high), but Rout high too ⇒
voltage gain degraded if RL ro//roc .
Key conclusions
• Figures of merit of an amplifier:

– gain
– signal swing
– power consumption
– frequency response
– robustness to process and temperature variations
• Common-source amplifier with resistive supply: trade-
off between gain and cost and frequency response.
• Trade-off resolved by using common-source amplifier

with current source supply.
• Two-port network computation of voltage gain, input
resistance and output resistance of amplifier.
Lecture 20 - Transistor Amplifiers (II)
Other Amplifier Stages
November 17, 2005
Contents:
1. Common-source amplifier (cont.)

2. Common-drain amplifier
3. Common-gate amplifier
Reading assignment:

Key questions
• What other amplifier stages can one build with a sin-

gle MOSFET and a current source?
• What is the uniqueness of these other stages?
1. Common-source amplifier with current-source

supply
VDD
iSUP
signal source
signal
RS iD + load
RL
vs vOUT
VGG
-
VSS
Loadline view:
load line
iSUP=ID
VGG-VSS=VDD-VSS
ISUP VGG-VSS
VGG-VSS=VT
0
VSS VDD VOUT
Current source characterized by high output resistance:

roc.
Then, unloaded voltage gain of common-source stage:
|Avo | = gm (ro //roc )
significantly higher than amplifier with resistive supply.
Can implement current source supply by means of p-

channel MOSFET:
VDD
VB iSUP
signal source
RS iD +
vs vOUT
VGG
-
VSS
• Relationship between circuit figures of merit and device

parameters
Remember:
�
�
�
W �
�
gm = 2 µnCox ID
�
L
1 L
ro ∝
λnID ID
Then:
Circuit Parameters
Parameters gm (ro//roc ) ∞ ro//roc
ISU P ↑ ↓ - ↓
W ↑ ↑ - -
µnCox ↑ ↑ - -
L↑ ↑ - ↑
∗
CS amp with current supply source is good voltage am-

plifier (Rin high and |Av | high), but Rout high too ⇒
voltage gain degraded if RL ro//roc .
Common-source amplifier is acceptable voltage amplifier

(want high Rin, high Avo , low Rout ):
RS Rout
+ +
vs + vin + Avovin
Rin RL vout
− −
− −
... but excellent transconductance amplifier

(want high Rin, high Gmo , high Rout ):
RS iout
+
vs + vin Gmovin RL
Rin Rout
−
−
Gmo = gm
Common-source amplifier does not work as transresis-

tance amplifier (want low Rin, high Rmo , low Rout ):
iin Rout
+
is + Rmoiin vout
RS Rin RL
−
−
nor as current amplifier

(want low Rin, high Aio , high Rout ):
iin iout
is RS Rin Aioiin Rout RL
Need new amplifier configurations.
2. Common-drain amplifier
VDD
signal source
RS
signal
vs + load
iSUP RL
vOUT
VGG
-
VSS
How does it work?
• VGG, ISU P , and W/L selected to bias MOSFET in

saturation, obtain desired output bias point, and de-
sired output swing.
• vG ↑ ⇒ iD can’t change ⇒ vOU T ↑
(source
(sour follower)
r)
ce follower
• to first order, no voltage gain: vout vs
• but Rout small: effective voltage buffer stage
(good for making voltage amp in combination with
common-source stage).
2 Small-signal analysis
Unloaded small-signal equivalent circuit model:
D
G
+ +
vgs gmvgs ro
- S
vin
+
roc vout
- -
+ vgs -
+ +
vin gmvgs ro//roc vout
- -
vin = vgs + vout
vout = gmvgs(ro //roc)
Then:
gm
Avo = 1 1
gm + ro //roc
Input impedance: Rin = ∞
Output impedance:
+ vgs -
it
+
+
RS vin gmvgs ro//roc vt
-
-
vgs=-vt
effectively:
it
resistance of
value 1/gm
+
gmvt ro//roc vt
-
1 1
Rout = 1
gm + ro //roc
gm
small!
Loaded voltage gain:
RL RL
Av = Avo 1 1
RL + Rout RL + gm
2 Effect of back bias:
If MOSFET not fabricated on isolated p-well, then body
is tied up to wafer substrate (connected to VSS ):
VDD
signal source
RS
VSS
signal
+ load
vs
iSUP RL
vOUT
VGG
-
VSS
Two consequences:
• Bias affected: VT depends on VBS = VSS − VOU T = 0
• Small-signal figures of merit affected: signal shows up

between B and S (vbs = −vout).
Small-signal equivalent circuit model:
D
G
+ +
vgs gmvgs gmbvbs ro
- S
vin -
+
vbs roc vout
- +B -
vbs=-vout
+ vgs -
+ +
vin gmvgs gmbvout ro//roc vout
- -
gm gm
Avo = 1 <1
gm + gmb + ro //roc
gm + gmb
Also:
1 1
Rout = 1
gm + gmb + ro //roc
gm + gmb
2 Relationship between circuit figures of merit and device

parameters:
�
�
�
�
�
W
gm = 2 � µnCox ID
L
gmb = � gm
2 −2φp − VBS
Circuit Parameters
1
Parameters gmg+g
m
mb
∞ gm+gmb
ISU P ↑ - - ↓
W ↑ - - ↓
µnCox ↑ - - ↓
L↑ - - ↑
∗
CD amp useful as a voltage buffer to drive small loads

(in a multistage amp, other stages will be used to provide
voltage gain).
3. Common-gate amplifier
Need to handle current-mode signal sources:
VDD
iSUP
iOUT signal
load
VSS
RL
signal source
is RS IBIAS
VSS
How does it work?

• since source is signal input terminal, body cannot be
tied up to source (Cdb is significant)
• iSU P , IBI AS , and W/L selected to bias MOSFET in
saturation, obtain desired output bias point, and de-
sired output swing
• iS ↑ ⇒ iD ↓ ⇒ iOU T ↓
• no current gain: is = −iout (curr
(current
ent buffer)
bufferr)
2 Bias: select ISU P , IBI AS , and W/L to get proper qui-

escent IOU T and keep MOSFET in saturation.
VDD
ISUP
IOUT
VSS
IBIAS
VSS
ISU P + IOU T + IBI AS = 0
Select bias so that IOU T = 0 ⇒ VOU T = 0.
Assume MOSFET in saturation (no channel modulation):
W
ID = µnCox (VGS − VT )2 = ISU P = −IBI AS
2L
but VT depends on VBS :
� �
VT = VT o + γn( −2φp − VBS − −2φp )
Must solve these two equations iteratively to get VS .
2 Small-signal circuit (unloaded)

iout
D
+ G
vgs gmvgs gmbvbs ro

- S
roc
-
vbs is
+ B
vbs=vgs
is vgs gmvgs gmbvgs ro

+
iout
is gm gmb ro
iout
iout
is = −iout ⇒ Aio = − = −1
is
Not surprising, since in a MOSFET: ig = 0.
Input resistance:
+
vgs gmvgs gmbvgs ro

-
roc RL
+
it vt
-
vgs=-vt
gmvt gmbvt ro
it vt
roc//RL
-
Do KCL on input node:

vt − (roc //RL )it
it − gmvt − gmbvt − =0
ro
Then:
1 + roc //R L
1
Rin = ro

gm + gmb + r1o gm + gmb
Very small.
Output resistance:
+
vgs gmvgs gmbvgs ro it

- +
roc vt
-
RS
vgs gmvgs gmbvgs ro it'

- +
vt'
-
RS
Do KCL on input node:

vt
+ vgs
i
t − gmvgs − gmb vgs − =0
ro
Notice also:
vgs = −i
tRS
Then:
1
Rout = roc//{ro [1+RS (gm +gmb + )]} roc//[ro (1+gm RS )]
ro
Very large, because of the feedback effect of RS .

Summary of MOSFET amplifier stages:
stage Avo , Gmo , Aio Rin Rout key function
common source Gmo = gm ∞ ro //roc transconductance amp.
gm 1
common drain Avo gm +gmb ∞ gm +gmb voltage buffer
1
common gate Aio −1 gm +gmb roc //[ro(1 + gm RS )] current buffer
In order to design amplifiers with suitable performance,
need to combine these stages ⇒ multistage amplifiers

Key conclusions
Different MOSFET stages designed to accomplish differ-

ent goals:
• Common-source stage:
– large voltage gain and transconductance, high in-

put resistance, large output resistance
– excellent transconductance amplifier, reasonable volt-
age amplifier
• Common-drain stage:
– no voltage gain, but high input resistance and low

output resistance
– good voltage buffer
• Common-gate stage:
– no current gain, but low input resistance and high

output resistance
– good current buffer
Lecture 21 - Multistage Amplifiers (I)
Multistage Amplifiers
November 22, 2005
Contents:
1. Introduction
2. CMOS multistage voltage amplifier
3. BiCMOS multistage voltage amplifier
4. BiCMOS current buffer
5. Coupling amplifier stages
Reading assignment:

Key questions
• How can one build a wide range of high-performance

amplifiers using the single-transistor stages studied so
far?
• What are the most important considerations when
assembling mulstistage amplifiers:
– regarding interstage loading?
– regarding interstage biasing?
1. Introduction
Amplifier requirements are often demanding:

• must adapt to specific kinds of signal source and load,
• must deliver sufficient gain
Single-transistor amplifier stages are very limited in what

they can accomplish ⇒ multistage amplifier.
VDD
signal source
RS
signal
+ load
vs RL
vOUT
-
VS
VSS
Issues:
• What amplifying stages should be used and in what
order?
• What devices should be used, BJT or MOSFET?
• How is biasing to be done?

2 Summary of single stage characteristics:
stage Avo , Gmo , Aio Rin Rout key function
CS Gmo = gm ∞ ro //roc transcond. amp.
gm 1
CD Avo gm +gmb ∞ gm +gmb voltage buffer
1
CG Aio −1 gm +gmb roc //[ro (1 + gm RS )] current buffer
CE Gmo gm rπ ro //roc transcond. amp.
1 RS
CC Avo 1 rπ + β(ro //roc //RL ) gm + β voltage buffer
1
CB Aio −1 gm
roc //{ro [1 + gm (rπ //RS )]} current buffer
2 Key differences between BJT’s and MOSFETs:
BJT MOSFET
IB = IβC IG = 0
�
qIC
gm = kT
> gm = 2 WL µCoxID
VA
ro = IC
> ro = 1
λID
2. CMOS multistage voltage amplifier
2 Goals:
• high voltage gain

• high Rin
• low Rout
2 Good starting point: CS stage
RS ro//roc
+ +
+ +
vs vin -gm(ro//roc)vin vout RL
- -
- -
• Rin = ∞
• Avo = −gm(ro //roc ), probably insufficient
• Rout = ro//roc, too high
2 Add second CS stage to get more gain:
RS ro1//roc1 ro2//roc2
+ + +
+ + +
vs vin1 -gm1(ro1//roc1)vin1 vout1=vin2 -gm2(ro2//roc2)vin2 vout2 RL
- - -
- - -
• Rin = ∞
• Avo = gm1(ro1 //roc1 )gm2 (ro2 //roc2 )
• but Rout = ro2//roc2 , still high
2 Add CD stage at output:
1
RS ro2 ⎢⎢roc2 gm3 + gmb3
+ + +
vs + + Avovin +
vin vin3 vout RL
− − −v gm3
in3
gm3 + gmb3
− − −
CS − CS CD
• Rin = ∞
• Avo = gm1(ro1 //roc1 )gm2 (ro2 //roc2 ) gm3g+g
m3 , still high
mb3
• Rout = 1
gm3 +gmb3
, now small
3. BiCMOS multistage voltage amplifier
2 Avo (CE) > Avo (CS) because ro(BJ T ) > ro(M OSF ET )
and gm (BJ T ) > gm(M OSF ET ) but...
CS stage is best first stage, since Rin = ∞.
2 Add CE stage following CS stage?
RS ro1 ⎢⎢roc1 ro2 ⎢⎢roc2
+ +
+
vs + vin1
+ Avo1vin1 vin2 rπ2 + Avo2vin2 vout RL
− − −
−
− −
CS CE
Trouble is interstage loading degrades gain:

Rout1 = ro1 //roc1 Rin2 = rπ2
Voltage divider between stages:
Rin2 rπ2 rπ2

= 1
Rout1 + Rin2 ro1 //roc1 + rπ2 ro1 //roc1
Additional gain provided by CE stage more than lost in

interstage loading.
2 Use two CS stages, but add CC stage at output:
1 ro2 ⎢⎢roc2
RS ro2 ⎢⎢roc2 gm3 + β3
+ +
+
+ + vin3 +
vs vin Avo1Avo2vin rπ3 + β3(ro3 ⎢⎢roc3 ⎢⎢RL) vin3 vout RL
− − −
−
− −
CS − CS CC
Interstage loading:
Rout2 = ro2//roc2 , Rin3 = rπ3 + β3(ro3 //roc3 //RL)
Then, interstage loss:

Rin3 rπ3 + β3(ro3 //roc3 //RL )
=
Rout2 + Rin3 ro2 //roc2 + rπ3 + β3(ro3 //roc3 //RL)
better than trying to use a CE stage, but still pretty bad.
Benefit is that Rout has improved:

1 Rout2 1 ro2 //roc2
Rout = Rout3 = + = +
gm3 β3 gm3 β3
Since, in general, gm (BJ T ) > gm (M OSF ET ), Rout

could be better than CD output stage if ro2//roc2 is not
too large. Otherwise, CD stage output is better.
2 Better voltage buffer: cascade CC and CD output

stages.
What is best order? Since Rin(CD) = ∞, best to place

CD first:
1 1 1
RS ro2 ⎢⎢roc2 gm3 + gmb3 gm4 + β (g + g )
4 m3 mb3
+ + +
+
vs + + Avo1Avo2vin vin3 + vin3 + vin4 vout
vin vin4 rπ4 + β4(RL ⎢⎢ro4 ⎢⎢roc4) RL
− − − −
−
− − −
CS − CS CD − CC
Interstage loading:
Rin3
=1
Rout2 + Rin3
Rin4 rπ4 + β4(ro4 //roc4 //RL)

= 1
Rout3 + Rin4 1
gm3 +g
+ rπ4 + β4(ro4//roc4 //RL )
mb3
and excellent output resistance:
1 Rout3 1 1
Rout = Rout4 = + = +
gm4 β4 gm4 β4(gm3 + gmb3 )
4. BiCMOS current buffer
2 Goals:
• Unity current gain

• very low Rin
• very high Rout
Start with common-base stage:
iin iout
is RS 1/gm -iin roc//(βro) RL
• Aio = −1
• Rin = 1
gm
• Rout = roc//{ro [1 + gm(rπ //RS )]}
Note that if RS is not too low, Rout roc //(βro).
Can we further increase Rout by adding a second CB

stage?
2 CB-CB current buffer:
iin1 iin2 iout
1 −iin1 1 −iin2
is RS gm1 β1ro1 ⎢⎢roc1 gm2 RL
CB CB
[ gm2ro2(rπ2 ⎢⎢β1ro1 ⎢⎢roc1)] ⎢⎢roc2
Now
Rout = Rout2 = roc2 //{ro2 [1 + gm2 (rπ2 //Rout1 )]}
Plugging in Rout1 roc1//(β1 ro1 ),
Rout = roc2//{ro2 [1 + gm2 (rπ2 //roc1 //β1 ro1)]}
But, since rπ2 roc1 //(β1 ro1), then
Rout roc2 //[ro2 (1 + gm2rπ2 )] roc2 //(β2ro2 )
Did not improve anything! The base current limits the

number
n ve Rout to just one.
improve
umber of CB stages that impro
Since CG stage has no gate current, cascade it behind CB

stage.
2 CB-CG current buffer:
iin1 iin2 iout
1 −iin1 1 −iin2
is RS gm1 β1ro1 ⎢⎢roc1 gm2 RL
CB CG
[gm2ro2(β1ro1 ⎢⎢roc1)] ⎢⎢roc2
Rout = Rout2 = roc2//[ro2 (1 + gm2 Rout1 )]
with Rout1 roc1 //(β1 ro1),
Rout = roc2 //[ro2 gm2 (roc1 //β1ro1 )]
Now Rout has improved by about gm2ro2 , but only to the

extent that roc2 is high enough...
5. Coupling amplifier stages
2 Capacitive coupling
Capacitors of large enough value behave as AC short, so
signal goes through but bias is independent for each stage.
Example, CD-CC voltage buffer:

5.0 V 5.0 V
3.2 V
4.0 V
2.5 V
2.5 V
ISUP1 ISUP2
Assumes VBE = 0.7 V
VGS = 1.5 V
• Advantages:
– can select bias point for optimum operation
– can select bias point close to middle of rails for
maximum signal swing
• Disadvantages:
– to approximate AC short, need large capacitors

that consume significant area
2 Direct coupling: share bias points across stages.
Example, CD-CC voltage buffer:
5.0 V 5.0 V
4.7 V 3.2 V
2.5 V
ISUP1 ISUP2
Assumes VBE = 0.7 V
VGS = 1.5 V
• Advantages:
– no capacitors: compact
• Disadvantages:
– bias point shared: constrains design
– bias shifts from stage to stage and can stray too

far from center of range
Solution: use PMOS CD stage:
5.0 V 5.0 V
ISUP1
3.2 V
1.7 V 2.5 V
ISUP2
Assumes VBE = 0.7 V
VGS = 1.5 V
Trade-off: gm(PMOS)< gm (NMOS) → higher Rout
In BiCMOS voltage amplifier:
1 1
Rout = +
gm4 β4(gm3 + gmb3 )
2 Summary of DC shifts through amplifier stages:
Transistor Type
Amplifier
Type
NMOS PMOS npn pnp
V+ V+ V+ V+
IN
iSUP iSUP IN
Common
Source/ OUT OUT OUT
IN OUT
Common
IN
Emitter iSUP iSUP
(CS/CE )
V− V− V− V−
V+ V+ V+ V+
iSUP IN iSUP IN
Common OUT
Gate/ OUT
OUT
Common OUT
Base
(CG/CB) iSUP IN iSUP
IN
V− V− V− V−
V+ V+ V+ V+
IN iSUP iSUP
IN
Common
OUT OUT OUT
Drain/
Common OUT IN
IN
Collector
iSUP iSUP
(CD/CC )
V− V− V− V−
Important difference in bias shift between stages in BJT

and MOSFET amps:
• In BJT (for npn):
VBE VBE,on
rather independent of transistor size and current level.
• In MOSFET (for nMOSFET):

�
�
�
� 2ID L
VGS = VT + �
�
�
µnCox W
Can be engineered through bias current and transistor
geometry.
5.0 V 5.0 V
4.7 V 3.2 V
2.5 V
ISUP1 ISUP2
Assumes VBE = 0.7 V
VGS = 1.5 V
Key conclusions
• To achieve amplifier design goals, several stages often

needed.
• In multistage amplifiers, different stages used to ac-
complish different goals:
– voltage gain: common-source, common emitter
– voltage buffer: common-drain, common collector
– current buffer: common-gate, common base

• In multistage amplifiers must pay attention to inter-
stage loading to avoid unnecessary losses.
• In direct-coupled amplifiers, bias is shared between
adjoining stages:
– must select compromise bias,
– must pay attention to bias shift from stage to stage.
Lecture 22 - Multistage Amplifiers (II)
DC Voltage and Current Sources
November 29, 2005
Contents:
1. DC voltage sources
2. DC current sources and sinks
Reading assignment:
Howe and Sodini, Ch. 9, §§9.4

Key questions
• How does one synthesize voltage and current sources?
• How can this be done in an economic way?

1. DC voltage sources
2 Features of voltage source:
• A well controlled voltage
• voltage does not depend on current drawn from source

(low internal resistance).
I-V characteristics of voltage source:
ideal real
0
0 VS V
Equivalent circuit model of voltage source:
RS
+
Vs
-
2 Consider MOSFET in ”diode configuration”:

ID
ID
+
VGS
+ VDS
VGS −
−
VGS=VT
0
0 VT VDS
I-V characteristics:
W W
ID = µCox (VGS − VT )2 = µCox (VDS − VT )2
2L 2L
Beyond threshold, MOSFET looks like ”diode” with quadratic

I-V characteristics.
2 How does one synthesize a voltage source with this?
Assume a current source is available.

iOUT
VDD
IREF
iOUT
iD
+ 0
vOUT VT vOUT
−
-IREF
VGS = VDS takes value needed to sink current:
W
ID = IREF + iOU T = µCox(vOU T − VT )2
2L
Then:
W
iOU T = µCox (vOU T − VT )2 − IREF
2L
Solving for vOU T :

IREF + iOU T

vOU T = VT +

W

2L
µCox
vOU T is function of IREF and W/L of MOSFET:

• IREF ↑ ⇒ vOU T ↑
• W/L ↑ ⇒ vOU T ↓
iOUT iOUT
W/L
IREF
VT VT
vOUT vOUT
−IREF1 −IREF
−IREF2
2 Small-signal view of voltage source:
D G it
+
+
ro gmvgs vgs vt
-
-
S
1 1
Rout = //ro
gm gm
Rout is small (good!).

2 PMOS voltage source:
VDD
iOUT
+
IREF VOUT
−
Same operation and characteristics as NMOS voltage source.
PMOS needs to be bigger to attain same Rout .

2. DC current sources and sinks
2 Features of current source:
• A well controlled current,

• supplied current does not depend on voltage across
(high internal resistance)
I-V characteristics of current source:
real
Is
ideal
0
0 V
Equivalent circuit model of current source:
Is RS
2 Connect voltage source to another MOSFET:
VDD
IREF iOUT
+
M1 M2 vOUT
+
VREF −
−
⎛ ⎞
1 ⎜W ⎟
IOU T ⎝ ⎠ µCox (VREF − VT )2
2 L 2
⎛ ⎞
1 W
IREF ⎜⎝ ⎟⎠ µCox(VREF − VT )2
2 L 1
Then:

W
L 2
IOU T = IREF
W
L 1
IOU T scales with IREF by W/L ratios of two MOSFETs

(current
(curr ent mirror circuit).
Well ”matched” transistors important.
• Small-signal view of current source:
it
+
1 +
gm1 vgs2 gm2vgs2 ro2 vt
-
-
Rout = ro2
I-V characteristics of NMOS current source:
iOUT
(W/L)2
IREF
(W/L)1 1/ro2
VDS vOUT
SAT2
2 PMOS current source
• NMOS current source sinks current to ground.
• PMOS current source ssources

ources
o current from positive
supply.
PMOS current mirror:
VDD
M1 M2
iOUT
IREF
2 Multiple current sources
Since there is no DC gate current in MOSFET, can tie

up multiple current mirrors to single current source:
VDD
M1 M2
MR M3
iOUT1 iOUT2 iOUT3
IREF

W
IOU T n = IREF
WL n
L R
Similar idea with NMOS current sinks:
VDD
IREF iOUT1 iOUT2 iOUT3
MR
+
M1 M2 M3
VREF
−
2 Multiple current sources and sinks
Often, in a given circuit, we need current sources and
sinks. Can build them all out of a single current source:
VDD
M1
MR M2
iOUT1 iOUT2
iOUT4
IREF
M3 M4

W
IOU T 1 = IREF
WL 1
L R

W
IOU T 2 = IREF
WL 2
L R

W W W
IOU T 4 = IOU T 1
WL 4 = L 4 L 1
IREF
W
W
L 3 L 3 L R
2 Generating IREF :
Simple circuit:
VDD
VDD −VOU T
IREF R IREF = R

IREF
+
VOU T = VT +

W µC
2L ox
VOUT
−
For large W/L, VOU T → VT :
VDD − VT
IREF
R
• Advantages:
– IREF set by value of resistor.
• Disadvantages:
– VDD also affects IREF .
– VT and R are function of temperature ⇒ IREF (T ).
In real world, more sophisticated circuits used to generate

IREF that are VDD and T independent.
2 Can now understand more complex circuits.
Examples:
+2.5 V
RS
M1
IREF
vs +
−
VBIAS + +
−
vOUT
M3 M2
−
−2.5 V
Amp stages:
What does it do?

2 Can now understand more complex circuits.
Examples:
+2.5 V
RS
M1
IREF
vs +
−
VBIAS + +
−
vOUT
M3 M2
−
−2.5 V
Amp stages:
What does it do?

2.5 V
RS
IREF M1
Vs +
−
VBIAS + +
−
RL vOUT
M3 M2
−
−2.5 V
Amp stages:
What does it do?

2.5 V
RS
IREF M1
Vs +
−
VBIAS + +
−
RL vOUT
M3 M2
−
−2.5 V
Amp stages:
What does it do?

+2.5 V
IREF
RS
Q1
vs +
− iOUT
VBIAS +
−
RL
M3 M2
−2.5 V
Amp stages:
What does it do?

+2.5 V
IREF
RS
Q1
vs +
− iOUT
VBIAS +
−
RL
M3 M2
−2.5 V
Amp stages:
What does it do?

+3 V
M2
M2B M4
iOUT
RS M3 +
M1
vs + RL vOUT
6 kΩ
− −
VBIAS +
−
−3 V
Amp stages:
What does it do?

+3 V
M2
M2B M4
iOUT
RS M3 +
M1
vs + RL vOUT
6 kΩ
− −
VBIAS +
−
−3 V
Amp stages:
What does it do?

+2.5 V
M4 M6
Q1
IREF RS
Q2
+
vs +
−
vOUT
VBIAS +
M5 − −
M3 M2
−2.5 V
Amp stages:
What does it do?

+2.5 V
M4 M6
Q1
IREF RS
Q2
+
vs +
−
vOUT
VBIAS +
M5 − −
M3 M2
−2.5 V
Amp stages:
What does it do?

Key conclusions
• Voltage source easily synthesized from current source

using MOSFET in diode configuration.
• Current source easily synthesized from current source
using current mirror circuit.
• Multiple current sources and sinks with different mag-
nitudes of current can be synthesized from a single
current source.
• Voltage and current sources rely on availability of well
”matched” transistors in IC technology.
Lecture 23 - Frequency Response of
Amplifiers (I)
Common-Source Amplifier
December 1, 2005
Contents:
1. Introduction
2. Intrinsic frequency response of MOSFET
3. Frequency response of common-source amplifier
4. Miller effect
Reading assignment:

Key questions
• How does one assess the intrinsic frequency response

of a transistor?
• What limits the frequency response of an amplifier?
• What is the ”Miller effect”?

1. Introduction
Frequency domain is a major consideration in most ana

-
log circuits.
Data rates, bandwidths, carrier frequencies all pushing
up.
Motivation:
• Processor speeds ↑
• Traffic volume ↑ ⇒ data rates ↑
• More bandwidth available at higher frequencies in the
spectrum
60 DOM Radio
50 'V Band'
40
Frequency
WE Datacom
LMDS Teledesic
25
Video Spacewav
20 WirelessMAN
4 Skybridge
MMDS
0 3G
0 2 8 20 40 45 100 155 500
BW (MHz)
Figure by MIT OCW.
2. Intrinsic frequency response of MOSFET
2 How does one assess the intrinsic frequency response

of a transistor?
ft ≡ short-circuit
short-circuit current-gain
-g cut-off frequency [GHz]
Consider MOSFET biased in saturation regime with small-

signal source applied to gate:
VDD
iD=ID+iout
iG=iin
vs
VGG
vs at input ⇒ iout: transistor effect

⇒ iin due to gate capacitance
Frequency dependence: f ↑⇒ iin ↑⇒ | iiout

in
|↓
iout
ft ≡ frequency at which | | = 1
iin
Complete small-signal model in saturation:
iin Cgd iout

G
+ D
+
vs vgs Cgs gmvgs gmbvbs ro
-
-
S - Cdb
vbs Csb
+
B
vbs=0
iin Cgd iout

1 2
+
+
vs vgs Cgs gmvgs
-
-
node 1: iin − vgsjωCgs − vgsjωCgd = 0
⇒ iin = vgsjω(Cgs + Cgd )
node 2: iout − gmvgs + vgsjωCgd = 0
⇒ iout = vgs(gm − jωCgd )

Current gain:
iout gm − jωCgd
h21 = =
iin jω(Cgs + Cgd )
2 Magnitude of h21:
�
2 + ω2C 2
gm gd
|h21| =
ω(Cgs + Cgd )
• For low frequency, ω gm

Cgd
,
gm
|h21|
ω(Cgs + Cgd )
• For high frequency, ω gm

Cgd ,
Cgd
|h21| <1
Cgs + Cgd
log |h21|
-1
1
ωT log ω
Cgd
Cgs+Cgd
|h21| becomes unity at:
gm
ωT = 2πfT =
Cgs + Cgd
Then:
gm
fT =
2π(Cgs + Cgd )
2 Physical interpretation of fT :
Consider:
1 Cgs + Cgd Cgs
=
2πfT gm gm
Plug in device physics expressions for Cgs and gm:

2
1 Cgs 3
LW Cox L
= =
2πfT gm W
L
µCox(VGS − VT ) µ 32 VGSL−VT
or
1 L L
= = τt
2πfT µ < Echan > < vchan >
τt ≡ transit time from source to drain [s]
Then:
1
fT
2πτt
fT gives an idea of the intrinsic delay of the transistor:

good first-order figure of merit for frequency response.
To reduce τt and increase fT :
• L ↓: trade-off is cost
• (VGS − VT ) ↑⇒ ID ↑: trade-off is power
• µ ↑: hard to do
• note: fT independent of W
Impact of bias point on fT :

�
gm W
L µCox (VGS − VT ) 2 WL µCox ID
fT = = =
2π(Cgs + Cgd ) 2π(Cgs + Cgd) 2π(Cgs + Cgd )
fT fT
0 0
VT
0
VGS ID
In typical MOSFET at typical bias points:

fT ∼ 5 − 50 GH z
ft of different device technologies
600
c Fujitsu (02, EDL) c
d UIUC (03, EL) d
500
e IBM (03, IPRM)
Cutoff Frequency [GHz]
f IBM (04, VLSI)

400
III-V HEMT e
300
III-V HBT
200 f
SiGe HBT
100 Si CMOS
0
1985 1990 1995 2000 2005
Year
3. Frequency response of common-source amp
VDD
iSUP
signal source
RS signal
+
load
vOUT RL
vs
-
VGG
VSS
Small-signal equivalent circuit model (assuming current

source has no parasitic capacitance):
RS Cgd
+ +
+
vs vgs Cgs gmvgs Cdb ro roc RL vout
-
- -
Rout'
Low-frequency voltage gain:
vout
Av,LF = = −gm(ro //roc //RL) = −gmRout
vs
RS Cgd
1 2
+ +
+
vs vgs Cgs gmvgs Cdb Rout' vout
-
- -
vs −vgs
node 1: RS − vgsjωCgs − (vgs − vout)jωCgd = 0
node 2: (vgs −vout)jωCgd −gmvgs −voutjωCdb − Rvout

=0
out
Solve for vgs in 2:
jω(Cgd + Cdb ) + R1
out
vgs = vout
jωCgd − gm
Plug in 1 and solve for vout/vs:

−(gm − jωCgd )Rout
Av =
DEN
with
1
DEN = 1 + jω{RS Cgs + RS Cgd [1 + Rout ( + gm)] + Rout Cdb}
RS
−ω 2RS Rout

Cgs (Cgd + Cdb )

[check that for ω = 0, Av,LF = −gmRout ]
Simplify:
1. Operate at ω ωT = gm
Cgs +Cgd
⇒
gm ω(Cgs + Cgd ) > ωCgs , ωCgd
2. Assume gm high enough so that
+ gm gm
RS
3. Eliminate ω 2 term in denominator of Av
⇒ worst-case estimation of bandwidth
Then:

−gmRout
Av ) + R C ]
1 + jω[RS Cgs + RS Cgd (1 + gmRout out db
This has the form:
Av,LF
Av (ω) =
1 + j ωωH
log |Av|
gmRout'
-1
ωH log ω
At ω = ωH :
1
|Av (ωH )| = √ |Av,LF |
2
ωH gives idea of frequency beyond which |Av | starts rolling

off quickly ⇒ bandwidth
1
ωH = ) + R C
RS Cgs + RS Cgd (1 + gmRout out db
Frequency response of common-source amplifier limited

by Cgs and Cgd shorting out the input, and Cdb shorting
out the output.
Can rewrite as:

1
fH =
2π{RS [Cgs + Cgd (1 + |Av,LF |)] + Rout
C }
db
Compare with:
gm
fT =
2π(Cgs + Cgd )
2 In general: fH fT due to
1
• typically: gm RS
• Cdb enters fH but not fT
• presence of |Av,LF | in denominator
2 To improve bandwidth,
• Cgs, Cgd , Cdb ↓ ⇒ small transistor with low parasitics

• |Av,LF | ↓⇒ don’t want more gain than really needed
but...
why is it that effect of Cgd on fH appears to being am-

plified by 1 + |Av,LF |??!!
4. Miller effect
In common-source amplifier, Cgd looks much bigger than

it really is.
Consider simple voltage-gain stage:
iin C
+ +
-
vin Avvin vout
- +
-
What is the input impedance?
iin = (vin − vout)jωC
But
vout = −Av vin
Then:
iin = vin(1 + Av )C
or
vin 1
Zin = =
iin jω(1 + Av )C
From input, C, looks much bigger than it really is. This

is called the Miller effect.
When a capacitor is located across nodes where there is

voltage gain, its effect on bandwidth is amplified by the
voltage gain ⇒ Miller
Mil ler ccappacitance:
acitance:
CM iller = C(1 + Av )
Why?
vin ↑ ⇒ vout = −Av vin ↓↓ ⇒ (vin − vout) ↑↑ ⇒ iin ↑↑
In amplifier stages with voltage gain, it is critical to have

small capacitance across voltage gain nodes.
fundamental
As a result of the Miller effect, there is a
fundamental
gain-bandwidth tradeoff in amplifiers.
gain-bandwidth
Key conclusions
• fT (short-circuit current-gain cut-off frequency): fig-

ure of merit to assess intrinsic frequency response of
transistors.
• In MOSFET, to first order,
1
ft =
2πτt
where τt is transit time of electrons through channel.
• In common-source amplifier, voltage gain rolls off at
high frequency because Cgs and Cgd short out input
and Cdb shorts out output.
• In common-source amplifier, effect of Cgd on band-
width is magnified by amplifier voltage gain.
• Miller effect: effect of capacitance across voltage gain
nodes is magnified by voltage gain
⇒ trade-off between gain and bandwidth.
Lecture 25 - Frequency Response of
Amplifiers (III)
Other Amplifier Stages
December 8, 2005
Contents:
1. Frequency response of common-drain amplifier

2. Cascode amplifier
Reading assignment:
Howe and Sodini, Ch. 9, §9.3.3; Ch. 10, §§10.5, 10.7
Announcement:
Final exam: December 19, 1:30-4:30 PM, duPont; open

book, calculator required; entire subject under examina-
tion but emphasis on lectures #19-26.
Key questions
• Do all amplifier stages suffer from the Miller effect?
• Is there something unique about the common drain

stage in terms of frequency response?
• Can we make a transconductance amplifier with a
large bandwidth?
1. Frequency response of common-drain am-

plifier
VDD
signal source
RS
signal
vs + load
iSUP RL
vOUT
VGG -
VSS
Features:
• voltage gain 1
• high input resistance
• low output resistance
• ⇒ good voltage buffer
High-frequency small-signal model:
Cgd
G D
+

S -
RS
- Cdb
vbs Csb
+
vs +
- +
B
roc RL vout
-
vbs=0
Cgs
+ vgs - +
RS
+ Cgd gmvgs Cdb ro//roc//RL=RL' vout
vs
- -
gmRL
Av,LF = ≤1
1 + gmRL
Compute bandwidth by open-circuit time constant tech-

nique:
1. shut-off all independent sources,
2. compute Thevenin resistance RT i seen by each Ci with

all other C’s open,
3. compute open-circuit time constant for Ci as
τi = RT iCi
4. conservative estimate of bandwidth:
ωH
Στi
2 First, short vs:
Cgs
+ vgs - +
RS Cgd gmvgs Cdb RL' vout
-
2 Time constant associated with Cgs:
v
it + t -
1 2
+ vgs - +
RS gmvgs RL' vout
node 1:
vt + vout
it − =0
RS
node 2:
vout
gm vgs − it − = 0
RL
also
vgs = vt
Solve for vout in 1 and plug into 2:


vt RS + RL
RT gs = =
it 1 + gm R
L
Time constant:

RS + RL
τgs = Cgs
1 + gm R
L
2 Time constant associated with Cgd :
+ vgs -
it +
+
RS vt gmvgs RL' vout
-
-
RT gd = RS
τgd = Cgd RS
2 Time constant associated with Cdb :
+ vgs -
it
+
RS gmvgs RL' vt
-
it
+
gm RL' vt
-

1 R
L
RT db = //R
L
=

gm 1 + gmRL

RL
τdb = Cdb
1 + gmRL
Notice:
RT db = Rout //RL
2 Bandwidth:
1 1
ωH =
τgs + τgd + τdb Cgs RS +RL + Cgd RS + Cdb RL
1+gm R 1+gmR L L
2 If back is not connected to source:
VDD
signal source
RS
VSS
signal
load
vs +
iSUP vOUT RL
-
VGG
VSS
Small-signal equivalent circuit:

Cgd
G D
+

RS -
S - Cdb
+ +
vs vbs Csb roc RL vout
-
-
+
B
Cgs
+ vgs - +
RS -
+ Cgd gmvgs gmbvbs vbs Csb ro//roc//RL=RL' vout

vs
- + -
Cgs
+ vgs - +
RS
+ Cgd gmvgs Csb RL'//(1/gmb)=RL'' vout
vs
- -
gm RL”
Av,LF =
1 + gm RL”
Csb shows up at same location as Cdb before, then band-

width is:
ωH RS +RL” RL ”
Cgs 1+g m RL ”
+ Cgd R S + Csb 1+gm RL”
Simplify:
• CD amp is about driving low RL from high RS ⇒

RS RL”, and
1
ωH
RS ( 1+gCmgsRL” + Cgd ) + Csb 1+gRmLR” L”
• CD stage operates as voltage buffer with Av,LF

1 ⇒ gm RL” 1, and
1
ωH
Cgd RS + Cgmsb
Since Cgd and 1/gm are small, if RS is not too high, ωH

can be rather high (approach ωT ).
2 What happened to the Miller effect in CD amp?
1
ωH
RS ( 1+gCmgsRL” + Cgd ) + Csb 1+gRmLR” L”
Miller analysis of Cgs:
gm RL” 1
Cgs = Cgs(1−Av ) = Cgs(1− ) = Cgs
1 + gmRL” 1 + gm RL”
agrees with above result.

Note, since Av → 1, Cgs → 0.
See in circuit:
iin C
+ +
+
vin Avvin vout
- -
-
CM = C(1 − Av )
if Av 1 ⇒ CM 0: bootstrapping
bootstrapping
2. Cascode amplifier
Common-source stage: excellent transconductance am

-
plifier, but bandwidth hurt by Miller effect.
What’s a circuit designer to do?
Consider CS-CG stage:
VDD VDD
iSUP1 iSUP2
signal source iOUT signal
RS load
vOUT1 VG2 VSS
RL
vs
iOUT1
VG1
IBIAS
VSS VSS
How does this address the problem?

• Rin2 very small ⇒ iOU T 1 can change a lot with vOU T 1
changing little ⇒ small voltage gain in CS stage ⇒
no Miller effect ⇒ high bandwidth
• CG stage also has high bandwidth
Before analyzing CS-CG amp, notice that if we make

iSU P 1 = iSU P 2 = iSU P , amplifier drastically simplified:
VDD VDD
iSUP iSUP
signal source iOUT signal
RS load
vOUT1 VG2 VSS
RL
vs
iOUT1
VG1
IBIAS
VSS VSS
VDD
iSUP
iOUT signal
load
VG2 VSS
RL
signal RS
source
vs
VG1
VSS
VDD
iSUP
iOUT signal
load
VG2 VSS
RL
signal RS
source
vs
VG1
VSS
Small-signal equivalent circuit model:

(gm2+gmb2)vgs2
RS Cgd1
+ ro2
+ -
vs vgs1 Cgs1 gm1vgs1 Cdb1 ro1 vgs2 Cgs2+Csb2 Cgd2+Cdb2 roc//RL=RL'

-
+
-
Time constants associated with Cgs1 and Cgd2 +Cdb2 have

not changed.
Time constant associated with Cdb1 + Cgs2 + Csb2 small

(looking into Rin2 1/gm ).
Focus on time constant associated with Cgd1 :
vt
+ -
+
it
RS vgs1 gm1vgs1 gm2+gmb2
-
From Lecture 24:
1 gm1
τgd1 =[ + RS (1 + )]Cgd1
gm2 + gmb2 gm2 + gmb2
If transistors identical (gm1 = gm2 ):
τgd1 2RS Cgd1
Much smaller than in single stage CS tansconductance

amp:

τgd = [Rout + RS (1 + gm Rout )]Cgd
Cascode:
Casco de: excellent transconductance amplifier with high
bandwidth.
Key conclusions
• Common-drain amplifier:
– Voltage gain 1, Miller effect nearly completely
eliminates impact of Cgs (bootstrapping)
– if RS is not too high, CD amp has high bandwidth
• Cascode amplifier:
– effective sharing of current source
– Miller effect minimized by reducing voltage gain of
CS stage as a result of low input impedance of CG
stage
– transconductance amplifier with high bandwidth
Lecture 26 - 6.012 Wrap-up
December 13, 2005
Contents:
1. 6.012 wrap-up
Announcements:
Final exam TA review session: December 16, 7:30-9:30

PM,
Final exam: December 19, 1:30-4:30 PM, duPont; open

book, calculator required; entire subject under examina-
tion but emphasis on lectures #19-26.
1. Wrap up of 6.012
2 The amazing properties of Si
• two types of carriers: electrons and holes
– however, can make good electronic devices with

just one, i.e. MESFET (Metal-Semiconductor Field-
Effect Transistor), or HEMT (High Electron Mo-
bility Transistor)
– but, can’t do complementary logic (i.e. CMOS)
without two
• carrier concentrations can be controlled by addition

of dopants
– over many orders of magnitude (about 20!)
– and in short length scales (nm range)
37 nm gate length MOSFET from Intel (IEDM ’05)
• carrier concentrations can be controlled electrostati

-
cally over many orders of magnitude (easily 10!)
• carriers are fast:

– electrons can cross L = 0.1 µm in about:
L 0.1 µm
τ= = 7 = 1 ps
ve 10 cm/s
– high current density:
Je = qnve = 1.6 × 10−19 C × 1017 cm−3 × 107 cm/s

= 1.6 × 105 A/cm2
⇒ high current drivability to capacitance ratio
• extraordinary physical and chemical properties
– can control doping over 8 orders of magnitude (p
type and n type)
– can make very low resistance ohmic contacts
– can effectively isolate devices by means of pn junc-

tions, trenches and SOI
2 The amazing properties of Si MOSFET
polysilicon gate
body source drain
gate
n+
p+ n+ n+

n channel
• ideal properties of Si/SiO2 interface:

– can drive surface all the way from accumulation
to inversion (carrier density modulation over 16
orders of magnitude)
– not possible in GaAs, for example
• performance improves as MOSFET scales down in

size; as L, W ↓:
– current:
W
µCox (VGS − VT )2 unchanged
ID =
2L
– capacitance:
Cgs = W LCox ↓↓
– figure of merit for device switching delay:
CgsVDD 2 2VDD
=L ↓↓
ID µ(VGS − VT )2
• No gate current.
• VT can be engineered.
• MOSFETs come in two types: NMOS and PMOS.
• Easy to integrate.
2 The amazing properties of Si CMOS
• Rail-to-rail logic: logic levels are 0 and VDD .

• No power consumption while idling in any logic state.
• Scales well.
As L, W ↓:
– Power consumption (all dynamic):

2 2
Pdiss = f CLVDD ∝ f W LCoxVDD ↓↓
– Propagation delay:
CLVDD
tP ∝ W ↓↓
L
µCox (VDD − VT ) 2
– Logic density:
1 1
Density ∝ = ↑↑
A WL
100
10
Cell Area (um2)
0.57 um2
0.5x every cell on 65 nm
2 years generation
0.1
1993 1995 1997 1999 2001 2003 2005 2007
Transistor density continues to double every 2 years
INTEL 6-T SRAM CELL SIZE TREND
Figure by MIT OCW.

Transistors
1,000,000,000
Itanium R 2 Processor
Itanium R Processor
100,000,000
Pentium R 4 Processor
Pentium R III Processor
Pentium R II Processor 10,000,000
Pentium R Processor
1,000,000
486TM DX Processor
286
386TM Processor 100,000
8086
10,000
8008 8080
4004 1,000
1970 1975 1980 1985 1990 1995 2000 2005
M O O R E ' S L AW
Figure by MIT OCW.

2 MOSFET scaling
Straight MOSFET scaling doesn’t work.
• electric field increases

VDD
Ey ↑
L
• power density increases
2
Pdiss f W LCoxVDD 2
∝ = f CoxVDD
device area WL
But
Pdiss
tP ↓↓⇒ f ↑↑⇒ ↑↑⇒ T ↑↑
device area
• total power increases
100
Power (watts)
10
0
1985 1987 1989 1991 1993 1995 1997 1999 2001 2003
Year
INTEL POWER OVER TIME
Figure by MIT OCW.

⇒ must scale VDD

Where is this going?

The future of microelectronics according to Intel:

2 Exciting times ahead in Si IC technology:
• analog electronics (since ∼ 50 s): amplifiers, mixers,

oscillators, DAC, ADC, etc.
• digital electronics (since ∼ 60 s): computers, micro-
controllers, random logic, DSP
• solid-state memory (since ∼ 60 s): dynamic random-
access memory, flash
• energy conversion (since ∼ 70 s): solar cells
• power control (since ∼ 70 s): ”smart” power
• communications (since ∼ 80 s): VHF, UHF, RF
front ends, modems, fiber-optic systems
• sensing, imaging (since ∼ 80 s): photodetectors, CCD
cameras, CMOS cameras, many kinds of sensors
• micro-electro-mechanical systems (since ∼ 90 s): ac-
celerometers, movable mirror displays
• biochip (from ∼ 2000): DNA sequencing, µfluidics
• vacuum microelectronics (from ∼ 2000?): field-emitter

displays
• ??????? (microreactors, microturbines, etc.)
2 Circuit design lessons from 6.012:
1. Importance of optimum level of abstraction:
• device physics equations, i.e.:

W
ID = µCox (VGS − VT )2 , etc.
2L
• device equivalent circuit models, i.e.:
Cgd id
G D
+
vgs Cgs Cgb gmvgs gmbvbs ro

-
S
-
vbs Csb
+
B
Cdb
• device SPICE models, i.e.:
drain
ID − qBD+
RD
+ qGD−
D′
− − vBD′ +
IS
vGD′
gate IDS(VGS,VDS,VBS) bulk
+
+ qGS−
IS
S′ − vBS' +
+ qGB− RS
− qBS+
source
2. Many considerations in circuit design:
• multiple performance specs:

– in analog systems: gain, bandwidth, power con-
sumption, swing, noise, etc.
– in digital systems: propagation delay, power, ease
of logic synthesis, noise, etc.
• need to be immune to temperature variations and de-
vice parameter variations (i.e.: differential amplifier)
• must choose suitable technology: CMOS, BJT, CBJT,
BiCMOS, etc.
• must avoid costly components (i.e.: resistors, capac-
itors)
3. Trade-offs:
• gain-bandwidth trade-off in amplifiers (i.e.: Miller ef-

fect)
• performance-power trade-off (i.e.: delay in logic cir-
cuits, gain in amplifiers)
• performance-cost trade-off (cost=design complexity,
Si area, more aggressive technology)
• accuracy-complexity trade-off in modeling
2 Exciting times ahead in circuit design too:
• Numbers of transistors available outstrips ability to

design by 3 to 1!
• Operational frequency of logic, analog, and communi-
cations circuits increasing very fast.
• Operational voltage shrinking quickly.
• New device technologies: GaAs HEMT, InP HBT,

GaN HEMT, etc
More subjects in microelectronics at MIT
• 6.152J - Micro/Nano Processing Technology. The-

ory and practice of IC technology. Carried out in
clean rooms of Microsystems Technology Laborato-
ries. Fulfills Institute or EECS Lab requirement. Fall
and Spring.
• 6.301 - Solid-State Circuits. Analog circuit design.
Design project. Spring. G-level.
• 6.334 - Power Electronics. Power electronics devices
and circuits. Spring. H-level.
• 6.374 - Analysis and Design of Digital Integrated
Circuits. Digital circuit design. Design projects. Fall.
H-level.
• 6.720J - Integrated Microelectronic Devices. Mi-
croelectronic device physics and design. Emphasis on
MOSFET. Design project. Fall. H-level.

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6.

012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 2-1

Lecture 2 - Semiconductor Physics (I)

September 13, 2005

1. Silicon bond model: electrons and holes

Howe and Sodini, Ch. 2, §§2.1-2.3

• How do semiconductors conduct electricity?

1. Silicon bond model: electrons and holes

Si is in Column IV of periodic table:

IIIA IVA VA VIA

Electronic structure of Si atom:

• GaAs, InP, InGaAs, InGaAsP, ZnSe, CdTe

(on average, 4 valence electrons per atom)

6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 2-4

Silicon crystal structure:

3sp tetrahedral bond

• Silicon is a crystalline material:

Simple ”ﬂattened” model of Si crystal:

4 valence electrons (– 4 q),

contributed by each ion

two electrons in bond

• all bonds satisﬁed → all valence electrons engaged in

6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 2-6

incomplete bond (mobile hole)

• ﬁnite thermal energy

”Free” electrons and holes are called carriers:

• mobile charged particles

Beware: picture is misleading!

• electrons and holes in semiconductors are ”fuzzier”:

• in 6.012, ”electron” means free electron

• not concerned with bonding electrons or core electrons

n ≡ (free) electron concentration [cm−3 ]

p ≡ hole concentration [cm−3 ]

2. Generation and Recombination

Generation = break up of covalent bond to form elec-

• requires energy from thermal or optical sources (or

other external sources)

Recombination = formation of bond by bringing to-

• releases energy in thermal or optical form

• recombination rate: R [cm−3 · s−1 ]

• a recombination event requires 1 electron + 1 hole ⇒

Generation and recombination most likely at surfaces where

• Generation rate in thermal equilibrium: Go = f (T )

• Recombination rate in thermal equilibrium: Ro ∝ no ·po

In thermal equilibrium and for a given semiconduc-

Electron-hole formation can be seen as chemical reaction:

similar to water decomposition reaction:

Law-of-mass action relates concentration of reactants

[H2O] [H +], [OH − ]

Question: In a perfectly pure semiconductor in thermal

Since when a bond breaks, an electron and a hole are

ni ≡ intrinsic carrier concentration [cm−3 ]

ni very strong function of temperature: T ↑ → ni ↑

Note: an intrinsic semiconductor need not be perfectly

5. Doping: introduction of foreign atoms to engineer

A. Donors: introduce electrons to the semiconductor

• For Si, group-V atoms with 5 valence electrons (As,

IIIA IVA VA VIA

• 4 electrons of donor atom participate in bonding

• 5th electron easy to release

immobile ionized donor

• If Nd ni, doping irrelevant

• If Nd ni, doping controls carrier concentrations

In general: Nd ∼ 1015 − 1020 cm−3