DEPARTMENT OF ELECTRONICS ENGINEERING

COLLEGE OF ENGINEERING AND ARCHITECTURE

HOLY ANGEL UNIVERSITY – ANGELES CITY

LABORATORY MANUAL FOR ECKTSAD

DATA AND RESULTS

Table 2.1 Resistance Reading of N-channel JFET Terminals

V1 = 𝑽𝒅𝒔
0 0.5 1 2 3 4 5 6 8
const 𝑽
V1 = -4V 𝑰𝒅𝒓𝒂𝒊𝒏 2.524 2.525 2.525 2.526 2.527 2.528 2.529 2.53 2.532
R4 = nA nA nA nA nA nA nA nA nA
1kΩ 𝒎𝑨
V1 = -3V 𝑰𝒅𝒓𝒂𝒊𝒏 2.523 2.524 2.524 2.525 2.526 2.527 2.528 2.529 2.531
R4 = nA nA nA nA nA nA nA nA nA
470Ω 𝒎𝑨
V1 = -2V 𝑰𝒅𝒓𝒂𝒊𝒏 2.522 2.523 2.523 2.524 2.525 2.526 2.527 2.528 2.53
R4 = nA nA nA nA nA nA nA nA nA
100Ω 𝒎𝑨

𝐼𝑑𝑟𝑎𝑖𝑛
𝑚𝐴

0 2 4 6 8 1 0

Figure 2.2 Output Characteristic Curve of FET

Experiment 2 – Output Characteristics of JFETS Page | 8

 DEPARTMENT OF ELECTRONICS ENGINEERING
COLLEGE OF ENGINEERING AND ARCHITECTURE
HOLY ANGEL UNIVERSITY – ANGELES CITY

LABORATORY MANUAL FOR ECKTSAD

REVIEW QUESTIONS

1. A JFET always operates with the gate-to-source pn junction Reversed Biased.

2. When gate-to-source voltage is 0 volt, the drain current becomes constant when
drain-to-source voltage exceeds in the constant-current region increases when the
gate-to-source bias voltage decreases.
3. The constant-current area of an FET lies between Pinch off and Breakdown.
4. IDSS for JFET is the maximum possible current with VGS held at 0v possible drain
current.
5. The channel of a JFET is between the Drain and Source.

DISCUSSION

In this experiment, we operated the JFET with a strategy. When testing a

JFET, a good strategy to follow is to insert the transistor pins into anti -
static foam (the material used to ship and store electronic components that
are static-sensitive) just before testing. When it is inserted, the conductivity
of the foam will make a resistive connection between all terminals of the
transistor. This connection will ensure the neutralization of all residual
voltage built up across the gate -channel PN junction, thus "opening up" the
channel for an accurate source -to-drain continuity mete r test. Because a
single, uninterrupted piece of semiconductor material is the JFET channel,
there is usually no distinction between the source and the drain terminals.
A resistance check from source to drain should produce the same value as
a drain-to-source check. When the gate -source PN junction voltage is zero,
this resistance should be relatively low (a few hundred ohms at most).
Pinch-off of the channel should be evident by an increased resistance
reading on the meter by applying a reverse -bias voltage between gate and
source.

Experiment 2 – Output Characteristics of JFETS Page | 9

 DEPARTMENT OF ELECTRONICS ENGINEERING
COLLEGE OF ENGINEERING AND ARCHITECTURE
HOLY ANGEL UNIVERSITY – ANGELES CITY

LABORATORY MANUAL FOR ECKTSAD

Circuit Diagram

For V1=-4V, R4=1kΩ

Experiment 2 – Output Characteristics of JFETS Page | 10

 DEPARTMENT OF ELECTRONICS ENGINEERING
COLLEGE OF ENGINEERING AND ARCHITECTURE
HOLY ANGEL UNIVERSITY – ANGELES CITY

LABORATORY MANUAL FOR ECKTSAD

For V1=-3V, R4=470Ω

For V1=-2V, R4=100Ω

Experiment 2 – Output Characteristics of JFETS Page | 11