EE1D21: Digital Systems B

BSc. EE, 1st year, 2020-2021, 2nd VHDL lecture

Arjan van Genderen, Stephan Wong, Computer Engineering

2021-02-11

Delft
University of
Technology

Challenge the future

Summary of previous lecture
• What is VHDL? What is it used for?
• Difference sequential vs. concurrent
• Basic VHDL concepts:
• Entity and architecture
• bit vs. std_(u)logic
• Structural description
• Testbench
• Simple, conditional, and selected signal assignment statements
• Delay models (inertial, transport, and delta)

EE1D21 – Digital Systems (VHDL) 2

 A short visual reminder
What happens when signal ‘a’
changes?

This will lead to:

1. The inputs of the ‘exor’-gate
and the ‘and’-gate change at
the same time.
= waveform 2. If both gates have the same
concurrency = delay, then the outputs will
also change at the same
entity half_adder is time.
port( a, b: in bit; sum, carry: out bit);
end half_Adder; - Entity? Ports?
- Architecture?
architecture my_ha_arch of Half_Adder is - Signals?
begin - Values?
carry <= a and b after 5 ns; - Events?
sum <= a xor b after 5 ns; - Propagation delays?
end my_ha_arch; - Waveform?
- Behavioral or Structural?

EE1D21 – Digital Systems (VHDL) 3

Today’s Topics
• Discrete Event Simulator
• Modeling of complex behavior à process
• Simple “programming”-constructs
• Variables vs. signals
• Wait statements
• State machine in VHDL (an example)
• Hierarchy of components
• Generics
• Configurations

EE1D21 – Digital Systems (VHDL) 4

Delay Models
• Inertial delay
• Standard model
• Suitable for modeling delays of gates
• Transport delay
• Models (small) delays in wires
• All inputs are assigned to the output
• Delta delay
• What if there is no propagation delay?
• An infinitely small delay is added by the simulator to ensure the
correct order of events

EE1D21 – Digital Systems (VHDL) 5

 Pulse Width (of gate input) Slide added in 2019-2020

• Simple example: NOT gate

output <=
not input after 10 ns;
equivalent

output <=
reject 10 ns
This is more flexible, but not
inertial not input
used often! after 10 ns;

EE1D21 – Digital Systems (VHDL) 6

Transport Delay Model

EE1D21 – Digital Systems (VHDL) 7

Delta Delays: example

EE1D21 – Digital Systems (VHDL) 8

Delta Delays: example

EE1D21 – Digital Systems (VHDL) 9

 Discrete Event Simulator: Introduction
• What are signals?
Signals are time-value pairs!
(each pair is called an event)

• What are events?

Events are changes in the value of signals at a
certain time.

• How are new events generated?

When a signal from the RHS of an signal
= waveform assignment statement changes (events).

• How does such a new event look like?

“signal X gets a new value Y on time Z”
entity half_adder is
port( a, b: in bit; sum, carry: out bit); • What do we do with all these events?
end half_Adder; Save them in an event list.

architecture my_half_adder_arch of Half_Adder is • How does the simulator deal with all events? In
begin other words: how is the concurrency intertwined in
carry <= a and b after 5 ns; the discrete event simulator?
sum <= a xor b after 5 ns; By ordering the event list and executing
end my_half_adder_arch; subsequent SIMULTANEOUS events concurrently.

EE1D21 – Digital Systems (VHDL) 10

 Discrete Event Simulator: Example Slide adapted in 2020-2021

2ns
Assumptions:
5ns • All signals are
initialized to ‘0’
5ns • In1 and In2
remain stable
5ns after change
2ns
Time 0 ns: Time 2 ns: Time 5 ns: Time 10 ns:
- In1 (1, 0ns) - s1 (0, 2ns) - s4 (1, 5ns) - z (0, 10ns)
- In2 (1, 0ns) - s2 (0, 2ns) - s3 (1, 5ns)
- s4 (1, 5ns) What to do now?
- s3 (1, 5ns) Stop
- s1 (0, 2ns)
- s2 (0, 2ns) Where is the precision of
- s4 (1, 5ns) - s3 (1, 7ns) the model?
- s3 (1, 5ns) - s4 (1, 7ns) - z (0, 10ns) Ex. in time steps and detail

EE1D21 – Digital Systems (VHDL) 12

Model complex behavior in VHDL
• Concurrent signal assignment statements are used to specify
digital systems at the gate-level.
• At higher level, digital components have more complex behavior:
• Input/output behavior that is difficult to translate to concurrent signal
assignments
• Models that make use of states
• Utilize more complex data structures
• Hence: more powerful contructs within VHDL needed

EE1D21 – Digital Systems (VHDL) 13

The “process” statement
library IEEE;
use IEEE.std_logic_1164.all;

entity mux is
port ( In0,In1,In2,In3: in std_logic_vector(7 downto 0);
Sel: in std_logic_vector(1 downto 0);
Z: out std_logic_vector(7 downto 0)); Sensitivity list
end mux;
Process starts execution from
architecture behavioral of mux is ‘begin’ to’ end’ when a signal in
begin the sensitivity lists changes!
process (Sel,In0,In1,In2,In3) is -- sensitivity list
-- declarative region of process
variable Zout : std_logic_vector(7 downto 0); -- variable instantiation, no time
component
begin
-- process body
if (Sel = “00”) then Zout := In0; -- variable assignment
elsif (Sel = “01”) then Zout := In1;
elsif (Sel = “10”) then Zout := In2;
elsif (Sel = “11”) then Zout := In3;
else Zout := In3;
Keyword “is” introduced in ’93 standard and is optional!
Z <= Zout;
end if;
end process;
end behavioral;

EE1D21 – Digital Systems (VHDL) 14

The “process” construct
• Statements inside a process are executed sequentially
• When assigning multiple values to a signal, only the last
assignment is “executed”
• The signal assignment statements are called: sequential signal
assignment statements - short intermezzo (next slide)
• A process is executed concurrently with other concurrent signal
assignment statements
• The process body ‘looks’ like C or Pascal:
• Declarations and use of variables
• If-then, if-then-else, case, for, and while constructs
• Body can also contain signal assignment statements
• A process requires 0 simulation time and it can schedule/generate
events in the future
• A process may be viewed as a complex signal assignment
statement

EE1D21 – Digital Systems (VHDL) 15

Short intermezzo Slide added in 2019-2020

• How do you call signal assignments outside a process?

Concurrent signal assignments

• Why are they called concurrent ?

They can be executed independent from

each other and even at the same time,
i.e., concurrently

EE1D21 – Digital Systems (VHDL) 16

 A few programming-constructs
• If-then-else:
if (input = ‘0’) then if (input = ‘0’) then if (input = “00”) then
Zout <= ‘1’; Zout <= ‘1’; Zout <= ‘0’;
end if; else elsif (input = “01”) then
Zout <= ‘0’; Zout <= ‘0’;
end if; elsif (input = “10”) then
Zout <= ‘0’;
else
Zout <= ‘1’;
end if;

• For-loops:
for INDEX in 1 to 32 loop
<loop body>
end loop;

• While-loops:
while j < 32 loop
<loop body> …
j := j + 1;
end loop;

• Case: (see example later)

EE1D21 – Digital Systems (VHDL) 17
 Concurrent processes: Full Adder

• Each component can be modeled by a process

• Processes “execute” in parallel (concurrently)
• Processes “communicate” by means of signals

EE1D21 – Digital Systems (VHDL) 18

Concurrent processes: Full Adder

EE1D21 – Digital Systems (VHDL) 19

Concurrent processes: Half Adder

EE1D21 – Digital Systems (VHDL) 20

Processes: general remarks
• Processes are used to describe the more complex behavior of
systems.
• Each concurrent signal assigment statement can be written as a
process statement (single event).
• Processes can generate multiple events.
• All processes are initiated once at the start of a simulation,
thereafter the “data flow” determines what processes will be
executed.
• Difference between the use of signals and variables.

EE1D21 – Digital Systems (VHDL) 21

 Variables vs. Signals

Assumption à at time t=0, both processes are executed AND the following
signals have the following values:
x=0 (t=0)
y=1 (t=0)
z=1 (t=0)
sig_s1=1 (t=0)
sig_s2=1 (t=0)

à Do res1 and res2 have the same value after the “calculation”?

EE1D21 – Digital Systems (VHDL) 22

 At time t=0:
Variables vs. Signals x=0 (t=0)
y=1 (t=0)
z=1 (t=0)
sig_s1=1 (t=0)
sig_s2=1 (t=0)

EE1D21 – Digital Systems (VHDL) 23

VHDL objects and types: summary
• VHDL supports 4 basic objects: variables, constants, signals, and
file types (1993)
• Variables and constants can only take on several values, where
constants cannot be changed after being defined
• Signals are special (think of real systems):
• They also have a time component (unlike variables) aside from the
values it can have
• The implementation of a signal is a series of time-value pairs!!
• File types will not be covered in this lecture

EE1D21 – Digital Systems (VHDL) 24

 How do I model a D-flipflop?
library IEEE; library IEEE;
use IEEE.std_logic_1164.all; use IEEE.std_logic_1164.all;

entity dff is entity dff is

port ( D, clk : in std_logic; port ( D, clk : in std_logic;
Q, Qbar: out std_logic); Q, Qbar: out std_logic);
end dff; end dff;

architecture behavior1 of dff is architecture behavior1 of dff is

begin begin
output: process (clk) is output: process is
begin begin
if (clk’event and clk=‘1’) then wait until(clk’event and clk=‘1’);
Q <= D; Q <= D;
Qbar <= not(D); Qbar <= not(D);
end if;
end process; end process;
end behavior1; end behavior1;

What are the differences?

EE1D21 – Digital Systems (VHDL) 25
Wait statements
• Wait for time to pass: ex: process (a,b) is
begin
• wait for <time expression>
wait on a;
• Wait on a signal: …
• wait on <signal> wait on b;
end process;
• Wait until “something is true” is:
• Wait until <boolean expression> What to do if b changes?

• Multiple wait statements may be used in a process.

• Explicit control of suspending and resumption of a process
• Makes it possible to represent synchronous and asynchronous events
within a digital system.
• Wait statements and sensitivity lists may never be used together in
the same process!! (Why not?)

EE1D21 – Digital Systems (VHDL) 26

Clock generation with wait statements

EE1D21 – Digital Systems (VHDL) 27

 Modelling of state machines

2 basic components:
• Combinational component: output and “next state” generation
• Sequential component
• Example is a Mealy machine (output depends on previous state and input)

EE1D21 – Digital Systems (VHDL) 28

 Example VHDL code (Mealy)
library IEEE; case state is
use IEEE.std_logic_1164.all; when state0 =>
if x=‘0’ then
entity state_machine is next_state<=state1; z<=‘1’;
port ( reset, clk, x : in std_logic; else
z : out std_logic); next_state<=state0; z<=‘0’;
end state_machine; end if;
when state1 =>
architecture behavior1 of state_machine is if x=‘1’ then
type statetype is (state0, state1); next_state<=state0; z<=‘0’;
signal state, next_state: statetype := state0; else
begin next_state<=state1; z<=‘1’;
end if;
comb_proc: process (state, x) is end case;
begin
-- combinational process description
end process; wait until (clk’event and
clk=‘1’)
seq_proc: process is if (reset=‘1’) then
begin state <= state0;
-- sequential process description else
end process; state <= next_state;
end if;
end behavior1;

EE1D21 – Digital Systems (VHDL) 29

 Example VHDL code (Moore)
library IEEE; case state is
use IEEE.std_logic_1164.all; when state0 =>
z <= ‘0’;
entity state_machine is if x=‘0’ then
port ( reset, clk, x : in std_logic; next_state<=state1;
z : out std_logic); else
end state_machine; next_state<=state0;
end if;
architecture behavior1 of state_machine is when state1 =>
type statetype is (state0, state1); z <= ‘1’;
signal state, next_state: statetype := state0; if x=‘1’ then
begin next_state<=state0;
else
comb_proc: process (state, x) is next_state<=state1;
begin end if;
-- combinational process description end case;
end process;
wait until (clk’event and
seq_proc: process is clk=‘1’)
begin if (reset=‘1’) then
-- sequential process description state <= state0;
end process; else
state <= next_state;
end behavior1; end if;

Moore Machines: Output only depends on the state!

EE1D21 – Digital Systems (VHDL) 30
Synchronous vs Asynchronous reset Slide added in 2019-2020

process (clk) is
begin
if (clk’event and clk =‘1’) then
if (reset = '0') then --reset checked only at the rising edge
output <= input;
else
output <= '0';
end if;
end if;
end process;
---------------------------------------------------------------------------------------------------------------------
-- write the VHDL code for the asynchronous reset
process (clk,reset) is
begin
if (reset =‘1’) then
output <= '0';
else
if (clk’event and clk =‘1’) then
output <= input;
end if;
end if;
end process;

EE1D21 – Digital Systems (VHDL) 31

 Hiearchy of components
entity full_adder is
port( a, b, cin: in bit;
Components can be built out of
sum, cout: out bit); smaller componentsà hierarchy
end full_adder;

architecture abc of full_adder is

component half_adder is
port( a, b: in bit; sum,cout: out bit );
end component;
component or_gate is
port( a, b: in bit; z : out; bit );
end component;
signal s1, s2, s3: bit;
begin
FA1: half_adder port map (a=>a,b=>b,sum=>s1,cout=>s3);
FA2: half_adder port map (a=>s1,b=>cin,sum=>sum,cout=>s2);
OR2: or_gate port map (a=>s2,b=>s3,z=>cout);
end abc;

EE1D21 – Digital Systems (VHDL) 32

 Hierarchy and abstraction

• Nested structural description produce hierarchical models

• Hierarchy is “flattened” before simulation is started
• Components on the lowest level must have a functional description
(not structural!)
EE1D21 – Digital Systems (VHDL) 33
Generics

By using generics, one can make parameterized models.

EE1D21 – Digital Systems (VHDL) 34

Generics in Hierarchical models

Precedence rules of generics:

1. The ‘generic map’ value
2. The default defined value
3. The default value of used type

EE1D21 – Digital Systems (VHDL) 35

 Characteristics of generics

• Generics are constant objects that can only be read

• The value of generics must be known during compile-time
• Generics are part of the entities interface, but don’t have a physical
equivalent
• The use of generics is not only limited to “delay” parameters

EE1D21 – Digital Systems (VHDL) 36

A N-input Gate Example

EE1D21 – Digital Systems (VHDL) 37

 Configuration and Binding Rules

Binding Rules:
• What architecture
description to use??
1. Find the entity with the
same name
2. “bind” the last compiled
architecture-description
to that entity
Configurations: • How can we exert more
• An entity can have several different controle on this “binding”
architecture descriptions ?ààà
• The configuration describes what architecture
description to use
EE1D21 – Digital Systems (VHDL) 38
Configuration specification Slide updated in 2019-2020

architecture abc of full_adder is

component half_adder is
port( a, b: in bit; sum,cout: out bit );
end component;
component or_gate is
port( a, b: in bit; z : out bit );
end component;
signal s1, s2, s3: bit; -- here more intermediate signals

library name
| entity name
| | architecture name
for HA1: half_adder use entity WORK.half_adder(behavioral);
for HA2: half_adder use entity WORK.half_adder(structural);
for OR2: or_gate use entity POWER.lpo2(behavioral)
generic map (gate_delay => gate_delay) -- (re-)specifying gate_delay
port map (I1 => a, I2 => b, Z => z); -- remapping the port names
begin
HA1: half_adder port map (a=>a,b=>b,sum=>s1,cout=>s3);
HA2: half_adder port map (a=>s1,b=>cin,sum=>sum,cout=>s2);
OR2: or_gate port map (a=>s2,b=>s3,z=>cout);
end abc;

EE1D21 – Digital Systems (VHDL) 40

Configurations (outside architecture) Slide added in 2019-2020

architecture abc of full_adder is

-- component and signal declarations left out (see previous slide)
begin
HA1: half_adder port map (a=>a,b=>b,sum=>s1,cout=>s3);
HA2: half_adder port map (a=>s1,b=>cin,sum=>sum,cout=>s2);
OR2: or_gate port map (a=>s2,b=>s3,z=>cout);
end abc;

configuration FA_config of full_adder is

for abc -- specify the relevant archictecture (as more can exist)
for HA1: -- for each label, specify the configuration binding
half_adder use entity WORK.half_adder(behavioral);
end for;
for HA2:
half_adder use entity WORK.half_adder(structural);
end for;
for OR2: or_gate use entity POWER.lpo2(behavioral)
generic map (gate_delay => gate_delay)
port map (I1 => a, I2 => b, Z => z);
end for;
end for;
end FA_config;

EE1D21 – Digital Systems (VHDL) 41

More exercises?
• Exam - July 5, 2019 : Q13 & Q14 & Q16

• Exam – July 6, 2018: Q14 & Q15

• Exam – July 31, 2017: Q13 & Q14 & Q16

• Exam – July 7, 2017: Q14 & Q15

• And many more in older exams…

EE1D21 – Digital Systems (VHDL) 42