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Assessment of Isolated and Non-Isolated DC-DC Converters for Medium-

Voltage PV Applications

Conference Paper · May 2017

DOI: 10.1109/IEEEGCC.2017.8448079

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 Assessment of Isolated and Non-Isolated DC-DC
Converters for Medium-Voltage PV Applications
Abdulrahman Alassi1, Member, IEEE. Ayat Al-Aswad, Member, IEEE, Adel Gastli2, Senior Member, IEEE,
Lazhar Ben Brahim3, Senior Member, IEEE, Ahmed Massoud4, Senior Member, IEEE
Department of Electrical Engineering, Qatar University, Doha, Qatar.
1. alassi@qu.edu.qa, 2. adel.gastli@qu.edu.qa, 3. brahim@qu.edu.qa, 4. ahmed.massoud@qu.edu.qa
Abstract— The potential of Photovoltaic (PV) panels as a main
tool of harnessing solar energy is increasing with the
advancements in their power conditioning and conversion stages
that vary based on applications. This paper focuses on the
conversion of a 22kW PV array output from low-voltage to
medium-voltage level (400V to 7kV). This high voltage conversion
ratio is difficult to achieve using conventional single-stage DC-DC
converters. Thus, different alternatives are proposed and
compared here, namely, the Parallel-Input Series-Output (PISO)
connection of two different stages using both isolated (full-bridge)
and non-isolated DC-DC converters. The converters are compared
on the basis of efficiency, footprint, components rating and
reliability. Thus, the isolated DC-DC converter system efficiency
was estimated at 97%, compared to 93% for the non-isolated
system, keeping into account the variations in terms of the filtering
capacitor requirements to maintain a constant minimal voltage
ripple at the output which is in favor of the non-isolated systems.
Keywords— Non-Isolated, Isolated, DC-DC Converters, Full-
Bridge Converter, Zeta Converter, PSIM, MATLAB/Simulink
I. INTRODUCTION
T he renewable energy applications involving the use of
Photovoltaic (PV) panels to capture solar energy are
gaining more interest with time, given the fact that they
can be utilized for different power applications ranging from
residential modules to large PV farms that can supply power in
the MW range [1-4]. Consequently, the use of power electronics
for controlling the PV output and converting its output to
higher/lower levels has grown significantly for different
applications, including the use of DC-DC and DC-AC
converters for grid integration of PV farms [5-6]. Nonetheless,
other existing applications involve converting PV modules’
output to different voltage levels for different purposes such as
charging batteries or feeding islanded loads [7-8]. This paper
specifically targets such applications, where the 400V output
voltage of a 22kW PV array is to be converted into a 7kV output
voltage for supplying DC loads. This conversion can be
achieved through DC-DC converters. However, the focus of
this paper is to study different alternatives in terms of the used
DC-DC conversion system’s efficiency, reliability, size and
cost. Ideally, a single stage boost converter can be utilized to
achieve the required conversion ratio of 17.5. However, the
required extreme duty cycle of 94.3% limits the practicality of
this selection as the parasitic effects would largely deteriorate
its gain at such duty cycle. As a result, different connections
have been proposed in the literature to overcome the problem
of high conversion ratio requirements [1, 9], including the use
of isolated and non-isolated converters. Conventional single-
diode, single-switch non-isolated DC-DC converters were
subject to several design modifications in order to
accommodate the higher gain requirements. For instance,
multilevel boost converters are used to add multi-modular
stages to enhance the converter’s boosting capability by
cascading diodes and capacitors at the output terminals without
achieving extreme duty cycles [10-11]. However, the
dependency on a large number of capacitors is not preferable
since it implies the use of larger filters to overcome the output
current discontinuity and to maintain a regulated output with
minimal ripple contents. On the other hand, cascade connection
of different conventional converter stages add more stresses to
the output converter components, in addition to the failure
propagation through its different stages [9, 12]. Alternatively,
Parallel-Input Series-Output (PISO) connection provides a
powerful tool that suits the given application in terms of
dividing the gain and stresses requirements between two stages,
where the power share of each stage can be controlled through
a proper selection of duty cycles [12]. Fig. 1 shows the PISO
configuration for a general type of converters. Thus, this
topology can be achieved for both isolated and non-isolated
configurations.
As for the non-isolated converters, both stages are connected
to the same common point, and thus it is required for their
outputs to have opposite polarities in order to avoid shorting the
second stage output, while considering the selection of
converters that reduce the overall system requirements (e.g.
input/output filtering capacitors). Consequently, directly using
the same converter for both stages without a polarity reversal
tool prior to the second stage is impractical. Moreover, system
modularity for such medium rating in terms of having the same
converter type for both stages is not vital, and thus directly
selecting two different converters forms a more economical
solution.
Considering the isolated DC-DC conversion that consists of
three stages to convert the voltage from DC to DC either to step
it up or to step it down, which are a DC/AC converter, a High
Frequency (HF) transformer, and an AC/DC converter as shown
in Fig. 2. Using such transformer is important in order to achieve
galvanic isolation, reduce the transformer size, and allow high
current and voltage between the input and the output. Several
works in the area of power electronics proposed different types
of isolated DC-DC converters. A switching technique was
proposed in order to operate at low duty cycle and reduce the
1
 Converter 1
overall efficiency. Additionally, both systems are compared in
+ terms of the number of used components, with their
VDC Stage 1 corresponding ratings and sizes.
+ In terms of the selected switching devices, PW55N80C3
-
MOSFETs are chosen, rated at 850 V and 56 A, and on-state
VDC resistance of 85 mΩ. Although the voltage stress level across the
Converter 2 semiconductor devices for non-isolated conventional converters
- is at least rated for the output voltage (3.5 kV), lower voltage
Stage 2 MOSFETs are chosen for both isolated and non-isolated
solutions in order to have a clear comparison in terms of the
overall voltage stress per stage for both configurations. As for
Fig.1. PISO DC-DC Converter General Block Diagram the diodes, High-Voltage (HV) ABB 5SLD 0600J650100 diodes
are used for both systems with an on-state resistance of
approximately 10 mΩ. Consequently, a safety margin of 100%
is assumed for each component rating.
As for the efficiency evaluation of the non-isolated system
(D2 and Zeta converters shown in Figs 3 and 4, respectively), it
requires the modelling of its parasitic losses that have a
significant effect on the gain deterioration at high duty cycles.
In order to derive the adjusted output/input transfer relation,
state space representation is utilized for both on and off states,
with inductor currents and capacitor voltages considered as the
Fig. 2. Isolated DC-DC convertor concept
fourth order system states that are written as:
voltage stress on the switch, which results in minimizing the
𝑖1𝑜𝑛
̇ 𝐴11 𝐴12 𝐴13 𝐴14 𝑖1𝑜𝑛 𝐵1
switching losses [13]. However, this technique, in medium
𝑖2𝑜𝑛 ̇ 𝐴 𝐴22 𝐴23 𝐴24 𝑖2𝑜𝑛 𝐵2
power application, affects the rating of the switch and increases [ ]= [ 21 ][ ] + [ ] 𝑣𝑠 (1.a)
𝑣𝐶1𝑜𝑛 ̇ 𝐴31 𝐴32 𝐴33 𝐴34 𝑣𝐶1𝑜𝑛 𝐵3
the system size and cost. In addition, the configuration layout
𝑣𝐶2𝑜𝑛 ̇ 𝐴41 𝐴42 𝐴43 𝐴44 𝑣𝐶2𝑜𝑛 𝐵4
makes it complex to parallel the input and series the output,
which is one of the paper aims to divide the stresses on different 𝑖1
stages. A half-bridge DC-DC converter is another proposed 𝑖2
𝑣𝑜 = [𝐶1 𝐶2 𝐶3 𝐶4 ] [ ] (1.b)
technique that has been used to reduce the switches’ voltage 𝑣𝐶1
stress using two switches instead of one, and placing them on 𝑣𝐶2
the input side of the isolated converter [14]. However, the rating The obtained system matrices for cases when the switch is on
of the switches is still high for medium power applications and and off are combined through the state-space averaging method
it increases the voltage stress resulting in higher losses. On the [18,19] as shown in (2):
other hand, a Full-Bridge (FB) converter allows for a higher
switching frequency with reduced voltage stress per switch, as
well as its ease of control, making it more suitable for this 𝑋𝑎𝑣𝑔 = 𝑑𝑋𝑜𝑛 + (1 − 𝑑)𝑋𝑜𝑓𝑓 (2)
application [15]. Where 𝑋 represents the state of interest, and d represents the
In this paper, the non-isolated PISO configuration employs duty cycle. Whereas the system non-idealities taken into
Zeta converter and D2 converter introduced in [16-17]. Those account are:
two converters are employed due to the smooth energy transfer
and the continuous output current capability. 𝑟𝐿 → 𝑖𝑛𝑑𝑢𝑐𝑡𝑜𝑟 ′ 𝑠𝑅 𝑟𝐶 → 𝑐𝑎𝑝𝑎𝑐𝑖𝑡𝑜𝑟 ′ 𝑠 𝐸𝑆𝑅
The isolated PISO configuration, on the other hand, employs FB 𝑟𝑆 → 𝑀𝑂𝑆𝐹𝐸𝑇′𝑠 𝑅𝑂𝑛 𝑟𝐷 → 𝐷𝑖𝑜𝑑𝑒′𝑠 𝑅𝑂𝑛
converter due to the aforementioned points. Finally, the main
contributions of this work can be summarized as follows: On the other hand, the FB isolated DC-DC converter,
 Proposing isolated and non-isolated high gain composed of two levels, is evaluated by assessing its individual
converters based on PISO configuration. stages efficiency from the input to the output side. That is, the
 Detailed modelling of Zeta and D2 non-isolated DC-DC efficiency of its bridge inverters is first estimated by calculating
converters. MOSFETs conduction losses, whereas switching losses are
 Comparing PISO FB isolated and PISO (Zeta and D2) assumed minimum through utilizing the appropriate soft-
non-isolated DC-DC converter systems in terms of switching circuits. After that, the transformer stage efficiency is
efficiency, performance and requirements for a medium- estimated, where the inverter output power is taken as its input.
voltage application range. Consequently, the main transformer losses: primary copper loss,
secondary copper loss, and core losses are estimated from [20]
II. METHODOLOGY since the system ratings are chosen to accommodate its given
The assessment methodology for both isolated and non- model as will be thoroughly discussed later. Finally, the
isolated topologies is clarified here, where the first step is to efficiency of the rectifier stage is estimated similar to the inverter
model each system non-idealities and to find its corresponding stage, and the output power can be obtained, leading to the

2
overall system efficiency estimation. In other words, the 𝑟𝐶2
𝐶𝑜𝐹𝐹 = [0 𝑅𝑃 0 1− ] (4.c)
efficiency of a single stage can be projected on both stages since 𝑟𝐶2 + 𝑅
they are assumed to share the same operating conditions and The output capacitor polarity given in Figs. 6 and 7 is
components. negative, thus the overall transfer relation is multiplied by a
negative sign to account for that. Correspondingly, the results
III. NON-ISOLATED DC-DC CONVERTERS from (3) and (4) can then be combined using (2) to obtain the
The two selected single-diode, single switch converters to averaged state-space representation, which can eventually be
compose the PISO system were Zeta and D2 as introduced used to obtain the non-ideal system response represented in (5).
earlier, where both of them inherently have opposite output The output capacitor polarity given in Figs. 6 and 7 is negative,
polarities with continuous output current (HV side of the thus the overall transfer relation is multiplied by a negative sign
converter in step-up applications), which helps reducing the to account for that. Correspondingly, the results from (3) and (4)
required filtering capacitors to ensure minimum current ripple. can then be combined using (2) to obtain the averaged state-
On the other hand, the input filter size is also reduced due to the space representation, which can eventually be used to obtain the
input current continuity of the D2 converter as well [17]. non-ideal system response represented in (5).
Additionally, the coupling capacitors provided in these fourth
𝑉𝑜 𝑅(𝐷 − 𝐷 2 )
order converters contribute to a smoother unidirectional power ( ) = (5.a)
flow, and although their ratings are slightly higher than the HV 𝑉𝑠 𝐷 𝛽1 𝐷 2 + 𝛽2 𝐷 + 𝛽3
2
side voltage, higher ripple content can be tolerated across them
to reduce the capacitor banks size and cost. Where:
𝛽1 = 𝑅 + 𝑟𝐿2 − 𝑟𝐶1 (5.b)
A. Modelling of D2 Converter 𝛽2 = 𝑟𝑠 − 𝑟𝑑 + 𝑟𝐶1 − 2𝑟𝐿2 − 2𝑅 (5.c)
The converter was modeled for both on and off states, where
basic circuit analysis tools were used to obtain the state space 𝛽3 = 𝑅 + 𝑟𝑑 + 𝑟𝐿1 +𝑟𝐿2 (5.d)
equations for each corresponding condition based on the given
operating conditions and non-idealities. Figs. 6 and 7 show the B. Modelling of Zeta Converter
non-ideal circuits for both on and off states, respectively, with The same steps were repeated for the Zeta converter, in terms
the assumed inductor current directions and capacitor voltage of obtaining the mathematical representation for the on and off
polarities. Equation (3) shows the mathematical expression of states equivalent circuits. Equations (6) and (7) represent the
the system dynamics when the MOSFET is switched on. system dynamic response for both cases, respectively.
−(𝑟𝑆 + 𝑟𝐿1 ) 𝑟𝐶1 1 −(𝑟𝑆 + 𝑟𝐿1 ) 𝑟𝑠 1
− − 0 − − 0
𝐿1 𝐿1 𝐿1 𝐿1 𝐿1 𝐿1
𝑟𝐶1 −(𝑟𝐶1 + 𝑟𝐿2 + 𝑅𝑃 ) −1 ((𝑅𝑝 /𝑅) − 1) 𝑟𝑠 −𝛽4 −1 ((𝑅𝑝 /𝑅) − 1)
− −
𝐿2 𝐿2 𝐿2 𝐿2 𝐿2 𝐿2 𝐿2 𝐿2
𝐴𝑂𝑁 = (3.a) 𝐴𝑂𝑁 =
1 1 1 (6.a)
0 0 0 0 0
𝐶1 𝐶1
𝐶1
𝑅𝑃 −1
0 0 𝑅𝑃 −1
[ 𝑟𝐶2 𝐶2 𝐶2 (𝑅 + 𝑟𝐶2 ) ] 0 0
[ 𝑟𝐶2 𝐶2 𝐶2 (𝑅 + 𝑟𝐶2 ) ]
1 1
𝐵𝑂𝑁 = [ 0 0]𝑇 (3.b) 1 1
𝐿1 𝐿2 𝐵𝑂𝑁 = [ 0 0]𝑇 (6.b)
𝐿1 𝐿2
𝑟𝐶2
𝐶𝑜𝑛 = [0 𝑅𝑃 0 1− ] (3.c)
𝑟𝐶2 + 𝑅
L2
Where, 𝑅𝑃 is equivalent to the parallel combination of the C1 D
load resistance R and the output filter capacitor ESR, namely -
𝑟𝐶2 . Consequently, the system response is altered when the Vs S C2 R Vo
MOSFET is switched off, where instead, the diode becomes L1 +
forward biased and the system dynamic behavior is represented
differently as in (4).

−(𝑟𝐿1 + 𝑟𝐶1 + 𝑟𝐷 ) Fig. 3. D2 Converter Topology

0 0 0 L2
𝐿1
−(𝑟𝐶1 + 𝑟𝐿2 + 𝑅𝑃 ) −1 (𝑅𝑝 /𝑅) − 1
0
𝐿2 𝐿2 𝐿2 S C1
𝐴𝑂𝐹𝐹 = (4.a)
1
0 0 0 +
𝐶1
𝑅𝑃 −1 Vs C2 R Vo
0 0
L1 D
[ 𝑟𝐶2 𝐶2 𝐶2 (𝑅 + 𝑟𝐶2 )] -
1 1
𝐵𝑂𝐹𝐹 = [ 0 0]𝑇 (4.b)
𝐿1 𝐿2

Fig. 4. Zeta Converter Topology

3
 rC1 + C1 - rL2 L2 Finally, (5) and (8) will form the basis for the upcoming
analysis for the combined PISO converter.
rs I2
rC2 C. Combined Topology
I1 Both Zeta and D2 converters were combined in a PISO
Vs + R
rL1 C2 connection in order to achieve the required step-up ratio by the
- given application (i.e. a total gain of 17.5 to step up the 400V
L1 PV output to 7kV). In other word, the individual gain
contribution for each of the converters is reduced to 8.75, with a
duty cycle of 89.7% for both MOSFETs. Fig. 8 shows the
Fig. 6. On-State equivalent circuit of the D2 converter connected converters with the specified arrangement.
The overall system gain is equal to the summation of
rC1 + C1 - rL2 L2 individual stages gain. Consequently, the system efficiency can
be approximated as in (9) [12].
rD I2 𝐺1 + 𝐺2
𝜂= (9)
I1 rC2 2𝐺𝑖𝑑𝑒𝑎𝑙
+ R
Vs rL1 Where 𝐺𝑖𝑑𝑒𝑎𝑙 represents the ideal gain of an individual
C2 converter, assuming that both stages are operating at the same
- duty cycle with the same gain requirements and ideal transfer
L1
characteristics (i.e. buck-boost type). The non-idealities
presented in the previous subsections have to be represented
Fig. 7. Off-State equivalent circuit of the D2 converter using logical assumptions that mimics real-life scenarios. That
is, MOSFETs and diodes on-state resistance ohmic values are
𝑟𝐶2 obtained from the components datasheets, where they are
𝐶𝑜𝑛 = [0 𝑅𝑃 0 1− ] (6.c)
𝑟𝐶2 + 𝑅 combined in series and parallel when needed if individual ratings
Where: are insufficient to cover the given application ratings. In this
𝛽4 = 𝑟𝐶1 + 𝑟𝐿2 + 𝑟𝑆 + 𝑅𝑃 case, 10 MOSFETs are connected as a switching valve per stage
(6.d) to withstand the rated voltage as explained earlier.
On the other hand, inductors winding resistance 𝑟𝐿 and
On the other hand, off-state system is represented similarly capacitors ESR are estimated on per-unit basis based on the
when the MOSFET is no longer triggered and the diode is individual component’s rated current and voltage. That is, input
forward biased in the following manner: inductors are rated for higher RMS currents, and thus lower
inductance values are required to maintain current continuity
−(𝑟𝐿1 + 𝑟𝐶1 + 𝑟𝐷 )
within the required current ripples regulations, indicating the use
0 0 0 of thick and short wires to achieve the required millihenries.
𝐿1
−(𝑟𝐷 + 𝑟𝐿2 + 𝑅𝑃 ) −1 (𝑅𝑝 /𝑅) − 1 Correspondingly, lower resistances are achieved for the input
0 side inductors. In contrast to the output inductors.
𝐿2 𝐿2 𝐿2
𝐴𝑂𝐹𝐹 = (7.a)
1 As for the capacitors, similar per unit ESRs are assumed for
− 0 0 0
𝐶1 coupling and output filters, although the voltage rating of the
𝑅𝑃 −1 coupling capacitor is higher, nonetheless, higher voltage ripples
0 0
[ 𝑟𝐶2 𝐶2 𝐶2 (𝑅 + 𝑟𝐶2 )] are tolerated across it as discussed earlier. Fig. 9 demonstrates
𝐵𝑂𝐹𝐹 = [0 0 0 0]𝑇 (7.b) the discussed tradeoffs for both inductors and capacitors.
𝑟𝐶2 Consequently, the assumed per-unit values with respect to
𝐶𝑜𝐹𝐹 = [0 𝑅𝑃 0 1− ] (7.c) the load resistor for each conversion stage are listed here, where
𝑟𝐶2 + 𝑅
the equivalent load resistance of the 22-kW system is 2.227 kΩ,
or 1.113 kΩ per-stage. The latter value is used as a base value
Likewise, the D2 converter model, an equivalent model can
for the calculation of per-unit parasitic resistances in Table I.
be obtained through state space averaged equation manipulation
Taking the aforementioned considerations into account, the
in order to obtain the output/input adjusted relation, shown in
theoretical efficiency calculated using (9) was found to be 93%,
(8).
which is found to be in an excellent agreement with the
𝑉𝑜 𝑅(𝐷 − 𝐷2 ) simulation result using PSIM that gave an output of 6.5 kV using
( ) = (8.a) the given parasitic resistances, which translates to the same
𝑉𝑠 𝑍𝑒𝑡𝑎 𝛽5 𝐷2 + 𝛽2 𝐷 + 𝛽6
conversion efficiency.
Where: TABLE I
Summary of the assumed 𝑟𝑝𝑢 for L & C
𝛽5 = 𝑅 + 𝑟𝐿1 + 𝑟𝐿2 − 𝑟𝐶1 (8.b)
Component 𝑳𝟏 , 𝑳𝟑 , 𝑪𝟏 , 𝑪𝟐 , 𝑪𝟑 , 𝑪𝟒 𝑳𝟐 , 𝑳𝟒
𝛽6 = 𝑅 + 𝑟𝑑 + 𝑟𝐿1 (8.c) 𝑟𝑝𝑢 0.0001 0.0005

4
 Zeta Converter
C1 L2

+ S1
Vs L1 G = 8.75 D1 C2
-
+
Vo
L3 -
S2 G = 8.75 C4

C3 D 2 L4
Fig. 10. Isolated FB DC-DC conversion topology
D2 Converter
Fig. 8. Zeta and D2 PISO Combined Topology

Higher Current, Lower L

Lower Current, Higher L
Ii
Higher C
Higher V
Lower C Li
Io

Fig. 11. On-State equivalent circuit of the isolated DC-DC

Lo
Fig. 9. L and C requirements for different ratings
IV. ISOLATED DC-DC CONVERTERS
The selected isolated DC-DC converter is a FB
unidirectional converter. Fig. 10 presents the isolated PISO
converter. The FB converter non-idealities were modelled as the
on-state losses for both switches and diodes, in addition to the
HF transformer model from the literature. Each switch is
assumed to be operational for 50% of each cycle, neglecting the
small dead-bands in between. The efficiency of each stage is
then approximated based on the given operating conditions and
circuit parameters (𝑉𝑖 = 400 𝑉, 𝑉𝑜 = 7 𝑘𝑉, 𝑓𝑠 = 30 𝐾𝐻𝑧, 𝑃 =
22 𝐾𝑤). The following calculations are made for one of the two
FBs composing the PISO converter as both stages are assumed
operationally identical and thus share the same efficiency with
the whole system.
The first stage of the FB is the inverter, where the same
MOSFETs are used as before. Consequently, switching losses
are also omitted based on the assumption of soft-switching
techniques utilization. The input current per-stage is 27.5 A.
Thus, its conduction losses are estimated as shown in (10).
1 2
𝑃𝑐𝑜𝑛𝑑 = 2(𝐼𝑖𝑛 ) (𝑟𝑠 ) = 130 𝑊
Now, the input power to the high frequency transformers, per
stage, after deducting the switches conducting losses can be
estimated as in (11).
′ 𝑃𝑖𝑛
𝑃𝑖,𝑡𝑟𝑎 = 𝑃𝑖𝑛 − 𝑃𝑐𝑜𝑛𝑑 = 10.87 𝑘𝑊
As for the transformer losses, they are divided into the core,
primary, and secondary windings losses, where the latter are
related to the heat dissipated when the current flows through the
winding in which the type of the copper is an important element
converter
in the loss calculation. Core loss, on the other hand, depends on
the flux variation and on the magnetic properties of the material
used for the construction of core. A high frequency transformer
for the given application and rating was introduced and
characterized in [20], where its losses were given as:
 Primary losses: Primary = 63 W, Seconday = 48 W
 Core losses = 96 W
These numbers the power losses of the transformer per stage
loss
as a total Ptra,tot , which is equivalent to 207W. The transformer
efficiency 𝜂 𝑇 can be calculated as in (12), taking into account
that the input power is the one after deducting the losses from
the inverter stage.
loss
𝑃𝑖,𝑡𝑟𝑎 − Ptra,tot
𝜂𝑇 = [ ] × 100% = 98.1% (12)
𝑃𝑖,𝑡𝑟𝑎
The last stage is the rectifier stage in which the diode
resistance is considered during the on state as in Fig. 11. The loss
calculation can be made similarly to the inverter stage, where the
rectifier conduction losses per stage were found to be minimal
(~0.2 W), since the current is significantly stepped down,
(10)
(12) indicating that they can be neglected. To sum up the efficiency
𝜂𝑡𝑜𝑡 of the system as a whole, the output power of the system is
first calculated as 21.33 kW, and thus the efficiency is estimated
as in (13).
𝑃𝑜𝑢𝑡
𝜂𝑡𝑜𝑡 = [ ] × 100 = 96.9% (13)
(11)
A Simulink layout was generated to compare between the
theoretical and simulation efficiencies. By knowing 𝐼𝑜𝑢𝑡 and
𝑉𝑜𝑢𝑡,𝑠𝑖𝑚 , the calculated efficiency was found to be 96.9%, which
is in good agreement with the simulation results.

5
 V. DISCUSSION OF THE RESULTS
The presented results for both non-isolated and isolated
converters showed comparable performance in terms of the
overall system efficiency. The non-isolated system efficiency
was estimated about 93%, whereas the isolated system had a
better efficiency of 96.9%. However, this result is based on the
use of strings of 10 MOSFETs with relatively high on-state
resistance per stage for the non-isolated system for the sake of
comparing the switches stress levels between the two topologies.
Nonetheless, the efficiency is expected to increase if higher-
rating IGBT switches with considerably less on-state resistance
are used instead, given that proper snubbers and soft-switching
circuity are used to minimize the potential switching losses.
On the other hand, isolated converters efficiency’s boost is
mainly due to the well-designed HF transformer. This shows the
potentials of developing such technologies in a highly efficient
manner, which can even be extended in the future to higher
power applications. In terms of systems footprint, the non-
isolated system would utilize more passive components with
higher ratings. However, the significant filtering capacitor
requirements of the isolated DC-DC converter system need to be
taken into account in terms of the connections shown in Fig. 9.
VI. CONCLUSIONS
This paper presented the conversion of a 22kW PV array
output from 400V to 7kV for medium-voltage PV applications.
Due to the large conversion ratio a Parallel-Input Series-Output
(PISO) connection of two different stages using both isolated
(full-bridge) and non-isolated (Zeta & D2) DC-DC converters
were proposed. The converters were compared according to
efficiency, footprint, components rating and reliability. The
isolated DC-DC converter system efficiency was estimated at
96.9%, compared to 93% for the non-isolated system, where the
high-frequency transformer was well developed and had good
efficiency, minimizing the power loss in the isolated system.
Yet, the non-isolated systems with continuous output current are
advantageous in terms of their output filter requirements.
Finally, the selection of a proper system for the given application
has to take into consideration all of the aforementioned points
with the advantages and disadvantages of each topology based
on the given discussion.
ACKNOWLEDGMENT
This publication was made possible by the National
Priority Research Program (NPRP) award [NPRP6-244-2-103]
from the Qatar National Research Fund (QNRF); a member of
the Qatar Foundation. Its contents are solely the responsibility
of the authors and do not necessarily represent the official views
of QNRF.
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