ADDIS ABABA SCIENCE AND TECHNOLOGY UNIVERSITY

Collage of electrical and mechanical engineering

Department of computer engineering
Course name: VLSI

Instructor name: Prof..S.Ramasamy

Prepared by:
Mathewos Budusa………………………………………….0735/08
subtractor

module sub_32_bits(diff,a,b);
input [31:0]a,b;
output [31:0]diff;
assign diff=a-b;
endmodule
/////////////////////////
module test_sub_32_bits;
reg [31:0]a,b;
wire [31:0]diff;
sub_32_bits sub(diff,a,b);
initial #500 $finish;
initial
begin
a=32'd1;
end
initial
repeat(31)
begin
#10;
a=32'b00000000000000000000000000011000;
b=32'b00000000000000000000000000000100;
#10;
a=32'b00000000000000000000000000001111;
b=32'b00000000000000000000000000000111;
#10;
a=32'b00000000000000000000000001011001;
b=32'b00000000000000000000000000000000;
#10;
a=32'b00000000000000000001001000000001;
b=32'b00000000000000000000011000000000;
#10;
a=32'b00000000000000000001010000000001;
b=32'b00000000000000000000010000000000;
end
endmodule
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////

module mux_3to1(a, b, c, sel, out);

input [1:0] sel;
input [31:0]a,b,c;
output [31:0]out;
reg out;
always @(a or b or c or sel)
begin
case (sel)
2'b00: out = a;
2'b01: out = b;
2'b10: out = c;
endcase
end
endmodule
////////////////////////////////////////
module test_mux_3t01;
reg a,b,c;
reg [1:0]sel;
wire out;
mux_3to1 mux3(a,b,c,sel,out);
initial #60 $finish;
initial
begin
{c,b,a}=3'b001;
sel=2'b00;
#20;
{c,b,a}=3'b010;
sel=2'b01;
#20;
{c,b,a}=3'b100;
sel=2'b10;
#20;
{c,b,a}=3'b110;
sel=2'b00;
#20;
{c,b,a}=3'b101;
sel=2'b01;
#20;
{c,b,a}=3'b011;
sel=2'b10;
end
endmodule
/////////////////////////////////////////////////////////////////////////////////
module mux_2to1(a,b,sel,out );
input sel;
input [31:0]a,b;
output [31:0]out;
reg out;
always @(a or b or sel)
begin
case (sel)
1'b0: out = a;
1'b1: out = b;
endcase
end
endmodule
////////////////////////////////////////////////////////
module test_mux_2t01;
reg a,b;
reg sel;
wire out;
mux_2to1 mux2(a,b,sel,out);
initial
begin
{a,b}=2'b10;
sel=1'b0;
#10;
{a,b}=2'b01;
sel=1'b0;
#10;
{a,b}=2'b01;
sel=1'b1;
#10;
{a,b}=2'b10;
sel=1'b1;
end
endmodule
////////////////////////////////////////////////////////////////////
module multiplier_16_bit (product,a,b);
input [15:0]a,b;
output [31:0]product;
assign product=a*b;
endmodule
///////////////////////////////////////////////////////////////
module test_multipLier_16_bit;
reg [15:0]a,b;
wire [31:0]product;
multiplier_16_bit multiply(product,a,b);
initial
#500
$finish;
initial
begin
a=16'd1;
b=16'd0;
end
initial
repeat(31)
begin
#10;b=b+16'd1;
a=a+16'd1;end
endmodule
//////////////////////////////////////////////////////////////////////////////////
module mini_ALU(a,b,sel,out);
input [31:0]a,b;
input [2:0]sel;
output [31:0]out;
assign out=(sel==3'b000)?(a+b):
((sel==3'b001)?(a+1):
(
(sel==3'b010)?(a-b):
((sel==3'b011)?(a-1):
((sel==3'b100)?(a*b):32'd1))));
/*
always @(a or b or sel)
begin
if(sel==3'b000) out=a+b;
//32 bit adder
else if(sel==3'b001) out=a+1;
//increment
else if(sel==3'b010) out=a-b;
//32 bit subtractor
else if(sel==3'b011) out=a-1;
//decrement
else if(sel==3'b100) out=a[15:0]*b[15:0];
//multiplier
else out=32'b00000000000000000000000000000000;
end
endmodul
module mini_ALU(a, b, f, r);
input [31:0] a, b;
input [2:0] f;
output [31:0] r;
wire [31:0] addmux_out, submux_out;
wire [31:0] add_out, sub_out, mul_out;
mux_2to1 adder_mux(b, 32'd1, f[0], addmux_out);
mux_2to1 sub_mux(b, 32'd1, f[0], submux_out);
Adder_32_bit our_adder( a,add_out,addmux_out);
sub_32_bits our_subtracter( a,sub_out,submux_out);
multiplier_16_bit our_multiplier(mul_out,a[15:0], b[15:0]);
mux_3to1 output_mux(add_out, sub_out, mul_out, f[2:1], r);*/
endmodule
///////////////////////////////////////////////
module test_mini_ALU;
reg [31:0]a,b;
reg [2:0]sel;
wire [31:0]out;
mini_ALU alu(a,b,sel,out);
initial
#3000
 $finish;
initial
begin
sel=3'b000;
a=32'd1;
b=32'd0;
end
initial
begin
while(1)
begin
#10;
sel=sel+3'b001;
if(sel>=3'b101)
begin
sel='b000;
end
end
end
initial
repeat(31)
begin
#50;
b=b+32'd1;
a=a+32'b1;
end
endmodule

//////////////////////////////////////////////////////////////////////////////////
module encoder(i, e);
input [3:0] i;
output [1:0] e;
assign e=(i == 4'b0001)?2'b00:((i==4'b0010)?2'b01:
((i == 4'b00100)?2'b10:
((i == 4'b1000)?2'b11:2'bxx)));
/*always @(i)
 begin
if (i == 4'b0001) e = 2'b00;
else if (i == 4'b0010) e = 2'b01;
else if (i == 4'b0100) e = 2'b10;
else if (i == 4'b1000) e = 2'b11;
else e = 2'bxx;
end */
endmodule
//////////////////////////////////////////////////////////////////////////////////
module test_encoder;
reg [3:0]i;
wire [1:0]e;
encoder enc(i,e);
initial
begin
i=4'b0000;
end
initial
begin
#10;
i=4'b0001;
#10;
i=4'b0010;
#10;
i=4'b0100;
#10;
i=4'b1000;
end
endmodule
//////////////////////////////////////////////////////////////////////////////////
module Adder_32_bit(sum,cout,cin,a,b);
input [31:0]a,b;
input cin;
output [31:0]sum;
output cout;
assign {cout,sum}=a+b+cin;
endmodule
/////////////////////////////////////////////////////////////////////////////////
module test_adder_32_bit;
reg [31:0]a,b;
reg cin;
wire [31:0]sum;
wire cout;
Adder_32_bit add(sum,cout,cin,a,b);
initial
#500
$finish;
initial
begin
cin=1'b0;
a=32'd0;
b=32'd1;
end
initial
repeat(31)
begin
#10;
a=a+32'd1;
b=b+32'd1;
end
endmodule