EXPERIMENT NO.

2
AIM:
To Design and simulate half subtractor and full subtractor
circuits using different modeling techniques.

SOFTWARE USED:
Xilinx ISE 14.7

THEORY:

HALF SUBTRACTOR: Half Subtractors are a type of digital circuit that

calculates the arithmetic binary subtraction between two single-bit numbers. It is
a circuit with two inputs and two outputs. For two single-bit binary numbers A
and B, a half subtractor produces two outputs.

FULL SUBTRACTOR: Full subtractor performs subtraction of two bits, one is

minuend and other is subtrahend. In full subtractor '1' is borrowed by the previous
adjacent lower minuend bit. Hence there are three bits are considered at the input
of a full subtractor. There are two outputs, that are DIFFERENCE output D and
BORROW output B.

CIRCUIT DIAGRAM:
Half Subtractor:

Figure 2.1

Boolean Expression:
D=A^B; B0= ~A & B;
Full Subtractor:

Figure 2.2

Boolean Expression:
D=a^b^c; B=((~a)&b) | ((~a)&c) | (b&c);

TRUTH TABLE:
Half Subtractor:
Table 2.1
Full Subtractor:
Table 2.2

APPLICATIONS:
1. The subtractor circuitry is utilized in the ALU implementation of a processor.
2. Carryout Multiplication -the dedicated multiplication circuit uses it to reduce
complexity.
3. For graphics related applications, where there is a very much need of complex
computations, the GPU uses optimized ALU which is made up of full adders.
VERILOG CODE:
Half Subtractor:
1.DATA FLOW
module HS_Dataflow(
input a,
input b,
output difference,
output borrow
);
assign difference=a^b;
assign borrow=(~a)&b;
endmodule
2.GATE LEVEL
module HS_Gate(
input a,
input b,
output difference,
output borrow
);wire w;
xor g1(difference,a,b);
not g2(n,a);
and g3(borrow,w,b);
endmodule

3.BEHAVIOURAL LEVEL
module HS_Behav(
input a,
input b,
output reg difference,
output reg borrow
);
always@(a or b)
case({a,b})
2'b00:begin difference=0;borrow=0;end
2'b01:begin difference=1;borrow=1;end
2'b10:begin difference=1;borrow=0;end
2'b11:begin difference=0;borrow=0;end
endcase
endmodule

Full Subtractor:
1.DATA FLOW
module FS_Dataflow(
input a,
input b,
input c,
output difference,
output borrow
);
assign difference = a^b^c;
assign borrow = ((~a)&b) | ((~a)&c) | (b&c);
endmodule

2.GATE LEVEL
module FS_Gate(
input a,
input b,
input c,
output difference,
output borrow
);wire n,n1,n2,n3;
xor g1(difference,a,b,c);
not g2(n,a);
and g3(n1,n,b);
and g4(n2,n,c);
and g5(n3,c,b);
or g6(borrow,n1,n2,n3);
endmodule

3.BEHAVIOURAL MODELLING
module FS_Behav(
input a,
input b,
input c,
output reg difference,
output reg borrow
);
always@(a or b or c )
case({a,b,c})
3'b000:begin difference=0;borrow= 0;end
3'b001:begin difference=1;borrow= 1;end
3'b010:begin difference=1;borrow= 1;end
3'b011:begin difference=0;borrow= 1;end
3'b100:begin difference=1;borrow= 0;end
3'b101:begin difference=0;borrow= 0;end
3'b110:begin difference=0;borrow= 0;end
3'b111:begin difference=1;borrow= 1;end
endcase
endmodule
TESTBENCH:
Half Subtractor:
a = 0;b = 0;#100;
a = 0;b = 1;#100;
a = 1;b = 0;#100;
a = 1;b = 1;#100;
Full Subtractor:
a = 0;b = 0;c = 0;#100;
a = 0;b = 0;c = 1;#100;
a = 0;b = 1;c = 0;#100;
a = 0;b = 1;c = 1;#100;
a = 1;b = 0;c = 0;#100;
a = 1;b = 0;c = 1;#100;
a = 1;b = 1;c = 0;#100;
a = 1;b = 1;c = 1;#100;

RTL Schematic:
Half Subtractor:
Gate Level Modelling:

Fig 2.3
Data Flow Modelling:

Fig 2.4
Behavioural Modelling:

Fig 2.5
Full Subtractor:
Gate Level Modelling:

Fig 2.6
Data Flow Modelling:

Fig 2.7
Behavioural Modelling:
 Fig 2.8

OUTPUT:
Half Subtractor:

Fig 2.9
Full Subtractor:

Fig 2.10
RESULT:
The half subtractor and full subtractor circuits have been
successfully implemented, simulated and verified using different modelling
techniques.