ADVANCED DIGITAL SYSTEM DESIGN

EXPERIMENT NO. : 7

Design a Sequence Detector which detects a sequence 1001 using MEALY

AIM: and MOORE FSM using VHDL and Verify them by using XILINX Simulator.

The Objective of this experiment is to design sequence detector using Mealy

and Moore circuit for sequence 1001 in Xilinx 14.1 ISE Design suite tool, and to
OBJECTIVE: test the circuit using test bench where outputs are observed for different
inputs.

STATE
DIAGRAM:

VHDL CODE: VHDL code for “1001” using MEALY circuit:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

ENTITY MEALY IS

PORT (X, CLK: IN STD_LOGIC;

Z: OUT STD_LOGIC);

END MEALY;

ARCHITECTURE Behavioral OF MEALY IS

TYPE State IS (A, B, C, D);

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 ADVANCED DIGITAL SYSTEM DESIGN

SIGNAL Y: State;

BEGIN

PROCESS (X, CLK)

BEGIN

IF (CLK = ‘1’ and CLK’EVENT)

THEN

CASE Y IS

WHEN A=> IF (X=’0’)

THEN Y<=A;
Z<= ‘0’;
ELSE Y<=B;
Z<= ‘0’;
END IF;
WHEN B=> IF (X=’0’)
THEN Y<=C;
Z<= ‘0’;
ELSE Y<=B;
Z<= ‘0’;
END IF;
WHEN C=> IF (X=’0’)
THEN Y<=D;
Z<= ‘0’;
ELSE Y<=B;
Z<= ‘0’;
END IF;
WHEN D=> IF (X=’0’)
THEN Y<=A;
Z<= ‘0’;
ELSE Y<=B;

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 ADVANCED DIGITAL SYSTEM DESIGN

Z<= ‘1’;
END IF;
WHEN OTHERS=> NULL;

END CASE;

END IF;

END PROCESS;

END behavioral;

VHDL code for “1001” using MOORE circuit:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

ENTITY MOORE IS

PORT (X, CLK: IN STD_LOGIC;

Z: OUT STD_LOGIC);

END MOORE;

ARCHITECTURE Behavioral OF MOORE IS

TYPE State IS (A, B, C, D, E);

SIGNAL Y: State;

BEGIN

PROCESS (X, CLK)

BEGIN

IF (CLK = ‘1’ and CLK’EVENT)

THEN

CASE Y IS

WHEN A=> IF (X=’0’)

THEN Y<=A;

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 ADVANCED DIGITAL SYSTEM DESIGN

ELSE Y<=B;
END IF;
Z<= ‘0’;
WHEN B=> IF (X=’0’)
THEN Y<=C;
ELSE Y<=B;
END IF;
Z<= ‘0’;
WHEN C=> IF (X=’0’)
THEN Y<=D;
ELSE Y<=B;
END IF;
Z<= ‘0’;
WHEN D=> IF (X=’0’)
THEN Y<=A;
ELSE Y<=E;
END IF;
Z<= ‘0’;
WHEN E=> IF (X=’0’)
THEN Y<=C;
ELSE Y<=B;
END IF;
Z<= ‘1’;
WHEN OTHERS=> NULL;

END CASE;

END IF;

END PROCESS;

END behavioral;

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 ADVANCED DIGITAL SYSTEM DESIGN

TEST BENCH: Test Bench for MEALY circuit:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

ENTITY TEST IS

END TEST;

ARCHITECTURE behavior OF TEST IS

COMPONENT MEALY

PORT (CLK, X: IN STD_LOGIC;

Z: OUT STD_LOGIC);

END COMPONENT;

SIGNAL CLK: STD_LOGIC:= '0';

SIGNAL X: STD_LOGIC:= '0';

SIGNAL Z: STD_LOGIC;

CONSTANT CLK_period: TIMEB := 100 ns;

BEGIN

uut: MEALY PORT MAP (CLK => CLK, X => X, Z => Z);

CLK_process: PROCESS

BEGIN

CLK <= '0';

WAIT FOR CLK_period/2;

CLK <= '1';

WAIT FOR CLK_period/2;

END PROCESS;

stim_proc: PROCESS

BEGIN

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 ADVANCED DIGITAL SYSTEM DESIGN

X<='1';

WAIT FOR 100 NS;

X<='0';

WAIT FOR 100 NS;

X<='0';

WAIT FOR 100 NS;

X<='1';

WAIT FOR 100 NS;

END PROCESS;

END;

Test Bench for MOORE circuit:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

ENTITY TEST IS

END TEST;

ARCHITECTURE behavior OF TEST IS

COMPONENT MOORE

PORT (CLK, X: IN STD_LOGIC;

Z: OUT STD_LOGIC);

END COMPONENT;

SIGNAL CLK: STD_LOGIC:= '0';

SIGNAL X: STD_LOGIC:= '0';

SIGNAL Z: STD_LOGIC;

CONSTANT CLK_period: TIME := 100 ns;

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 ADVANCED DIGITAL SYSTEM DESIGN

BEGIN

uut: MOORE PORT MAP (CLK => CLK, X => X, Z => Z);

CLK_process: PROCESS

BEGIN

CLK <= '0';

WAIT FOR CLK_period/2;

CLK <= '1';

WAIT FOR CLK_period/2;

END PROCESS;

stim_proc: PROCESS

BEGIN

X<='1';

WAIT FOR 100 NS;

X<='0';

WAIT FOR 100 NS;

X<='0';

WAIT FOR 100 NS;

X<='1';

WAIT FOR 100 NS;

END PROCESS;

END;

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 ADVANCED DIGITAL SYSTEM DESIGN

MEALY CIRCUIT:
SIMULATION
RESULTS:

MOORE CIRCUIT:

MEALY CIRCUIT:
RTL
SCHEMATIC:

MOORE CIRCUIT:

RESULT/ Thus we have successfully design sequence detector using Mealy and Moore
CONCLUSION: circuit using XILINX tools and verified the simulation result.

ROLL NO.: 17
NAME &
NAME: SAMRUDHI CHARDE MARKS SIGNATURE
OUT OF 15 OF SUBJECT
TEACHER Prof. Pradnya
SEM/ BRANCH: VII/ETC-A Maturkar

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