Chapter 4 Digital Test

Architectures

Jin-Fu
u Li
Advanced Reliable Systems (ARES) Laboratory
Department of Electrical Engineering
National Central University
Jhongli, Taiwan
 Outline
† Scan test
† Logic BIST
† Test Compression

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 2

 Evolution of DFT Techniques

Fault
Tolerance
At-Speed Test Low-
Logic
Scan Delay Compres- Power
BIST Defect and
Testing
g sion Testing
Error
Tolerance

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 3

 Scan Testing
† Principle of scan testing
„ In test mode,, the scan chain can change
g a
sequential circuit into a combinational circuit.
Therefore, the test complexity can be reduced
† An example of sequential circuit
X1
Y1
X2 Combinational logic
X3 Y2

FF1 FF2 FF3

D Q D Q D Q

CK

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 4

 Scan Chain Architectures
† Muxed-D scan design
„ Convert storage elements in a circuit into muxed-D scan
cells
† Clocked-scan design
„ Convert storage elements in a circuit into clocked scan
cells
† Level-sensitive scan design (LSSD)
„ Convert storage elements in a circuit into LSSD shift
register latches
† Enhanced
E h d scan design
d i
„ Convert storage elements in a circuit into enhanced scan
cells each consists of D latch and a muxed-D
muxed D scan cell
† Low-power scan design
„ Reduce the dynamic power of the circuit under test in
test mode
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 5
 Muxed-D Scan Design

X1 Y1
PI X2 PO
X3 Combinational logic Y2

PPI PPO

SFF1 SFF2 SFF3

DI DI DI
SI SI Q SI Q SI Q SO
SE SE SE
SE
CK

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 6

 Enhanced Scan Design
† Application
„ Testing
g delay
y faults
† Testing for a delay fault requires applying a
pair of test vectors in an at
at-speed
speed fashion
† An enhanced scan design
„ Use an additional D latch and a muxed-D
muxed D scan
cell to store two bits of data that can be applied
consecutively to the combinational logic driven
by the scan cells

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 7

 Enhanced Scan Design

X1 Y1
X2 Y2
Combinational logic
…

…
Xn Ym
LA1 LA2 LAS
D D D
Q Q Q
UPDATE C C … C

SFF1 SFF2 SFFS

DI DI DI
SDI SI Q SI Q … SI Q
SE SE SE SE

CK …
…
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 8
 Enhanced Scan Design
† Advantage
„ Achieve high
g delay y fault coverage
g by
y applying
pp y g
any arbitrary pair of test vectors
† Disadvantages
g
„ An additional scan-hold D latch is required
„ Maintaining the timing relationship between
UPDATE and CK for at-speed testing may be
difficult
„ Many false paths, instead of functional data
paths, may be activated during test, causing an
over-test
t t problem
bl

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 9

 Low-Power Scan Architectures
† Test power is related to dynamic power
„ P=1/2fCV
/ 2

† Multi-phase low-power scan design

X1 Y1
PI X2 PO
X3 Combinational logic Y2
PPI PPO

SFF1 SFF2 SFF3

DI DI DI
SI SI Q SI Q SI Q SO
SE SE SE
SE
CK
CK21
CK3
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 10
 Low-Power Scan Architectures
† Bandwidth-matching low-power scan design
SI1 SIm
…
ck1 Clock
TDDM controller

Full-Scan
Circuit
S10 S11 S12 S13 … Sm0 Sm1 Sm2 Sm3

ck2
…
t10 t11 t12 t13 … tm0 tm1 tm2 tm3

TDM

…
SO1 SOm
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 11
 Typical Logic BIST System
Test Pattern Generator
(TPG)

Logic
BIST Circuit Under Test
controller (CUT)

Output Response Analyzer

(ORA)

† TPG: generate test patterns

† ORA: compact the test responses of the
CUT into a signature
† Controller:
C t ll generates
t th
the scan enable
bl
signals and clocks

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 12

 Logic BIST Architectures
† Off-line BIST architectures can be classified
into two classes
„ Using the test-per-clock BIST scheme
„ Using
g the test-per-scan
p BIST scheme
† Comparison of test-per-clock and test-per-
scan BIST schemes
„ Test-per-scan BIST: long test time, but low area
cost
„ Test-per-clock BIST: short test time, but high area
cost

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 13

 STUMPS
† STUMPS (self-testing using MISR and
parallel SRSG))
p
„ A test-per-scan BIST design
„ MISR: multiple-input
p p signature
g register
g
„ SRSG: shift register sequence generator
„ G pa
PRPG: parallel
a e SRSG
S SG
PRPG
…
CUT
…
(C)

…
MISR

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 14

 STUMPS-Based BIST Architecture
† To reduce the lengths of the PRPG and MISR and
improve the randomness of the PRPG
„ An optional linear phase shifter and an optional linear
phase compactor is used in industrial applications

PRPG
…
Linear Phase Shifter
…
CUT
…
(C)

…
Linear Phase Compactor
…
MISR

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 15

 CBILBO
† Concurrent built-in logic block observer (CBILBO)
„ Test-per-clock BIST scheme
„ No
N ffault
lt simulation
i l ti iis required
i d
„ Area cost is higher than that of the STUMPS
Y0 Y1 Y2
B1

Scan Out
Scan-Out
MISR
0 D D D B1 B2 Operation mode
1 Q Q Q _ 0 Normal
1 0 Scan
0 1 Test Generation and
0 1D 1D 1D Signature Analysis
2D Q 2D Q 2D Q
1 SEL SEL SEL
TPG

Scan-In B2 SCK X0 X1 X2
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 16
Coverage-Driven Logic BIST Scheme
† Pseudo-random test generation is usually used to
serve as a TPG of a logic BIST
„ Fault coverage is limited by the presence of random-
pattern resistant (RP-resistant) faults
† Four approaches can be used to enhance the fault
coverage of a BIST scheme
„ Weighted
g p
pattern ggeneration
„ Test point insertion
„ Mixed-mode BIST
„ Hybrid BIST

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 17

 Weighted LFSR as PRPG
† Weighted pattern generator
„ Insert a combinational circuit between the LFSR
and the CUT
„ Probabilities of the distributions of 0’s and 1’s
at the input of the CUT can be changed

1 0 0 1

X4
X3
X2
X1

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 18

 Test Point Insertion
† Weighted pattern generation is simple in design,
but achieving adequate fault coverage for a BIST
circuit
i it remains
i a problem
bl
† Test points can be used to increase the circuit’s
fault coverage to a desired level
† Example of inserting test points to improve
detection probability
X1
X2 X1
X3 X2 X4
X4 Y X3 X5
Y
X5 X6
X6 control point
observation point
Min. Detection 1
= Min. Detection 7
Probability
64 Probability
= for Y SA0 or Xi SA1 faults
128
for Y SA0 or Xi SA1 faults

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 19

 Mixed-Mode BIST
† A major drawback of test point insertion is that it
requires modifying the circuit under test
† Mixed-mode BIST
„ Without modifying the CUT
„ Pseudo-random
P d d patterns
tt are generated
t d to
t detect
d t t RP-
RP
testable faults and then some additional deterministic
patterns are generated to detect the PR-resistant faults
† Methods for generating deterministic patterns on-
chip
„ ROM compression
„ LFSR reseeding
„ Embedding deterministic patterns
† ROM compression
„ The size of the required ROM is often prohibitive

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 20

 LFSR Reseeding
† Reseeding with multiple-polynomial LFSR

..

ding
Logic
Decod
…

LFSR
… … …
Poly. Id Seeds
…

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 21

 Embedded Deterministic Patterns
† Many pseudo-random patterns generated during
pseudo-random testing do not detect any new
f lt
faults
„ Some useless patterns can be transformed into
deterministic patterns that detect RP
RP-resistant
resistant faults
„ This can be done by adding mapping logic between the
scan chains and the CUT or in a less intrusive way by
adding
ddi the
th mapping
i logic
l i att the
th inputs
i t tot the
th scan chains
h i
to either performing bit-fixing or bit-flipping
Bit-flipping
† Bit flipping BIST

LFSR Scan Chain

Bit-Flipping
Function

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 22

 Hybrid BIST
† Using BIST circuit to detect the PR-testable faults
and using ATE which applies deterministic patterns
to detect
d the
h PR-resistant
i ffaults
l
† In an system-on-chip, test scheduling can be done
to o
overlap
e lap the BIST runn time with
ith the transfer
t ansfe
time for loading the deterministic patterns from
the tester

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 23

 Low-Power Logic BIST Schemes
† Test-vector-inhibiting BIST scheme
„ Inhibit LFSR-generated
g pseudo-random
p
patterns, which do not contribute to fault
detection from being applied to the circuit
under
d test
t t

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 24

 Low-Power Logic BIST Schemes
† Modified LFSR low-power BIST scheme
„ Partition an n-stages LFSR into two separated or
interleaved n/2-stages LFSRs
„ A test clock module is used to generate the two non-
overlapping clock, CK1 and CK2, for deriving LFSR
LFSR-11 and
LFSR-2
„ Only one part of the CUT is activated at any given time
Test
PRPG
CK1 Clock
Test Tree
LFSR-1
CK Clock CUT
C
Module CK2 Clock
Tree
LFSR-2
2

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 25

 Test Compression
† Test data are inherently highly compressible
because typically only 1% to 5% of the bits on a
t t pattern
test tt that
th t generated
t d by
b an ATPG program
have specified (care) values
† Lossless compression techniques can thus be used
to significantly reduce the amount of test stimulus
data that must be stored on the tester

Compressed
Stimulus Response
mpressor

Stimulus Compacted

mpactor
Scan- Response
Low-Cost Based
ATE Circuit
Decom

Com
(CUT)

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 26

 Broadcast Scan
† This method has been used as the basis of many
test compression architectures, including some
commercial DFT tools
† Concept of broadcast scan
„ Consider two independent circuits C1 and C2 C2. Assume that
these two circuits have their own test sets T1=<t11,
t12,…t1k> and T2=<t21,t22,…t2l>, respectively
„ In the beginning of the ATPG process, usually random
patterns are initially used to detect the easy-to-detect
faults. Some random p patterns are used for C1 and C2, thus
we may have t11=t21, t12=t22, …., up to some ith pattern
„ Then, deterministic patterns are generated for hard-to-
detect faults.
faults Typically,
Typically these patterns have many “don’t
don t
care” bits
„ For a pattern for C1, we can assign specific values to the
don’t care bits in the pattern to detect faults in C2
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 27
 Broadcast Scan Architecture
Scan_input

SC1 SC2 SCk

…

1 2 3 … N1 1 2 3 … N2 1 2 3 … Nk
…

† Advantages
g
„ All faults that are detectable in all original circuits will
also be detectable with the broadcast structure
† Broadcast
d scan can also
l b be applied
l d to multiple
l l
scan chains of a single circuit if all subcircuits
driven by the scan chains are independent
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 28
 Illinois Scan
† Issue in broadcast scan
„ If two scan chains are sharing the same channel, then
the ith scan cell in each of the two scan chains will
always be loaded with identical values. If some fault
requires
qu two
o such
u scan a cells to
o have
a opposite
oppo values
a u in
order to be detected, it will not be possible to detect this
fault with broadcast scan
† Illinois
Illi i scan architecture
hit t
„ The scan architecture consists of two modes of
operations, namely a broadcast mode and a serial scan
mode
„ The serial scan mode is used for the remaining faults that
cannot be detected in broadcast mode
„ Drawback: the compression ratio is degraded

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 29

 Illinois Scan Architecture

Scan In
Segment 1

MISR
Segment 2

Segment 3 Scan Out

Segment 4

(a) Broadcast mode

Scan In Scan Out

Scan Chain

(b) Serial chain mode

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 30

 Reconfigurable Broadcast Scan
Pin Pin Pin Pin
1 2 3 4 Control Line

0 Scan Chain 1
1

0 Scan Chain 2
1

0 Scan Chain 3
1

0 Scan Chain 4
1
Scan Chain 5
Scan Chain 6
0 Scan Chain 7
1
S
Scan Chain
Ch i 8

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 31

 Test Response Compaction
† Test stimulus compression must be lossless, but
test response compaction can be lossy
† Test compaction schemes
„ Space compaction
„ Time compaction
„ Mixed space and time compaction
† Diff
Difference between
b t space compaction
ti and
d time
ti
compaction
„ A space compactor compacts an m-bit-wide output
pattern to a p-bit-wide output pattern, where p<m
„ A time compactor compacts n output patterns into q
output patterns, where
h q<n

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 32

 X-Tolerant Response Compaction
SC1 SC2 SC3 SC4 SC5 SC6 SC7 SC8

XOR XOR XOR XOR XOR XOR XOR XOR XOR XOR

XOR XOR XOR XOR XOR

Out1 Out2 Out3 Out4 Out5

11100
10110
11010
11001
M= 10101
10011
01011
00111
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 33
 X-Tolerant Response Compaction
† Theorem 1
„ If only
y a single
g scan chain produces
p an error ay
y
any scan-out cycle, the X-compactor is
guaranteed to produce errors at the X-
compactort outputs
t t att the
th scan-outt cycle
l if and
d
only if no row of the X-compact matrix contains
all 0
0’s
s.
† Theorem 2
„ E
Errors ffrom any one, two,
t or odd
dd number
b off
scan chains at the same scan-out cycle are
guaranteed to produce errors at the X
X-
compactor outputs at that scan out cycle if
every row of the X-compact matrix is nonzero,
distinct, and contains an odd number of 1’s.
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 34
 X-Masking Technique
Scan Out 1
Mask Bit 1

Scan Out 2
Mask Bit 2
compactor

Scan Out 3
Mask Bit 3

Mask
controller

† Mask data are needed to indicate when the

masking should take place. These mask data can
be stored in compressed format and can be
decompressed using on-chip hardware.

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 35

 X-Impact Technique
† X-impact technique uses ATPG to algorithmically
handle the impact of residual X’s on the space
compactor
t without
ith t adding
ddi any extra
t circuitry
i it
† Example 1: handling of Xs (f1 has a stuck-at-0
fault)

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 36

 X-Impact Technique
† Example 2: handling of aliasing (f2 has a stuck-at-
1 fault)

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 37

 Mixed Time and Space Compaction
† q-compactor with single output

inputs

output

D D D D D

† Different from a conventional MISR,, a q-

q
compactor does not have a feedback path
„ Any error or X injected into the compactor is shifted out
after
f at most five
fi cycles
l
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 38
 UltraScan Architecture
ATE
Test Responses

Pass/Fail comparator

Expected Responses
Test Patterns VirtualScan
inputs
ESI1 … ESIn
ck1 Clock
TDDM controller
VirtualScan SI1 … SIm
Circuit
Broadcaster
Full-Scan S10 S11 S12 S13 … Sm0 Sm Sm2 Sm3
Circuit 1

… ck2

t10 t11 t12 …

t13 tm0 tm1 tm2 tm3
ck1
C
Compactor
t

SO1 … SOm
TDM
ESO1 … ESOn

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 39

 Random Access Scan
† Serial scan design
„ Advantage:g low routing
g area overhead
„ Disadvantages: high power dissipation during
shifting and capture operations; fault diagnosis
is difficult
† Random access scan offers a promising
g
solution
„ Rather than using g various hardware and
software approaches to reduce test power
dissipation in serial scan design, random-access
scan attempts
tt t to
t alleviate
ll i t th
these problems
bl by
b
making each scan cell randomly and uniquely
addressable
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 40
 Typical Random Access Scan Architeture

PI Combinational logic PO

S S S
C C
… C
Row (X)) decoderr CK
S S S
C C
… C SI
… SCK

…
…
SO
S S S
C C
… C

Column (Y) decoder

Address shift register AI

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 41

 Typical Random-Access Scan Cell

D
0
D
I
Q . Q

SI 1
TM S
I
S
AS E CK

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 42

 Progressive Random-Access Scan

Sense-amplifiers & MISR PO

…
SC SC … SC

Combiinational logic
w enable s shift
register
SC SC … SC

…
…
Row

SC SC … SC

…
Column line drivers
TM Test PI
SI/SO Control …
CK logic
l i Column address decoder

CA

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 43

 Shift-Addressable Random-Access Scan
SO

Sense-amplifiers PO
…
SC SC … SC

Combinational logic
w enable shift
register
SC SC … SC

…
…
Row

SC SC … SC

…
Column line drivers
Test PI
TM Control …
CK logic
l i Buffers

SI
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 44
 STAR Compression Architecture
SO

Compactor PO
…
…

national logic
SC SC SC

Row enable shhift

rregister
SC SC … SC

…
…

Combin
SC SC … SC

…
Column line drivers
Test PI
TM Control …
CK logic Decompressor

SI
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 45
 Reconfigurable STAR Compression Architecture
SO

Compactor

PO
…

Combinational logic
SC SC … SC

able shift
register
Row ena SC SC … SC

…
SC SC … SC

C
…
Column line drivers
Test
TM …
Control
0 1 0 1 0 1
PI
CK logic

Decompressor

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 46