Keysight i3070 In-Circuit Test System

Introduction to Test
Methodologies

Multiple Board Versions 7

Limited Access Test Solutions 8
TestJet and VTEP v2.0 Powered! 9
Connect Check 17
Polarity Check 20
DriveThru Test 22

See also:
Analog Testing
Digital Testing
Boundary-Scan Testing
Flash Programming
External Devices (Utility Card)
Balanced Ports and GP Relays (Utility Card)
i3070 LED Test
Multiple-board Testing
The i3070 In-Circuit Test System provides the following features for multiple-board
testing:
• Panel Test - develop tests and fixtures for multiple boards or panels of boards.
• Throughput Multiplier - tests boards simultaneously (one board per testhead
module at one time) to increase test system throughput.
• Dual-Well Shared Wiring - reduces the number of testhead resources needed,
and increases operator throughput by specifying shared (parallel) wiring from
resources to boards.

Panel Test
The i3070 ICT system makes it easier and faster to develop board tests and fixtures
for multiple-board panels. You can use Throughput Multiplier and Dual-Well
Shared Wiring when developing panel tests.
You need to enter the board and X-Y data only once for each type of board to be
tested on the fixture instead of once for every board. The development software
automatically does the following:
• Generates the device tests for the devices on all boards.
• Generates a testplan that controls the testing of the individual boards,
pass/fail reporting, serializing, and datalogging. The status of one board does
not affect the testing of other boards. The testplan allows the operator to
specify which boards of the panel to skip; this is for partially-loaded panels or
for retesting the boards of the panel that failed previously.
• Generates the files and reports needed to build the fixture. The fixture
verification feature automatically instructs you to probe the locations on each
board and checks the connections to those locations.
• During debugging, applies changes to the device test on all boards of the type
currently being debugged. You can also manually change the device test on
just one of the boards, leaving the test on the other boards unchanged.
The i3070 ICT system allows a maximum of 256 boards per
panel.

2 Test Methodologies
 Figure 1 shows examples of panels, which can be:
• Identical boards fastened together in a panel.
• Boards of varying types fastened together in a panel.
• Identical boards to be tested on one fixture that are not fastened together.
• Boards of varying types to be tested on one fixture that are not fastened
together.

Figure 1 Examples of multiple-board panels

Board Board Board Board Board Board

1 2 3 4 1 2

Board Board Board Board Board Board

5 6 7 8 3 4

Board Board Board Board Board

1 2 3 4 1 Board
3
Board Board Board
5 6 2

VTEP/TestJet With Multiple Boards

If you are using VTEP or TestJet on multiple boards, you can instruct the software
to minimize the number of VTEP/TestJet mux cards, or to use one mux card for
every board under test. Figure 2 shows an example.

Figure 2 VTEP with multiple boards

MUX Card

Board 1 Board 2 Board 3

MUX Card MUX Card MUX Card

Board 1 Board 2 Board 3

Test Methodologies 3
 Throughput Multiplier
Throughput Multiplier in conjunction with PanelTest reduces test time by testing up
to four boards of a single-board-type panel simultaneously. You can use
Throughput Multiplier with Dual-Well Shared Wiring.
Because each module of the testhead provides complete test capability, the
modules can perform testing on a board simultaneously. As shown in Figure 3, up
to four boards can be tested at the same time. In this example, a panel of eight
identical boards are assigned as two boards per module:
• Boards 3 and 7 are assigned to module 0.
• Boards 4 and 8 are assigned to module 1.
• Boards 2 and 6 are assigned to module 2.
• Boards 1 and 5 are assigned to module 3.
Boards 1, 2, 3, and 4 can be tested simultaneously; boards 5, 6, 7, and 8 can be
tested simultaneously.

Figure 3 Using Throughput Multiplier on i3070 Series 5

Board 1 Board 2 Board 3 Board 4

Board 5 Board 6 Board 7 Board 8

Module 2 Module 0

Module 3 Module 1

Testhead

Throughput Multiplier supports only single-board-type

panels.

4 Test Methodologies
 Dual-Well Shared Wiring
Use Dual-Well Shared Wiring to specify parallel wiring from resources to boards.
This reduces the number of testhead resources needed and increases operator
throughput by allowing a board to be tested while the operator replaces another
board on the fixture. You can use Dual-Well Shared Wiring with Throughput
Multiplier.
Dual-Well Shared Wiring specifies that the same node on multiple boards share
testhead resources. As shown in Figure 4, node_a on boards 1and 2 are wired to the
same personality pin. With separate support plates and vacuum wells, the system
can test Board 2 while the operator is replacing Board 1 with a new board to be
tested.

Figure 4 Dual-well shared wiring

node_a node_a
Board 1 Board 2
Support Plate

Probe Plate
Probe

Personality Pin Testhead

For the board development process, treat multiple boards as a panel. If all the
boards are the same type, develop a test and fixture for a single-board-type panel;
if the boards are not all the same, develop a test and fixture for a
multiple-board-type panel.

Parallel wiring
You can specify parallel wiring across single-board-type panels and across
multiple-board-type panels.
For parallel-wired boards, you can specify some nodes to be wired independently
instead of in parallel. This is determined by the node name; nodes with a common
name are wired in parallel, nodes with unique names are wired independently.
Because the test system considers all boards of a single type to be identical, a
board with an independently wired node (unique node name) requires its own board
type.
You can specify up to three boards to be wired in parallel.
The fixture must be built with separate support plates and vacuum wells for each
board.

Test Methodologies 5
 You need to modify the testplan to actuate the vacuum wells appropriately for your
test situation. Never allow the vacuum for more than one parallel-wired board to be
actuated at any one time.

Using Dual-Well Shared Wiring with Throughput Multiplier

You can use Dual-Well Shared Wiring with Throughput Multiplier to test multiple
boards simultaneously. You need to assign the boards that are to be tested
simultaneously, to independent modules and a common vacuum well.
In the example shown in Figure 5:
• Boards 1 and 4 are wired in parallel and assigned to module 2.
• Boards 2 and 5 are wired in parallel and assigned to module 0.
• Boards 3 and 6 are wired in parallel and assigned to module 1.
• Boards 1, 2, and 3 are controlled by vacuum A.
• Boards 4, 5, and 6 are controlled by vacuum B.
While Vacuum B is actuated and boards 4, 5, and 6 are being tested, the operator
can remove boards 1, 2, and 3 to replace them with new boards to be tested.

Figure 5 Dual-Well Shared Wiring with Throughput Multiplier

Vacuum A Board 1 Board 2 Board 3

Vacuum B Board 4 Board 5 Board 6

Module 2 Module 0

Module 3 Module 1

6 Test Methodologies
Multiple Board Versions
Use the multiple board versions feature to develop and maintain one test and fixture
for multiple versions of a PC board. This is useful when an Engineering Change
Order (ECO) is applied to a board and you still need to support the previous version
of the board in test. This is also useful if you have a common blank PC board that
can be loaded with different configurations of devices.
Board versions can vary in the following ways:
• analog device values
• devices which are not included on the PC board (not placed)
• a different test library or test method for a device
The following are examples of multiple board versions:
• An analog board when R2 can be any one of three values.
• A memory board that might be configured with different amounts of memory.
• A complex digital device that you might want to test with a digital library or
VTEP.
The differences between board versions cannot include X-Y locations of devices or
probes and connectivity changes. The use of multiple board versions requires the
same blank PC board for all versions.
When using a test with multiple board versions, the test developer describes the
base board and then describes the differences between versions. The test system
automatically generates the tests and testplan. At runtime, the test operator must
specify which version of the board is to be tested.

Test Methodologies 7
Limited Access Test Solutions
Traditional in-circuit test techniques are based on the assumption of 100%
electrical access to nodes on a PC board. Increasingly, electronic manufacturing
trends such as smaller board size, higher density packaging, and higher node count
boards result in a test environment in which 100% nodal access is not always
possible. Consequently, board test developers are faced with the difficult challenge
of attaining acceptable test coverage in limited access situations. To address this
challenge, Keysight has developed the following software solutions designed to
help you maximize test coverage in a limited access environment.
• DriveThru Test
• Boundary Scan
• Cover-Extend Technology (CET)

8 Test Methodologies
TestJet and VTEP v2.0 Powered!
• About TestJet and VTEP v2.0 Powered!
• VTEP/iVTEP/NPM Test Method
• Cover-Extend Technology (CET)
• VTEP Probes
• Enhancements
This section describes VTEP v2.0 Powered! (VTEP, iVTEP, NPM, and CET) and
TestJet, which can be used to test for manufacturing defects such as open
connections, missing devices, and improperly positioned (skewed) devices.
Information on VTEP also applies to TestJet, unless otherwise specified.
Connect Check is available on Mux systems only.

See also: What Test to Use for Different Device Types

About TestJet and VTEP v2.0 Powered!

VTEP is a combination of advanced measurement hardware and improved software
algorithms which dramatically improve the noise characteristics, stability, accuracy
and repeatability of TestJet measurements. With these enhancements, reliable
measurements down to single-digit femtofarads can now be made.
The VTEP/TestJet method does not require test vectors or that power be applied to
the device under test. Because VTEP/TestJet tests are fast to develop, you can
release your test and fixture to production quickly; then, add powered digital and
mixed testing later.
You can use VTEP/TestJet to test most devices that have a lead frame or metallic
pins or leads to which the VTEP/TestJet probe can capacatively couple.
iVTEP extends the measurement capability of VTEP. More accurate measurements
can be made using existing VTEP hardware. These measurements are less
dependent on lead-frame geometries than VTEP or TestJet. Autodebug has been
updated to add iVTEP capability automatically on a per-pin basis. Test
development, hardware, and fixturing are the same as VTEP.
NPM (Network Parameter Measurement) extends the measurement capability of
VTEP for connectors and sockets. For the first time at in-circuit test, opens on
connector power and ground pins can be detected and diagnosed. This capability
will be essential as signal speeds increase and defects on ground return paths
cause signal integrity problems.
See VTEP/iVTEP/NPM Test Method on page 10.

Test Methodologies 9
 Cover-Extend Technology (CET) extends the measurement capability of VTEP into
powered testing by using the Boundary Scan output cell to test the connectors and
socket signal pins. This capability extends the Boundary Scan limited access
solution on non boundary scan devices with the use of VTEP and CET signal
conditioner card hardware. (See Cover-Extend Technology (CET) on page 11.)
VTEP, iVTEP, NPM, and CET are collectively known as VTEP v2.0 Powered!

VTEP/iVTEP/NPM Test Method

VTEP1 is an unpowered test of the connectivity from each pin on a device to the
circuit board. The system uses the VTEP hardware to measure the capacitance from
a pin of a device to the VTEP probe. The measurement is repeated for each pin on
the device, except power and ground pins. Pins that are tied together are tested as
one pin.
iVTEP is a breakthrough for integrated circuits. For the first time, the measured
capacitance value is less dependent on shrinking lead-frame geometries. iVTEP will
work only on devices with little or no lead-frames (like uBGAs and flip-chips) and
devices under heat spreaders. It will not work on connectors. Its noise signature is
up to 7 times better than VTEP which is in turn 3 to 7 times better than TestJet. This
is a proprietary and patent-pending technique.
NPM is a breakthrough for connectors. Finding opens on power and ground pins
using vectorless test has always proved problematic at ICT. First, directly injecting
a source voltage on power or ground nets causes significant voltage drops due to
the presence of large capacitances on these nets. Second, individual open defects
are masked since many pins are typically tied to these nets. NPM does not rely on
this direct approach. Instead, existing VTEP hardware is used to make network
parameter measurements of the connector pins during the execution of the VTEP
test. Opens on power and ground pins are detected and diagnosed based on these
network parameter measurements.
The i3070 In-Circuit Test Software release 7.20p includes an enhancement to
reduce noise and improve the stability of VTEP tests. A new throughput adjustment
option provides an improved guard path (lower impedance); this enhanced
guarding applies to both VTEP (generic) and NPM. A significant improvement in
guard path impedance will be obtained just by using the new option alone, but a
further reduction is possible if the user chooses to wire an unused digital ground
resource to J1 Pin 1 of the VTEP mux. For details, see Improving Guard Path
Impedance on page 15.

1. Information on VTEP also applies to TestJet, unless otherwise specified.

10 Test Methodologies
 Cover-Extend Technology (CET)
Cover-Extend Technology (CET) is the latest addition to the VTEP v2.0 Powered!
test suite which targets limited-access PCBAs.
CET is a hybrid between VTEP and Boundary-Scan. It draws the best from what
each technology offers and enhances the overall capability of i3070 In-Circuit Test
Systems. The following are the key contributions of the constituent technologies:
• VTEP – Simple, robust and fast measurement using VTEP sensors and
amplifiers.
• Boundary-Scan – A world-wide standardized test methodology (IEEE 1149.x
standard). It provides limited-access capability – the ability to control the I/O
functions of individual pins through the use of only four pins of the test access
port.
The Cover-Extend measurement is accomplished by using the Boundary Scan
output cell to drive signals to the connector/socket and non boundary scan
devices. The signal pickup by the VTEP sensor plate is amplified and filtered by the
Cover-Extend signal conditioner card to improve signal quality.
CET automatically generates test vectors on the target device under test.

CET Requirements
To use CET, you will require the following:
• i3070 In-Circuit Test Software release 07.20p or later
• Cover-Extend license
• CET Signal Conditioner Card
The CET Signal Conditioner Card has to be connected to a CET- capable VTEP
mux card. Note that the VTEP mux+ref card is not CET capable.
• USB Interface Kit
This provides the components to enhance the ASRU card and make it available
for use with CET.

Test Methodologies 11
 VTEP Probes
Three types of VTEP/TestJet probes are available:
• The standard probe is available in sizes up to 2.5 inches square, is mounted on
spring-loaded probes, and can be used in the top and bottom sides of the
fixture.
• The connector probe is 6.0 x 0.5 inches, is mounted on foam pads, and can be
used only in the top side of the fixture.
• The small probe has sensor plates available for B-C and D size surface mount
(SMT) device packages, is mounted on spring-loaded probes, and can be used
in the top and bottom sides of the fixture.
You can use multiple standard or connector probes on large devices or trim the
probes for smaller devices.
TestJet probes and Signal Conditioner Boards (mux cards) are also used for Polarity
Check which is described in Polarity Check on page 20.
TestJet Signal Conditioner/Reference Boards (mux+ref cards) are also used for
Connect Check (for Mux systems only) which is described in Connect Check on
page 17.
Figure 6, Figure 7, and Figure 8 show the three types of VTEP probes; Figure 9
illustrates the standard probe detecting an open pin.
The analog capacitance measurement is accomplished by connecting the S bus to
the pin being tested, the I bus to the VTEP probe, and the G bus to all other pins on
the device. The signal is amplified and filtered to improve signal quality.
Each VTEP probe is connected to a port on a mux card (or mux+ref card) that is
mounted in the fixture. Because each mux card has 64 ports, you can connect up
to 64 probes on each mux card.
The mux card improves the signal quality and reduces the number of test resources
required. There can be a maximum of 15 mux cards (or mux+ref cards) per fixture.
For VTEP no more than 6 can be connected in one module. Each mux card address
is set by 4 switches on the mux card. The mux card addresses must be numbered 1
through 15; address 0 is reserved.
For PanelTest and Throughput Multiplier, there can be a maximum of 6 VTEP mux
cards, or 15 TestJet mux cards per module. Connect Check (on Mux systems only)
requires that one of the 15 mux cards be a mux+ref card.
Do not mix VTEP and TestJet muxes in the same fixture. Do
not mix VTEP and TestJet probes in the same fixture.

12 Test Methodologies
 Figure 6 Standard VTEP probe

Mux Card
Fixture Top

VTEP Probe
Device

Fixture Bottom

Connections to ASRU Testhead

Guard Source
and Control Cards (G Bus) (S Bus)

Figure 7 VTEP Connector probe

To Mux Card
Milling for Electronic Plate
and Wires

Top Plate
Foam Pad VTEP Probe

Connector PC Board

Figure 8 Small VTEP probe

Mux Card

Fixture Top

Small VTEP Probe

Device

Fixture Bottom

Connections to ASRU Testhead

Guard Source
and Control Cards (G Bus) (S Bus)

Test Methodologies 13
 Figure 9 Detecting an open connection

Mux Card
Fixture Top

VTEP Probe
Device
Open

Fixture Bottom

Connections to ASRU Testhead

Guard Source
and Control Cards (G Bus) (S Bus)

If a connection is open, as shown in Figure 9, the defect is indicated by a smaller

value of capacitance.
Failing devices and pins are listed on the report is device (usually the strip
printer). The list of failing devices and pins includes the measurement values. See
Example 1.

Example 1
--------------------------------
VTEP Report for "vtep".
Wed Dec 23 13:23:33 1992
VTEP ET Board
--------------------------------
Device: U1
Failed Open #1, Measured 10.7
(22321)
U1.12
--------------------------------

If more pins fail than are specified by the report limit statement, the printed list
is truncated and the message Too many to print is added. The report limit
statement is explained later.
Figure 10 shows VTEP probes in the top and bottom sides of the fixture for testing
devices on both sides of the circuit board.

14 Test Methodologies
 Figure 10 VTEP probes on both sides of the fixture

Mux Card
Fixture
Top
VTEP Probes

PC Board

Mux Card

Fixture Bottom

Connections to ASRU Testhead

and Control Cards

Enhancements

Improving Guard Path Impedance

The i3070 In-Circuit Test Software (starting with release 7.20p) introduces a new
method for reducing the guard path impedance without requiring the use of general
purpose relays and effectively isolates the test node signal with reasonable
standard deviations.
When generating VTEP tests, the software uses the option throughput
adjustment 4, an enhanced throughput mode that provides a significant
improvement in guard path impedance.
A further reduction is possible if the user chooses to wire an unused digital ground
resource to J1 Pin 1 of the VTEP mux. (Unused digital ground refers to a ground pin
that is not wired to the DUT.)
The user can either identify an unused pin card ground pin or create one by
removing its wire from the fixture. The digital ground resource must come from one
of the modules used by the VTEP test. This unused pin is then wired directly to the
mux connector, J1, pin 1 using a heavy gauge wire (Figure 11).
Connecting the network of guarded nodes to digital ground, which is also wired to
ground on the mux connector (J1 pin 1) has the effect of grounding the guard point
more effectively. Ground on the mux connector is wired to a control card
unswitched ground. This improved guard path provides a short, low impedance
path to ground and bypasses the impedance of the backplane. An unused (e.g.
unwired) digital ground must be chosen for the additional wire so that no
unexpected connection to system ground occurs during the unpowered statement.

Test Methodologies 15
 Figure 11 Wiring unused pin to J1, pin 1 of VTEP mux

16 Test Methodologies
Connect Check
Keysight Connect Check is used to test for manufacturing defects such as open
connections, missing devices, and improperly positioned (skewed) devices.
Connect Check is available on Mux systems only.
We recommend that you use VTEP or TestJet instead of Connect Check if possible.
(See What Test to Use for Different Device Types.)

Connect Check Test Method

Connect Check uses the intrinsic pin protection diodes of the device-under-test to
verify contact between the device and the PC board. Refer to Figure 12 on page 18.
The Connect Check test does the following:
1 Applies a negative voltage on the pin being tested (response pin) to forward
bias its diode, and measures the resulting current IR.
2 While maintaining the bias voltage on the response pin, applies a larger
negative voltage on another pin (stimulus pin) to forward bias its diode,
causing current flow IS.
3 Measures IR again and calculates the difference in the current measurements.
Because IR and IS both flow through the common substrate resistance, IR
decreases if both pins are connected to the PC board; if either pin is not
connected, IR does not change.
Parallel current paths in the DUT or surrounding circuit cause changes in IR if
the pins are connected or open. Connect Check uses guarding to decrease the
effect of these parallel paths. The test method uses learning, thresholds, and
test limits to determine if the change in current is due to connectivity or parallel
current paths.

4 Compares the difference in IR measurements to the test limits to determine

connectivity.
5 Repeats the test for each response pin up to six times using a different
stimulus pin each time; the response pin passes as soon as connectivity is
determined once.

Test Methodologies 17
 Figure 12 Connect Check test method
Device Under Test
Vcc

Response Pin

Stimulus Pin Internal

-
Logic
V
-
+
V
IS IR
+ A

Gnd R Substrate

A TestJet mux+ref card in the test fixture provides the reference voltage that biases
the response pin.
A digital driver on a hybrid card in the testhead provides the pulsed stimulus
voltage that biases the stimulus pin. This requires the testhead to include at least
one Hybrid Pin card per module.
The ASRU Card in the testhead measures the current.
When the test is executed, failing pins for each device are listed on the report is
device (usually the strip printer). If a failing pin has only one stimulus pin in the test
(as for U3 in Example 2), the stimulus pin is also listed.

Example 2
------------------------------------------
ConnectCheck Report for "connectcheck".
Wed Mar 06 13:23:33 1996
Test Board
------------------------------------------
ConnectCheck Open #1 Device: U1
Pin 4 (BRC 211150)
------------------------------------------
ConnectCheck Open #1 Device: U2
Pin 11 (BRC 211129)
ConnectCheck Open #2 Device: U2
Pin 17 (BRC 211127)
------------------------------------------
ConnectCheck Open #1 Device: U3
Pin 14 (BRC 211149)
Stim Pin 12 (BRC 211131)
------------------------------------------

If more pins fail than are specified by the report limit statement, the printed list

18 Test Methodologies
 is truncated and the message Too many to print is added. Note that several failing
pins might indicate an open ground pin.
For debug, you can instruct the system to send a report to the printer is device
by executing the connectcheck print level is all statement. The report includes
the following information for all tested pins:
• each stimulus pin and brc
• the measured current in uA before stimulus (I1)
• the measured current in uA after stimulus (I2)
• the difference in the measured currents
• the test limit (learned value listed in the source file * test limit multiplier)
• whether the test passed, failed, or was being learned (pass = measured > test
limit)

Example 1-1 Sample report

Device: U2
RESPONSE PIN STIMULUS PIN I1 I2 MEASURED TEST LIMIT
21 (11570) 6 (11311) 64803 63474 1329 805.23 PASS
21 (11570) 26 (20216) 62969 62001 968 777.88 PASS
21 (11570) 19 (21121) 63020 62369 651 760.16 FAIL
21 (11570) 20 (21129) 62986 62366 620 544.55 PASS
21 (11570) 23 (20225) 63053 62635 418 438.94 FAIL
21 (11570) 18 (21115) 63053 62685 368 433.33 FAIL
24 (11572) 6 (11311) 50942 49725 1217 1115.23 PASS
24 (11572) 22 (20215) 50925 49774 1151 987.88 PASS
24 (11572) 9 (21141) 50891 49874 1017 965.27 PASS
24 (11572) 20 (21129) 50976 50059 917 884.42 PASS
24 (11572) 23 (20225) 50891 50040 851 878.24 FAIL
24 (11572) 12 (21125) 50991 50225 766 823.54 FAIL

Test Methodologies 19
Polarity Check
• Testing Capabilities
• Test Method

Testing Capabilities
Polarity Check automatically tests the orientation (polarity) of electrolytic
capacitors on the board under test. This unpowered test detects reversed
capacitors before they can fail and possibly damage the board or cause safety
hazards.
You can use Polarity Check to test tantalum and aluminum Surface Mount
Technology (SMT) and axial lead capacitors. Capacitors that are connected in
parallel are tested individually. See Polarity Check capacitor testing capabilities for
the capacitor values that can be tested with Polarity Check.

Requirements for Testing Both Sides of a Board

Using VTEP or TestJet probes and revision B mux cards, you can test capacitors on
both (top and bottom) sides of the board. The small VTEP probe provides two sensor
plates:
• B-C size for B or C size SMT devices.
• D size for D or E size SMT devices.
The Polarity Check technique requires VTEP probes.
The development software now uses transfer probes for wiring the topside VTEP
mux cards. This eliminates the external wires in the fixture that go to the VTEP
mux card on the top plate. The transfer probes will only be installed if topside
probing is allowed in the board file or the fixture defaults file. VTEP transfer
probes will not be added to existing fixtures even if topside probing is allowed.

See TestJet and VTEP v2.0 Powered! for information on VTEP technology.

20 Test Methodologies
 Test Method
Polarity Check uses a VTEP or TestJet probe and four signal probes to test the
polarity of an electrolytic capacitor. As Figure 13 shows, there must be two
accessible points on each node to which the capacitor is connected.
Failing devices are listed on the report is device (usually the strip printer). The list
of failing devices includes the measurement values. For example:
-------------------------------------
Polarity failure on C1
Measured: 0.15
Threshold: 1.00
************** WARNING **************
Capacitor Polarity Check has failed.
Replace device prior to power up.
-------------------------------------
If more devices fail than are specified by the report limit statement, the printed
list is truncated and the message Too many to print is added. The report limit
statement is explained later.

Figure 13 The Polarity Check test method

Mux Card

Fixture Top

TestJet Probe

Capacitor

Fixture Bottom

Connections to ASRU Testhead

and Control Cards

Test Methodologies 21
DriveThru Test
• About DriveThru Test
• DriveThru Impedance Threshold
• Interpreting a VTEP Report Ticket

About DriveThru Test

DriveThru Test is one of the software solutions designed to address limited access
test problems.
Many factors in board design can result in limited electrical access, including high
density packing, reduced component size, and increased node count. Limited
access means you cannot place a bed-of-nails fixture probe on a node.
DriveThru provides a means to test integrated circuits and/or connectors when
there is no access directly on the device under test. It is particularly suited for high
node count board designs in which small-valued series damping resistors are
placed at driver pins to absorb reflections in high-speed digital designs.
DriveThru helps to resolve limited access test problems in two ways: it allows you
to use VTEP to test boards with limited nodal access, and it allows you to selectively
remove probe access from digital device outputs.
• Extending the capabilities of VTEP
Without DriveThru, VTEP requires a node with probe access to test a device’s
pins. Although it is possible to test a device with inaccessible pins, test
coverage is reduced for that device. With DriveThru, if there is a series
component between a pin on the DUT and a node with access, the pin can be
tested.
DriveThru can test devices when one or more pins of the device under test are
inaccessible, if these pins are attached to series components (resistors,
capacitors, inductors, jumpers, switches, and fuses). The node on the other
side of the inaccessible pin must be:
• accessible
• not fixed
• not tied to ground through an impedance that is lower than the impedance
of the series component that is being tested through
• Using Access Consultant to perform a node analysis
Utilize DriveThru in conjunction with Access Consultant, which performs a
node analysis on a board, identifies nodes that are required, nodes with
potential for access removal, and automates the process of removing access
from selected nodes.
When you have a board in development that has more nodes than your
testhead has resources, use Access Consultant software to identify which
nodes are required and which ones are not needed when testing digital devices

22 Test Methodologies
 with VTEP and to remove access to selected nodes. When the test
development software writes your tests, these nodes are not probed. DriveThru
defines stimulus points both directly on the device under test, if that node is
accessible, and on remote stimulus points buffered from the device by a series
resistance, if the node is not accessible.

Limitations of Keysight DriveThru Test

DriveThru cannot resolve limited access situations in which one or more pins of the
device under test are inaccessible, if these pins are not attached to series
components. Also, DriveThru cannot test through more than one series component.
Drive Thru does not:
• diagnose wrong-valued resistors
• test through buffers, inverters, or combinational logic
• test through more than one series component

DriveThru Impedance Threshold

The default setting and recommended value for the DriveThru Impedance
Threshold is 10,000 ohms. The purpose of the threshold is to limit the impedance of
series devices that can be tested through using DriveThru and VTEP. The software
calculates appropriate threshold values for capacitors, resistors and inductors
based on this threshold.
In some cases, the impedance of the series device associated with a limited access
location may be above the defined threshold. Any device with a series impedance
above this value is not included in an DriveThru/VTEP test. You can increase the
DriveThru threshold value to accommodate devices with higher impedances in an
DriveThru/VTEP test. For example, if you have set the value at 33 ohms, but have
50 ohm series resistors on your board, the 50 ohm resistors are not considered for
DriveThru testing. You can increase the threshold to exceed 50 ohms, so that the
desired devices can be tested.

Test Methodologies 23
 Interpreting a VTEP Report Ticket
A VTEP Report generates information to help you understand the details of your
VTEP/ DriveThru tests. This information is intended to help you diagnose
failures.The VTEP report includes the following information:
• Failing devices with a list of pins indicating if they have been tested, unused,
probed
• The date of the VTEP test
• The name of the board being tested
• Test information which includes the device name, the pins that are tested, the
node used to test the pin, and the series component that is tested through.
Figure 14 and Example 2 show an example circuit and repair ticket.

Figure 14 Example of devices listed on report ticket

R1
8 R1-2 8 U305-8
R2
R6
7 7
R3 R2-2 R5-2
U304 R5 J1 R7
U303 3 U305 6
6 J1-2
R4 R8
R4-2 R7-2
5 5 R9
R8-2

Example 2 A sample VTEP report ticket

----------------------------------------
VTEP Report for "vtep".
Wed Mar 24 13:04:21 1998
production board
----------------------------------------
Open #1 Device u303
Pin 5 Node R4-2
Through r4
Pin 6 Node R4-2
Through r4
Measured 136.2 (BRC 21104)
Open #2 Device u303
Pin 7 Node R2-2
Through r3
Through r2
Measured 109.4 (BRC 21101)
Open #3 Device u303
Pin 8 Node R1-2
Through r1
Measured 143.1 (BRC 21103)
1820-1430 4-bit Binary Counter
----------------------------------------

24 Test Methodologies
 Open #1 Device u304
Unknown pin Node J1-2
Measured 140.2 (BRC 21110)
----------------------------------------
Open #1 Device u305
Pin 5 Node R8-2 Note: This is the test node, node R7-2 is
Through r8 not used in test.
Measured 136.2 (BRC 21105)
Open #2 Device u305
Pin 6 Node R5-2
Through r6
Pin 7 Node R5-2
Through r5
Measured 109.4 (BRC 21107)
Open #3 Device u305
Pin 8 Node U304-8
Measured 143.1 (BRC 21109)
1820-1430 4-bit Binary Counter
----------------------------------------

Test Methodologies 25
26 Test Methodologies