Roll No. Total No.

of Pages : 02
Total No. of Questions : 08
B.Tech (CSE)/(IT) (Sem.–3)
DIGITAL ELECTRONICS
Subject Code : BTES-301-18
M.Code : 76435
Date of Examination : 21-10-21
Time : 2 Hrs. Max. Marks : 60

INST RUCT IONS T O CANDIDAT ES :

1. Attempt any FIVE question(s), ea ch que stion c arrie s 12 marks.

1. Using the Boolean Algebra, simplify the expression :

AB   A  B  C  AB

2. Use a Karnaugh map to simplify the function to its minimum sum of product form :

X  ABCD  ABCD  ABCD  ABCD

3. Draw the block schematic of Magnitude comparator and explain its operation.

4. Draw & explain the block diagram of a 4-bit parallel adder / Sub-tractor.

5. Write a note on FPGA with a neat diagram.

6. Simplify using K-map.

f (ABCDE) = ΠM(6,9,11,13,14,17,20,25,28,29,30) and implement using NAND/NOR

logic.

7. a) Explain the principle of operation of a dual slope ADC. How is it advantageous over
ramp type ADC?

b) Design a synchronous Mod-6 counter using JK-flip-flops.

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8. Write short notes on any Two :

a) EPROM

b) Shift register

c) Master-slave JK flip-flop

Note: Any student found attempting answer sheet from any other person(s), using
incriminating material or involved in any wrong activity reported by evaluator shall be
treated under UMC provisions.
Student found sharing the question paper(s)/answer sheet on digital media or with any
other person or any organization/institution shall also be treated under UMC.
Any student found making any change/addition/modification in contents of scanned copy of
answer sheet and original answer sheet, shall be covered under UMC provisions.

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