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CMOS Technology

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Snehil Sanyal Shashank Bhushan

Indian Institute of Technology Guwahati MIT Academy of Engineering
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DesignandReali
zati
onofCMOSCi r
cui
tsUsi
ng
Dual
Int
egratedTechni
quetoReducePower
Dissi
pation

pass an encour agi ng solution f oradmi ni

steri
ng hi ghly
powerconst rai
nedsy stems.Byscal ingt hesuppl yv olt
age
Abstract —Many a change have been t aking pl ace i nt he (Vdd)bel ow thethr esholdv oltage( Vth)oft hedev ice,the
technol ogiesandt r
endsi nv eryl argescal ei ntegr ati
on( VLSI ) subt hreshol
dcur rentbecomesav erysl owlychargeand
theseday s.Themai nf actorsinVLSIar eAr ea, Speedandpower .
As t her ei s a need ofl ow powerci rcui tsi n allr ealtime dischar gesatjunctionsf orcircui toper ati
on.Butoper ati
on
applicationsl i
keconsumerel ectronics,medi cal appl i
cat i
ons,and withmi nimum poweri sachiev ed.Her et heneedoft heuse
mobi leappl icati
ons.Sol ow powerdesi gnt hemei sr aised.As ofdualsuppl yvol
tagei si
fbyappl yonl ysinglenomi nalVdd
thispaperi nt roducesamet hodt or educepowerdi ssi pati
oni n tot heSoC.Theent ir
esuppl yv oltagei sapplicablef orall
digit
alCMOS ci rcui
tsusi ng powergat ed dualsub t hreshol d systems i n SoC.Butsome sy stems hav el ow power
(PGDST)suppl yv olt
age.Thepur poseoft hisdualsuppl yv oltage dev i
cesi nSoC.Byusi ngdualsubt hresholdsuppl yv olt
age
i
ssomeoful t
ralowpowerappl icationsandt heci rcuitswi thl ow
techni que,the dissi pati
on ofpoweri sr educed,ev en
suppl yv ol
tages.Theydi dnotgi vesat isfact oryresul tswi thsingl e
suppl yv oltage.Thi ssecondar ysuppl yv ol t
agei sassi gnedf or thought herearesomel imitationsl ikepowerdi ssipation,
gates, component sdependsont hecr i
ti
calpat handpat hdensi ty andl owper f
ormance.Toav oidt hesepr oblems,thispaper
i
n t he ci rcuit. Power gat i
ng t echnique i s appl i
ed f or proposes a new PGDST t echni que t or educe power
correspondi ngci r
cuitatsuppl yv ol t
agel ev eltor educepower dissipationindigi
tal CMOSci rcuit s.
dissipation.Thi sentirewor kisimpl ement edi nMent orGr aphics
Back End Toolwi t
h Py xis Schemat ic 10. 3v ersion on Li nux Thenextphaseoft hepaperisorgani
zedasf oll
ows:
operat i
ngsy stem.Byusi ngt hi
st echniquehi ghamountofpower Thesecondsect i
ondealswithpr
oposedsystem.Thet hi
rd
dissipationi sr educedi ndesi gnedci rcuitsandi ncr easest he sect
ion deals wi
thI mplement
ati
on.The fourt
h sect i
on
performanceoft hedesi gnedci rcuits. deal
swi thResult
s,andf i
nal
l
yConclusionandReferences
arepresent
ed.
I ms—Subt
ndexTer hr
esholdcir
cui
ts,
dualv
olt
agedesi
gn,
power
gati
ng,
powerdi
ssi
pat
ion,
perfor
mance
I
I. PROPOSEDSYSTEM
Int
hismethodther
earetwotechni
quesnamel
ypower
I
. I
NTRODUCTI
ON gat
inganddualsub-
thr
eshol
dsuppl
y.
VLSIisanimpor t
antinaugur alintheel ect r
onicdesi gn
automationindustry.InthepastVLSIscal ingoft echnology
i
ncreasespowerdensi tyismor et hanexpect ed.Allmoder n
SoCdev icesdemandf ormor epower .Finallyov eral
lusage
ofpoweri sdr amat i
call
yi ncreased.Dualsub t hreshold
supplyv ol
tageci r
cuitsdesi gncanr educet heconsumed
powerup t o some ext entby scal i
ng t he const rained
parametersoft het r
ansistor.TheSubt hr esholdci rcui
ts
 2:
Int
ernal
str
uct
ureofpowergat
ingci
rcui
t
Powergat i
ngisoneoft het echniquesusedtoreduce
thepowerconsumpt ionofadesi gn. Int hi
s,t
heblocks
whi char enotusingatt hepar t
icularti
mecanbeshutof ft
o
reduce t he leakage poweri nt hatdesi gn.So parall
el
combi nat i
onoft woNMOSt r
ansi st
ors( N1andN2)wi t
h
enablesi gnalasai nputisused,t osleepsuchbl ocks.
These N- MOS t ransistor
s ar e al so used as sl eep
transistorswhenenabl esignalisnotpr esentasaninput.
Thei nternalpowergat ingcir
cuitisshowni nfi
gur
e2.
Fi
g1:
Blockdi
agr
am ofpr
oposedmet
hod
Thepowergati
ngt echniqueisappl
iedfordualsub
t
hreshol
dsuppl
yvol
tagecircui
tsshowni
nf i
gur
e1.

Fi
g
downt heparamet ersofthet r
ansi st
or,li
kechannellengt h,
and Gate widt
h oft he transistor.Forex actfunctional
operati
onofsubt hresholdlogiccircuit
,suppl
yvolt
age( Vdd)
shouldbegreatert hanthecertainmi nimum vol
tage( Vmin).
Vmincanbeexpressedi ntheoreticalformis
Fi
g3:
Cir
cui
tfordual
suppl
yvol
tage S
2l
n1 (
1)
ApplyingDualSuppl yVol tagef orgatesi n aci rcui
ti s
seeni nfigure3.Assi gningdualsuppl yv oltagedepends
WhereVT=KT/ Qi sthethermalv oltage,K=1. 381x10-23
upont hecriti
calpat handpat hdensi ty
.Criticalpat hmeans
J/Ki sBol t
zmann’sconst ant
,Ti sabsol utet emper at
urei n
l
ongestpat h,pathdensi tymeansdensi tyofdi fferentpaths
Kelvin,q=1.602x10-19 C isdenot esel ectronicchar ge.At
i
nt he circuit
.Lowersuppl yv olt
age (Vddl)appl yt ot he
300K ( room t emper ature)
. Gener ally t r
ansistors ar e
dev i
ceswhi chhav elessdensi t
y .Theyareusedt or educe
designed in such a wayl i
ke width oft he gate shoul d
staticpowerl eakageoft heci rcui
t.Highsuppl yv olt
age
greaterthant hechannell ength.Tor educel eakagei nsub
(Vddh)isappl yt ot hedev iceswhi chhav ehi ghdensi tyt o
threshol
dr egionthewi dthtolengthr atiowi llbeconsi der
mai ntaint he ov eral
lci r
cuitper f
ormance.Forexampl e,
asa1: 1r ati
o.Stat
icpowerusedbyt heci rcuit,whenci r
cuit
cir
cuitf orassi gningdualv ol
tagei sshowni nf i
gure3.I n
i
snotpr ocessofswi tching.
thisAND gat ei sassi gnedwi t
hhi ghsuppl yv oltageand
NOTgat eisassi gnedwi thl ow supplyv oltage.I nment or Pstatic=Istatic xVdd (
2)
graphics,thisdualsuppl yv olt
agei sassignedatSi mulati
on
Thel ow v ol
tageoper ati
oni s,t hattheconduct i
onof
l
ev el.
tr
ansistor
sduet odif
fusionofchar gecar r
iers.Transi
stors
A PowerDissi
pat
ion areconnect edtol ow thresholdsuppl yvoltage,thent he
To oper
atethe cir
cui
tsi n saf
e operati
ng area,is channelwi l
lbef ormedf orv erylow v ol
tage.Sot hatev en
depends on t
he powerr el
eased by thatci r
cui
t.The forah ighth r
esholdsup pl
yv ol
taget hep ow erdissi
p at
ion
si
mplestwaytoreducethepowerdi ssi
pati
onofaci rcuit byt het r
ans i
storisless. Ifth er
ea ree qual paths,near
wit
houtchangi
ngt heoper
ati
onoft heci r
cuit
,byscal i
ng thr
esh ol
dv olt
ageissu f
fici
en ttoc ondu ctt
h etransi
stors.I
t
meanst her
earenononcriti
calpat
hsandcri
ti
calpat
hs.So 4:
Inv
erterschemat
icwit
ht r
ansi
stor
s
thenstati
cpowerisreduced.Thedynamicpowercanbe Thecor respondi ngi nputf ortheci rcuitisappliedat
expressedbyt
heequati
onformi s. portA.Theout putoft heci r
cuitistakenf rom outputpor
tB.
Infi
gure5gi vedet ailswi thassigningenabl esignaltothe
2 3 cir
cuitatsupplyvoltagel evel
.
Pdynami
c=pcap+pt
ransi =(
ent cL+c)
*vdd*
f*N
(
3)
Wher
eNi
sthel
ogi
cal
val
uest
hatar
eswi
tchi
ng,
Fi
stheswi
tchi
ngf
requency
,
Ptransient:I
tisdefi
nedast heamountofpowerusedwhen Fi
g
l
ogi coft hedev
icechanges, 5:
Inv
ert
ersi
mul
ati
onschemat
ic

Pcap:I
tisdef i
nedast heamountofpowerusedt ocharge B NANDCi rcuit
l
oadcapaci tance. N AND ci
rcuiti s designed int ransist
or leveland
apply
ingthehighsuppl yv ol
tagethati
srepresentedas( Vddh)
I
II
. I
MPLEMENTATI ON i
sappl i
edatsuppl yv ol
tagelevelisshowni nfigur
e6.Hi gh
The enti
re worki simplemented in Ment
orGr aphi
c supplyvol
tage (
V ddh)i
s appl
ied,f
or t
he accurat
e funct
iono f
BackEndToolwi thLINUXplatf
orm.Thistooli
sveryuseful theN ANDc i
rcuit
. Inputof t
h eci
rcuiti
sAa ndBa ppl
ieda t
todesignt hecircui
tsfr
om physicaldesi
gnapproach.The theinputport
s.O u t
putistakenfrom theportY.
si
mul at
ionandanal ysi
sofresult
sal
sof l
exi
blei
nrealti
me.
Digi
talcircui
ts,inv er
ter
,NAND,2t o4 Decoder ci
rcui
t,
4:
1Mul t
ipl
exer,Ring counter
,D Fli
p-Fl
op,Fulladderare
desi
gnedandi mplementedusingdualsuppl
yvolt
agewi t
h
powergatingtechnique.
AI nvert
erCir
cuit
I
nvert
erdesign int r
ansist
orleveland apply
ing t
he Fi
g 6:
NANDci
rcui
tschemat
icwi
thtr
ansi
stor
s
nominalVdd,thatisr epresent
ed as (
Vddl)i
s appli
ed at
supplyvolt
agelevel
isgiveninfi
gur
e4. I
nfi
gur
e7t hereisanI Nsignalisappliedast
heenable

Fi
g

Fi
g7:
NANDci
rcui
tsi
mul
ati
onschemat
ic

C 2t
o4DecoderCi
rcui
t Fi
g8:
2to4Decoderdual
vol
tageschemat
ic
The2t o4decodercircui
tdesignedwithdualsub- Powergati
ng technique accor
ding t
ot he proposed
thr
eshol
dsuppl
yvolt
ageshowni nf
igure8.Thei
nputsare met
hodisshowninfigure9.Thispowergat ingt
echnique
S0,S1andoutput
sareD0,D1,D2,D3.Vddlisappl
iedfor
NOTgates,
andVddhi
sappl
iedforNANDgates.
i
sappl
i
edatthesupplyvolt
agelevelf
ordesignedci
rcui.
t
 Fi
g9:
2to4Decodersi
mul
ati
onschemat
ic
i
nputsignal.Pat
terni
nputi
stakenasi nputsignal
.Inpl
ace
ofpat
terninputalsot
akepulseinputbutpulseisananlog
i
nputform patt
ernisi
ndigi
talf
orm.

D 4:
1Mul
ti
plexerCi
rcui
t
Figure10shows4: 1mul ti
plexercir
cui
twithdualsub
t
hreshold supplyv olt
age.Forappl y
ing multi
ple suppl
y
vol
tages,themul t
iplexerisimplementedwi t
hNOT,AND,
ORgat es.Theinputsar eSo,S1,i1,i
2,i3,i
4.Theout puti
s
OUT.

Fi
g10:
4:1Mul
ti
plexerdual
vol
tageschemat
ic

Employingpowergat ingtechni
queatsuppl
yv ol
tage
l
evelforthe4:1multi
plexercir
cui
tandi
tisshowninfi
gure
11.Theinputsforpowercircui
tar
eIN1,
IN2,andI
N.

Fi
g11:
4:1Mul
ti
plexersi
mul
ati
onschemat
ic
E DFl
i
p-Fl
opCi
rcui
t
Dfl
i
p-fl
opusi
ngdualsub-
thr
eshol
dsupplyv
olt
agewit
h
combi
nati
onofNOTandNANDgat esisshowni
nfigur
e12.
SPACES-
2015,
DeptofECE,
KLUNI
VERSI
TY

Fi
g12:
DFl
i
p-Fl
opdual
vol
tageschemat
ic

Infi
gure12Vddli
sappl
i
edf orNOTgateduet othelow ci
rcui
tr
y.Vddh appl
iedforNANDgatebecauseofmor
e
t
ransist
ors,
alsot
ogetpr
operoutput
.Powergat
ingtechni
queisappli
edforDf l
i
p-f
lopispr
esenti
nfi
gur
e13.

Fi
g13:
DFl
i
p-Fl
opsi
mul
ati
onschemat
ic

.
Fi
g15:
Simul
ati
onschemat
icoff
ull
adder
G RingCount erCircuit
Ther i
ngcount ercircui
tdesignedwi t
hdualsub-thresholdsupplyvolt
ageshowninf i
gur
e16.Ri ngcounteri
sa
sequent
ialci
rcuitandi simplementedusingDfli
p-f
lops.Df li
p-f
lopisusedasmemor yelement.Theinput
sforDfli
p-
fl
opareclock,count err
eset.Supplyvol
tagei
slowVthf orNOT, highVthf
orNANDcircui
tsinDfl
ip-fl
op.

Fi
g16:
Ringcount
erdual
vol
tageschemat
ic
The4i nputNORgateisdr
ivenbysuppl
yv ol
tageVdd.Powergat
ingtechni
queaccor
dingt
otheproposedmet
hod
i
sshowni nf i
gure17.Fort
heri
ngcounterci
rcui
t.Thi
sPowergat i
ngtechniquei
sappli
edatthesuppl
yvolt
agel
evel
f
ordesignedcircuit
.
F FullAdderCircui
t
Ful
ladderusi
ngXOR,AND,andORgateswi
thapplyi
ngmult
ipl
esub-
thr
eshol
dv ol
tagesVddlf
orORgat
e,Vddhf
or
ANDgat
e,Vddf
orXORgat
e.Applyi
ngi
nput
sareA,B,
Cinandout
putareS,
Couti
sshowninfigur
e14.

Fi
g14:
Gat
elev
eldi
agr
am off
ull
adder
Byper
for
ming1bi
taddi
ti
ont
henr
esul
tisobt
ained.Enabl
esi
gnal
canbeappl
i
edf
ort
hreest
ages,
asl
i
keVdd,
Vddl,
andVddh.Thi
sst
ruct
urei
sshowni
nfi
gur
e15.

Fi
g17:
Simul
ati
onschemat
icofr
ingcount
er

IV RESULTS
Thesi
mul
ati
onr
esul
tsf
ordesi
gnedci
rcui
tsi
nMentorGraphi
car
eshowni
nfi
gur
e18t
ofi
gur
e25.

Fi
g18:
Simul
ati
onwav
efor
m ofi
nver
ter
Theinvert
edwav ef
ormf ori
nputAisshowninfigur
e18.I
nputAispul
seinput
.Forf
ir
stper
iodofenabl
esi
gnal
i
nputtheinver
sionoperat
ionisdonef
orsecondper
iodnooper
ati
onisper
for
med.

Fi
g19:
Simul
ati
onwav
efor
m ofNANDci
rcui
t
SPACES-
2015,
DeptofECE,
KLUNI
VERSI
TY
Vini
stheinputofenabl
esignalf
orNANDci
rcui
t,i
fVini
sof
fst
atet
henci
rcui
tgoest
oof
fst
ate.Sonoout
puti
s
appeari
ngthati
sshowninfigur
e19.

Fi
g20:
Decodersi
mul
ati
onwav
efor
m wi
thcl
ocki
nput
s
Theappl
yi
ngenabl
esignali
nput
sar
eVi
nandVi
n1anddecoder
input
sar
eS0andS1al
sooneoft
hedecoder
out
putQ0isshowninf
igure20.

Fi
g21:
Decodersi
mul
ati
onwav
efor
m wi
thout
put
s
TheRemaini
ngout put
sareshowninfi
gure21.Thoseoutput
sar
eQ1,Q2,andQ3.AtON posi
ti
onofenabl
e
si
gnalonl
ytheci
rcui
tisoperat
edot
her
wiseci
rcui
tinof
fstat
e.
 Fi
g24:
Ful
laddersi
mul
ati
onwav
efor
m
Forf
ulladdert heinput
sareA,B,Cinandenabl
esi
gnali
nputI
Nispl
ott
edandonebi
taddi
ti
onwi
thout
put
sas
sum (
S),
carry(Cout)i
sshowninfi e24.
gur

Fi
g25:
Ringcount
ersi
mul
ati
onwav
efor
m

Thecorr
espondi
ngout
put
sforr
ingcount
erar
eQ0,
Q1,
Q2,
andQ3.Thei
nputi
senabl
esi
gnal
,Whi
char
ecl
ear
ly
showninfi
gure25.
TABLE1
Compar
isonofpowerdi
ssi
pat
ionwi
thexi
sti
ngt
echni
que

Fi
g22:
4:1Mul
ti
plexersi
mul
ati
onwav
efor
m
Her eenabl
einputformult
ipl
exeri
sVin2 i
staken,sel
ect
ionl
i
nesS0,S1andout
puti
sYi
sshowni
nfi
gur
e22.
Mul
ti
plexeri
nputsi
0,i
1,i2,
i4ar
eshowni nfi
gure10.

Fi
g23:
DFl
i
p-Fl
opsi
mul
ati
onwav
efor
m

Theinput
sfortheDfl
i
p-fl
oparetheenabl
esi
gnali
nput(
In)
,D,
CLKandt
heout
put
sar
eQ,
Qbar
.AsI
NisONt
hent
he
Dfl
i
p-fl
opoutputi
sobtai
ned.Thati
sshowninf
igur
e23.

Table1givest
hepowerdissi
pat
ioncompari
sonwit
hexi
sti
ngtechnique.I
nthi
sindi
vi
dualci
rcui
tcomparisonwi
th
supplyv
olt
agel
evel
s,powerdi
ssi
pati
on,
alsoshownt
hebet
terper
formanceinpowerdi
ssi
pati
onreduct
ion.
TABLE2
 Powerdi
ssi
pat
ionofci
rcui
tswi
thPGDSTt
echni
que.

SPACES-
2015,
DeptofECE,
KLUNI
VERSI
TY
Table2givestheCompari
sonofdif
fer
entCMOSci r
cui
tsusi
ngPGDSTt echnique.Theappl
i
edhighandl
ow
subt
hreshol
dvolt
agesfori
ndi
vi
dual
cir
cui
tsandthepowerdi
ssi
pat
ionf
oreachcircui
tisshownint
abl
e2.

Var
iat
ion ofPowerDi ssi
pat
ion f
orAdiabati
c
CMOSandConv ent
ionalCMOSDigi
tal
Cir
cuit
s
switching ener
gy is notdecreasing att hesame r ate,
whichl ead toincreasei npowerdi ssipat
ionand al so
makesheatr emovalmor edif
fi
cultandexpensi ve.Thus,
Abst r
act—From t
hepastf ew decades,VLSItechnologyhas powe rconsumpt ion becomes a maj orlimitation for
beengr owingtothelargeextent
.Allcredi
tforthi
sgoest othe numbe rofelectr
onicsy st
ems.Thi spaperst udiest he
i
ncr easi
ngusageofi ntegrat
edcircuit
sf oreveryembedded ma jor sources of t he power dissipati
on and t he
system, mobi le technologi
es, comput i
ng sy stems, et c. techniques toreduce the powerdi ssipat
ion t o much
Increasi
nggr owthanduseoft echnologyhasi ncreasedt he mor eextent.AnADI ABATICapproachi sperfectsolution
thir
stf orlow energyorpowerconsumpt ion.An Adi abatic forthedesignofpowerandener gyeffici
entdesi gns[21].
approachi sper f
ectsoluti
onf orthedesi gningofpowerand
energyef fi
cientdesigns.Thewor d‘Adiabat i
c’referst othe ADI
ABATI
CCI
RCUI
TS
changeofst atethatoccurswi t
houtthel ossorgai nofheat .
Thispaperst udi
eslow powerdesi gntechniquesandj usti
fies The term “ adiabat
ic”referst othe t
hermodynamic
the need of ener gy r ecov ery adiabati
c ci rcuits ov er processt hatexchangesnoener gywit
henvir
onment,and
conventionalCMOS.Thel ogicci r
cui
tsbased on t radit
ional therefor
et hereis no occurrence ofpowerorener gy
CMOS Logi cand posi t
ivef eedbackAdi abat i
cLogi cwi llbe dissipat
ion [ 22]
[23]. Duri
ng t he swit
ching pr
ocess,
designed and si mulated usi ng standard 90nm CMOS adiabati
ct echnologyreducesthe
technologyataf r
equencyof50MHz.TannerEDAt ooli sused
fordesigningt heschematicandanal ysi
s.TheS- EDITi sused
todesignt heschemat icandT- SPICEisusedt oSimul ateand 978-
1-4788-7225-8/
15/$31.00©2015I EEE
checkt her esult
sofPowerDi ssipat
ion.W- EDITi sused t o Gurvi
nderSingh,PushpinderSharma
displ
ayt hesimulati
onresultsint hefor
m ofwav ef
orm. Assi
stant Professor, El
ectroni
cs and
Communi cat
ion
Key
wor
ds—Adi
abat
icci
rcui
ts,
Powerdi
ssi
pat
ion,
PFAL BabaFaridGr oupofInsti
tutes,
Bathi
nda, I NDIA
I
NTRODUCTI
ON gurv
indersi
ngh@gmai l.
com, pushpinderbf
gi@gmail
.com
Duetov astdevelopmenti nVLSIt echnologyi nt he
fi
eld of embedded sy stems, mobi l
e t echnology,
computi
ng sy st
em, et c. demand f or l ow-power powerorener gydissipationandr eusessomepar tof
consumpti
on hasi ncreased.Dev iceswith high power theener
gybyr ecycl
ingi tf
rom thel oadcapacit
ance.
consumpti
onar enotsor el i
able.Packingandcool ingof
suchdevi
cesi salsodi f
ficult,whichleadt oincreasei n xForr eusingener gy,theadi abati
ccircui
tusest he
costofdev ice [
1][
3].Fur t
hermor e,thereis const ant pri
nciple of Const ant current sour
ce power
i
ncreasei
nnumberofgat esperchi parea,butt hegat e supply.
 xForreduci
ngpowerdissi
pati
onadiabat
iccircuit
s S
usest hepr
inci
pleofTrapezoi
dalorsinusoidal r
. Ful
l
yAdi
abat
ic Par
ti
alAdi
abat
ic
vol
tagepowersuppl
y. No.
Powersupplyr ecov
ers
Whi leoper ati
ngonaci rcuititcanuser ev ersibl
el ogi
c 1 Somechar
geis
al
lthechargeont heload
. t
ransf
err
edt
otheground
ori r
rever si
blelogi c[9][17].Whenci rcuiter asesabi tof capaci
tance.
i
nf ormat iontheni tissai dt obeani rr
ev ersibl
epr ocess, 2 I
thasmorecompl
ex Ithassimpler
andwhent heci rcuitdoesnoter asebi tofi nformat i
on . ar
chi
tect
ure. ar
chit
ecture.
theni tiscal ledr eversibl
el ogic.Adi abaticci r
cui t
suses EnergyLossi sdirectl
y
principalofr eversibl
el ogicsandi sener gyef fi
cientwhen Nonidealswi
tchesl
oss
3 proport
ionaltothe
compar ed wi t
h ot her t echnologies. These ci r
cuit
s ener
gyduet ol
eakage
. capacit
ancedr i
venand
curr
ent.
dissipateener gyasheatdur ingswi t
chi ng.Tor educet hi
s squar
eoft hresholdvalue.
dissipationofener gytherear etwor ules: Itdoesnotf acemuch
Faceal otofprobl
ems
pr
oblem wi threspecttothe
xAtransist
orshouldbeswi tchedoffwhenther
eis 4 wi
thr especttotheoperati
ng
oper at
ingspeedandt he
voltagedif
ferencebetweensourceanddr
ain. . speedandt heinput
spower
input spowercl ock
xAtransist
orshoul dbeswitchedonwhent her
eis clocksy nchroni
zati
on.
synchronizati
on.
currentfl
owingt hr
oughit
. SI
MULATI
ONRESULTS

Fi
g.1andFig.2showst
heChar
gingandDischarging Allt he desi gn struct
ur es based on Conv entional
i
n convent
ionalCMOS cir
cui
tand Adiabat
ic System CMOSLogi candAdi abat i
cSwi tchingLogicaredesi gned
r
especti
vel
y. and si mul ated using st andard TSMC 90nm CMOS
technologyandanoper ati
ngf r
equencyof50MHZ.The
l
oadcapaci t
anceof0. 05pfi susedi ncaseofi nv erter,
NOR gat e and Ful ladder ,whi lei n case of l oad
capacitance of 0. 02pf i s used. Tanner EDA v 13
schemat i
cbasedt oolknownasS- EDIThav ebeenused
forthedesi gningt heSchemat i
cofci rcui
ts.Theanal ysis
oftheci rcuit
sisdonei nT-SPICEofTannerEDAv 13.The
result
ant wav eform of t he out put is displ
ayed i n
Fi
gur
e 1.Char
ging and Di
schar
ging i
n Conv
ent
ional wav eform edi t
orofTannerEDAknownasW- EDIT.The
Sy
stem basiccel l
sl i
keNOTgat e,two-inputNORGat e,t
wo-to-one
Mul t
iplexer,oneBitFullAdderar edesignedandaf t
ert hat
theyar eanal y
zedf orbot hconv enti
onalandadi abat i
c
CMOS.
A.DesignofConv enti
onal2*1Mul t
ipl
xer
The t r
adit
ionalCMOS based 2* 1 Mul t
ipl
exer is
designed inS- EDIT ofTannerEDA i nSt andard 90nm
CMOSTechnol ogyasshowni nFig.3.Iti
ssi mulatedinT-
Figur
e2.Chargi
ngandDi
schar
ginginAdi
abat
icsy
stem SPICESi mulat
or[ 3]
[4]
[12].
The transi
entanal ysi
s wit
h 2. 5V v olt
age sour ce,
ADIABATI CLOGI CTYPES capaciti
veloadof0. 02pfand50MHzf r
equencyar eused
Duringl it
eraturesurvey,wef ounddi ff
erenttypesof forthesimulati
on.Fig.4showst hesi mulatedresults.
adi
abaticci r
cuits[8][
22][
24].Theycanbegr oupedinto
twofundament alki
nds:
x Ful lyAdiabati
cCi r
cuit

x Par
ti
all
yener
gyr
ecov
eryAdi
abat
icCi
rcui
t(Quasi
)

Popular Par t
iall
y Adiabaticf amilies incl
ude t
he
foll
owing[ 16]
:
x Ef
fici
entChar geRecov er yLogic
(ECRL).x 2N- 2N2PAdi abati
cLogi c.x
Positi
veFeedbackAdi abaticLogic(PFAL) .x
NMOSEner gyRecov eryLogic(NERL) .x
ClockedAdiabat i
cLogic(CAL).x Tr ue
Singl
e-PhaseAdi abati
cLogic(TSEL) .
TABLEI
.DI
FFERENCE BETWEEN FULLY ADI C CI
ABATI TS AND PARTI
RCUI AL
ADI CCI
ABATI RCUITS
 Fi
gure3.Schemat
icofConv
ent
ional
2*1 Technol ogyasshowni nFi g.5.ItissimulatedinT-
Mult
ipl
exer SPI
CE Si mul ator[3]
[4][
6].The t r
ansientanalysis wi
th
si
nusoidalv olt
agesour ce,capacit
iveloadof0. 02pfand
50MHz f requency ar e used f orthe simulati
on.The
si
mulatedr esultsar
easshownbel owi nFi
g.6.

Fi
gur
e4.Si
mul
ati
onResul
tof2*
1Mul
ti
plexer

Thef i
rstandsecondwav eformfrom bottom shows
t
woi nputs.Thet hi
rdwavefor
m showst heselectli
ne Fi
gur
e5.Schemat
icofPFALMul
ti
plexer
whi
lethef ourt
hshowst heout putwaveform.Thef i
ft
h
wavef
orm givesthepoweranal
ysisofthecir
cuit
. Thefir
sttwowav efor
msf rom bott
om showt heinput
.
Thet hi
rdwavefor
m showst heselectli
ne.Thefourt
hand
B.Desi
gnOfPFAL2* 1Multi
plexer fi
fth gi
ves the outputand i t
s complimentar
y output
ThePFALCMOSbased2* 1Mul t
ipl
exeri
sdesignedi
n respect
ivel
y.Thesixthgi
vesthepoweranal y
sis.
SEDITofTannerEDA.I
tusesSt andard90nm CMOS
Itisimplementedinthestandard90nm t echnologyand
si
mul at
ed i nt he T-SPI
CE simulator,r espect
ively
.The
tr
ansientresult
sareobtai
nedinW- EDITasshowni nFi g.11
andFig.12f orsum andcar
ryoutputsrespecti
vely
.

C.DesignofConv ent
ional1BitFul lAdder
TheCMOSbasedOne- BitFullAdderisdesignedi
nS-
EDITwi t
h90nm CMOSTechnol ogyandsi mulatedwit
hthe
T-SPICESimulatorwiththesuppl yvolt
ageof1. 8V,a
capaciti
veloadof0.05pFand50MHzoff r
equency.The
schemat i
cdesignofonebi tfulladderisshowni nFi
g.7and
thetransi
entsimulat
edr esult
sar eshowni nFig.8
[10]
[21][
23][
26].

Fi
gur
e10.Schemat
icofPFALFul
lAdder(
Car
ry)

Fi
gur
e7.Schemat
icofConv
ent
ional
Ful
lAdder
 Fi
gur
e6.Si
mul
ati
onResul
tsofPFALMul
ti
plexer

Fi
gur
e9Schemat
icofPFALFul
lThef
ir
stthr
eewavef
ormsfrom bott
om showstheinput
sA( 01010101),B
(
00110011)andC( 00001111).Four
thandfi
ft
hwavefor
m showstheoutputscar
ryandsum respecti
vely
,
whil
ethesi
xthwavef
orm showsthepoweranalysi
softhecircui
t

[
2][
11]
. Fi
gur
e12.Si
mul
ati
onr
esul
tsofFul
lAdder(
Car
ry)

D.Desi
gnofConv
ent
ional1Bi
tFul
lAdder
Thefi
rstt
hreewaveformsfr
om bot
tom showthei
nputs,
Apart
ial
l
yadi
abati
clogicfamil
yPFALone-bitFul
lAdderwhi
lethet
opt wowav ef
ormsgivet
hepoweranalysi
sof
bl
ockcanbeimplementedasshownint heFi
g.9(forSUM)ci
rcui
tandoutputr
eceivedr
espect
ivel
y.andFi
g.10(for
CARRY)bel
ow,r
especti
vel
y[6][
10]
[23]
[24].
 CONCLUSI
ONANDFUTURESCOPE POWER 4.
6579418Pw 1.
318593Pw
RESULTS
Fr om theabov eobser vati
on,i
tcanbeconcl udedthat
PFAL t echni
que i s energy effi
cientas compar ed to (
PFAL)
TABLEIV. COMPARI
SONBETWEENTHEPOWERRESULTSOFNORGATE
Conv ent
ional or t radit
ional technique. The power
CIRCUI
TS
di
ssi pationisgreatl
yr educedduet or ecycli
ngprocessin
NORGATE PREVI OUSYEAR PRESENT
PFAL.Whencompar edwi ththepr evi
ousy earitcanbe RESULTS RESULTS
noticed t hatthe powerr esult
s ar er educed wit
ht he
SI
MULATI
ON 1.
8:-vol
tage 1.8V:
-vol
tage
decr easei nt
echnologyused. source sour
ce
CONDI
TIONS
0.05pF:- 0.
05pF:
-
Inf ut
ure,researcherscandesi gnotherlogicci
rcuit
s capacit
ance capaci
tance
l
ikede-multi
plexer,shi
ftregi
steretc.ort
hesameci rcuit
s 50MHz: - 50MHz: -
wit
h di f
ferent technology. The power compar i
son f
requency f
requency
betweenconv enti
onalCMOSci rcui
tsandadiabati
cPFAL TECHNOLOGY 180nm 90nm
CMOS di git
alci r
cuits based on 90nm t echnol
ogy at
50MHzf requencyisshownbel owi nthetabl
eII. USED
POWER 9.
1454464Pw 8.
866097Pw
TABLEII
. COMAPARISONBETWEENPOWERDISSI
PATI
ONOF RESULTS
CONVENTI
ONALCMOSCI TSANDADI
RCUI CPF
ABATI ALCMOSDI GI
TAL
(
conv
ent
ional
)
CI
RCUI
TS
POWER 6.
9542012Pw 4.
136027Pw
CI
RCUI
TS CONVENTI
ON PFAL RESULTS
DESI
GNED AL (
PFAL)
NOT 4.
223813Pw 1.
31859
TABLEV.COMPARISONBETWEENTHEPOWERRESULTSOF2*1MULTIPLEXER
3
2*1 PREVIOUSYEAR PRESENT
Pw MULTIPLEXER RESULTS RESULTS
NOR 8.
866097Pw 4.
13602 2.5V:
-vol
tage 1.8V:
-vol
tage
7 sour
ce sour
ce
Pw SI
MULATI
ON 0.02pF:- 0.
05pF:
-
2*1 9.5e-8Pw 7e-9Pw CONDI
TIONS capacit
ance capaci
tance

MULTI PLE (0.00000095) (0.

00000 50MHz: - 50MHz: -
f
requency f
requency
XER 0007)
TECHNOLOGY
FULL 19.87048Pw 9.
86526 180nm 90nm
USED
ADDER
POWER 2.
2e-
7Pw 9.
5e-
8Pw
(SUM) Pw
RESULTS (
0.0000022) (
0.00000095)
FULL 3.
04657
(
conv
ent
ional
)
ADDER 4
POWER 2e-8Pw 7e-
9Pw
(CARRY) Pw (
0.00000002) (
0.000000007)
RESULTS
Whencompar edwit
ht hepr ev
iousy earresul
tsitcan
(
PFAL)
observet hatf orthesamesi mulat
ioncondit
ionsast hatof
previ
ously used [ 1][
2][3][
4] but usi
ng 90nm CMOS TABLEVI
. COMPARI
SONBETWEENTHEPOWERRESULTSOFFULL
ADDERCIRCUI
TS
technologyi nsteadof180nm CMOSt echnologythent he
PREVIOUSYEAR PRESENT
powerdi ssipation i
sr educed as compar ed wi tht he FULLADDER
RESULTS RESULTS
previ
ousy ears.
1.
8:-vol
tage 1.8V:
-vol
tage
source sour
ce
TABLEI
II
. COMPARI
SONBETWEENTHEPOWERRESULTSOFNOTGATE
CI
RCUI
TS SI
MULATI
ON 0.05pF:- 0.
05pF:
-
NOTGATE PREVIOUSYEAR PRESENT CONDI
TIONS capacit
ance capaci
tance
RESULTS RESULTS 50MHz: - 50MHz: -
SI
MULATI
ON 1.
8:-vol
tage 1.
8V:
-vol
tage f
requency f
requency
CONDI
TIONS source sour
ce TECHNOLOGY
0.05pF:- 0.
05pF:- USED 180nm 90nm
capacit
ance capaci
tance
50MHz :
- POWER 21.
546534Pw 19.
87048Pw
50MHz: -
f
requency RESULTS
f
requency
TECHNOLOGY 180nm 90nm (
conv
ent
ional
)
POWER 13.
64454Pw 9.
86526Pw
USED
RESULTS
POWER 7.
9551340Pw 4.
223813Pw (
PFAL-
SUM)
RESULTS
POWER 7.
654049Pw 3.
046574Pw
(
conv
ent
ional
) RESULTS
(
PFAL-
CARRY)
 SUNGMOKANG,
SENI
ORMEMBER,
IEEE

Abstract—Powerdi ssipationisoneoft hemosti mpor tantf actorsin

VLSIdesi gnandi t
st echnologychoi ce.I tbecomesi ncreasinglymor e
i
mpor tantt oreducethepowerdi ssipationast henumberofdev i
cesi n
VLSIi ncreases.Thereforeaccur atesi mul ati
onofpowerdi ssipationis
hi
ghlydesi rabl
ewhi l
eci r
cuitsaresi mul atedwi t
hcircuitsimul atorssuch
as SPI CE.Thispaperpr esentsanaccur atemet hodf orsi mul ati
ngt he
powerdi ssipati
onwithuseofadependentcur r
entsour ceandapar al
lel
RC circuit.The steady-statev oltage acr oss the capacitorr eads t he
averagepowerdr awnfrom t hesuppl yv oltagesOürce.Si mulationr esul
ts
areshownf orCMOSci rcuit
s.
Fi
g.1.Anof t
en-
proposedschemeforrneasur
ingtheaver
agecurr
ent
drawn f rom t
hev olt
agesourceVI
)D.Thei deaist
ocalcul
atethe
I
.INTRODUCTI
ON ayeragepowerby

Powerdi ssipat i
oninint
egr at
edci rcuit
sisclosel yr el
at edt othe
choice oft echnol ogy,circuitdesi gn,and al so t he scal e of
i
ntegr at
ion.Si ncet hescaleofi ntegrati
onhasbeenof tenl i
mi t
ed TABLE1AVERAGECURRENTSOBTAI
NEDwr
rHTHEMETERI
NFI
G.1
by t he accept able maximum power di ssipation [ 1],ci rcuit
designer spayspeci alatt
entiont othechoi ceoft echnol ogyand
applyci rcui
tt echniquestor educet hepowerdi ssipation.Oneof
themaj orreasonsf ortheCMOSt echnologyt obecomeamaj or (
Themeasur
edci
rcui
tisshown
forcei nt hecur rentVLSIist hatt hepowerdi ssipationi nCMOS
cir
cuitsi ssignifi
cantlyl
owert hant hatinothert echnol ogyci rcuits in
atcompar ablespeed.Ev enaf terchoosi ngat echnol ogy ,VLSI
designer sneedt omi ni
mizet hepowerdi ssipationwhi lemeet i
ng
otherdesi gnobj ectiv
essuchasspeed, chiparea, devicecost ,and IF 0 m
1F 0 m
reli
abi
li
ty. Therefor
ei ti s quite usef
ult o simul at
e power Fi
g,4andT*600nS.
)
dissi
pation accurat
elywhi l
e ci
rcui
ts ar
e analyzed with ci
rcui
t
simulatorssuchasSPI CE[ 2]
.Thispaperwilli
ntroduceasi mple
yetaccur at
e" powermeter"thatcanbei nsert
edasasubci rcui
t
withoutdist
urbingtheori
ginalci
rcui
tbehavi
or. 0.
027xI
(F
0.
000x10-
8

I
l.DRAWBACKSI
NCONVENTI
ONALMETHODS
Fig.1showsanof ten-mentionedschemef ormoni t
oringt he
averagepowerdi ssipationi nint
egrat
edcircuits.Inthi
scasea
whereTi stheper i
odcor r
espondi ngt othemachinecycleofthe
l
ar gecapacitori sinsertedi nseri
eswiththesuppl yvolt
ageVI )D
ci
rcuit
,andV\( 0)i
ssett ozero.
sour ce.Itappear st o be a v iabl
e means so l ong as t he
capaci t
ancev alueislargeenoughnott oint
roduceanysi gnif
icant I
nr eal
it
y,thecalculat
edv alueofI DDdependsst rongl
yon as
series impedance.When t he seri
es impedance is smal l
,t he showni nTableI.Foralargev alueofq, thecor
respondi
ngperi
od
steady -
statev oltage acr oss the vol
tage vx can be used t o T needst obei ncreasedpr oportionall
ysinceotherwi
se ( T)
calculatetheav eragecur rentas would notev en be detectable.The r esul
tsshown in Tabl
eI
i
ndicatethatt
hisschemei snotusabl e.
cxv
x(T) Others met hods for esti
mati
ng t he power
consumpt i
onarebasedonformul
as.Forexampl
e,the
frequent
lyusedformul
aforCMOSpowerdissi
pat
ionis
[3]

Manuscri
ptreceivedOctober22,1985.Thi sworkwassuppor t
edi n Pcr
v/)
Df
par
tbyt heSemiconductorResearchCorpor
ation(SRC)underGr antRSCH
Rd-06049-
5. wher eCTi st hetot aleffectivccapaci tanceaf fectedbyt hel ogi
c
The aut
hori s withthe Coordi
nated Science Laboratoryand t he changei namachi necy cleandfi sthemachi necy clefrequency .
DepartmentofElectr
icalandComput erEngineeri
ng,Universit
yofI l
li
nois Theappl icationoft hisformul at oreali ntegratedcircuit
sofev en
atUrbanaChampaign,Urbana,I
L61801.IEEELogNumber8609887. amoder atesi zeisnotpr acti
calmai nlybecausei ti sdifficultto
estimateCT.Theest i
mat ionofCTr equi resnotonl yident if
ica-
ti
on ofst ate-changi ng logic gat es,butal so t heiref f
ectiv
e
capaci t
ancesi nt hegat er egi
onsanddr ainr egi
onsal ongwi t
h
backgat é bi asi
ng ef f
ect s.Ther efore,i n pr act
ice,t he abov e
formul acannotbeappl iedt ot heaccur atemoni toringofpower
dissipati
oni nl ar
ge- scal
ei ntegratedcircuits.
 I
llNONI
NVANI
VEPOWERMETERS
Nottodisturbthemagnit
udeofcur rentdr
awnf r
om the
powersupplyinthesi
mulat
ion,thesubcir
cui
ttobeinsert
ed
i
nserieswit
ht hepowersupplyshoul
dnothav eanyloadi
ng
eff
ect
.Sucha

01986I
EEE
890 t
henatt=T

(
5)
Fi
g.2,AsubCircui
twithacurrent
-cont
roll
edcur
rentsour
ceanda Thi
ssuggest
sthatVp(
T)=Pav
gwhen
par
allelRCci
rcui
tformeasur
ingtheav er
agepowerconsumpt
ion
byreading (
=%DCpf
. 6)
I
EEEJOURNALOFSOLI
D-STATECI
RCUI
TS,
VOL.SC-
21,
NO.5,
OCTOBER1986

subcir
cuitcanber
eal
i
zedbyusingacurrent
-cont
rol
l
ed
dependentsourceoravol
tage-cont
rol
l
eddependent
source[4].
A.PowerMet
erwi
thaCur
rent
-Cont
rol
l
edCur
rentSour
ce

Fi
g.2 shows a subcircui
tthat i
s composed of a
curr
ent
contr
oll
edcur
rentsourceandaparal
lelRC ci
rcui
t.
Theshunt
resistorRvi srequir
edi nthesimulati
ontopr ovideadc
path.Thei nserti
onof0- Vindependentv ol
tagesour ce
doesnotchanget hei ntr
insiciddint hecircuit.Al
so,
duet otheuni dir
ecti
onalityofthedependentsour ce, Vin(
t)
thesubci r
cui tdoesnoti mposeanyl oading.Wi tha Fig.3.Asubcir
cuitwit
hav ol
tage-cont
rol
ledcurr
entsourceandaparal
l
el
RCcir
cuitf
ormeasuringt
heav eragepowerconsumpti
onbyreadi
ng
properchoi ceoft hecur rentgainpar amet erß,t he
voltageacrosst hecapaci torq,inthesubci rcuitwil
l
readt heaveragepowerconsumpt i
onPav g.Thepr oper
valueofßcanbe
derivedasf oll
ows.Firstwenot ethat parall
elRCcircuit
.Someear l
ierversi
onsofSPI CEdi dnotal
low

cur
rent
-cont
rol
l
edsour
ces.I
nsuchcases,
thesubci
rcui
tinFi
g.3
(
1)
Fr
om t
hesubci
rcui
tinFi
g.2 canbeusedi nst
ead.Theseri
esresi
stancerxshouldbe
smallsothatt
hedist
urbancei
niddisnegligi
ble.Fort
his
ci
rcui
t,(
2)canbemodifi
edas
(
2)
wher
eis=zddandK,
(0)=0.Sol
vi
ngf
orVpi
n(2)
y
iel
ds •¯gri
m xdd (
7)
( dt
3)
when
wher
ea-
1/R)
Cv.
—IfwechooseRvandCpsuch
t
hat
(
4)
I
dd (
8)
whi
chsuggest
sthat

or

(
9)

I
V.APPLI
CATI
ONTOCMOSCI
RCUI
TS
 B.PowerMet
erwi
thaVol
tage-
Cont
rol
l
edCur
rentSour
ce 4.
6

Fi
g.3 shows a subci
rcui
tformonitori
ng t
he average
powerconsumpt
ionwithavolt
age-
cont
roll
edcur
rentsource
3.
6
anda
Tocompar ether esultsofpr oposedappr oacheswi t
ht he
resul t
sshowni nTåbl eI ,wechoset omoni tort heav erage
currentdr awnf rom t hepowersuppl yv oltagei nsteadoft he
aver agepowerconsumpt i
on.Thi smodi ficat i
onshoul dnot
causeanyconf uSionsi ncet hev alueofßorgm i ssi mpl y
scaleddownby%D;i .e.,insteadofVDDCpforVDDC) f
/rx,
wewi lluseq, forCv frxt omoni t
ort heav eragecur rent ,The
power di ssipation i s si mply VDDVv ( T) Li nder t his
arrangement .Fi g.4 shows a CMOS pol y
cel lci rcuit[ 5]
composed of mul ti
ple-input NAND,NOR gat es,and 1VI
N
i
nv erters.Thet ot alcur rentdr awnf rom t heVDDsour cei s
thesum ofcur rent srequi redt oswi tcht hel ogicst at esi n 2.
6
i
ndi vidualgates.Thel oadi ngcapaci tanceCLofeachgat e
i
st hesum ofI -
PFwi ri
ngcapaci t
anceandt het otalgat e-to-
subst ratecapaci t
ancesi nt hreef an- outingl ogicgat esof 1.
6
thesamet ype.I ti snont ri
vialtocal cul atet heef f
ect ive
capaci tance inv olv
ed i n swi tching.I n ci r
cui tsi mul ation,
onlywi ri
ngcapaci t
ancei sspeci f
iedandt het hreef an-out 0.
6
gatesar eti
edt oout putnodes.TheSPI CEsi mul ationwas
donewi ththesubci rcuitinFi g.3atT=950C, VDD=4. 5V
12
withR=10 0,CY=1pF,andT=600nS.Thi schoi ce
0.
0 1.
0 2.
0 3.
0 4.
0 5.
0 6.
0
satisfiesthei nequal i
tyR„ Cv>T.Thr eedi f
fer entv aluesof x10—7
rx,10- 510 Ti
me(
s)

I
EEEJOURNALOFSOLI
D-STATECI
RCUI
TS,
VOL.SC-
21,
NO.5,
OCTOBER1986 891

Fi
g,4,ACMOSpoly
cel
lci
rcui
t
usedt
osi
mul
atet
heav
eragecur
rentdr
awnf
rom t
hevol
tagesour
ce.

TAB I
Av
rRA CURRl
E OBTAI
NE W
G1i NT D I
TH

1 70 0 m
t 60 0. m
124 A
10-
5Q 0.
124mA Fi
g.5.I
nputv
olt
agewav
efor
m usedi
nSPI
CEsi
mul
ati
onofFi
g.4
ci
rcui
t.
 thr
oughanexampleinthispaper.Theproposedmethodcanbe
and1070, wer etr
ied.Asshowni nTabl
eIl,themeasur edaver
age usedinanyel
ectr
oni
corel ect
ri
ccircui
tsolongastheinequal
i
ty
currentremai ns const antthroughoutthe t hr
ee cases,which const
rai
ntmenti
onedi
nt hi
spaperissati
sfi
ed.
i
ndicatest hattheproposedappr oachisreliabl
e.Fig.5showsthe
i
nput v oltage wav eform used i n t he si mulati
on. The
correspondi ng out puts are shown i n Fi g. 6 f or both
i
nstantaneousidi d( t)andV)( t).Notethatasexpect edK,(t
)
reachesi tsst eadystatev al
ueatt=T,whi chi stheav er
age
currentdrawnf rom theVI )Dsourceovertheper i
odT=600nS.

V.CONCLUDI
NGREMARKS
I
nthi
spaper
,wepr
esent
edasi
mpl
eci
rcui
tformeasur
ingt
he

aver
agepowerconsumpt i
onini
ntegrat
edcir
cuits.Theuse
of cur
rent-
control
led or v
olt
age-cont
rol
l
ed dependent
sour
ceinconj unct
ionwit
hapar al
lelRCcircui
ty i
eldeda
si
mplesubcircui
tforpowermeasuremenLThi ssubcircui
t
canbeinser
tedintoany

0.
0 1.
0 2.
0 3.
0 4.
0 5.
0 6.
0
Ti
me(
s)

Fi
g.6.SPI CEoutputwaveformsforiddandv p.Her
ethesteady
-
stat
evalueV),(T)repr
esentst
heaveragecur
rentdr
awnfr
om the
volt
agesourceovertheperi
odT.

VLSIci r
cuitmodelwi t
houtcausinganyi nter
ferencewhi let he
ci
rcuitissimul atedwithasi mulat
orsuchasSPI CE.Bypr operly
choosingt het r
ansfergainßi nt
hecasewi thacur r
enbcontrol
led
currentsour ceorthetransferconductancegm i nthecasewi tha
volt
age-cont r
oll
ed currentsour ce,the av erage power
consumpt ionofci rcui
tscanbemeasur edbyr eadingthev olt
age
acrosst hecapaci torattheendoft heperiodT.Thi smet hodi s CONCLUSI
ONANDFUTURESCOPE
si
mpl ey etrendersaccurateresult
sasdemonst rated Fr
om theabov
eobservat
ion,i
tcanbeconcl
udedthat
PFAL t
echni
que i
s ener
gy effi
ci
entas compared to
Conv ent
ional or t r
adit
ional techni
que. The power POWER 7.
9551340Pw 4.
223813Pw
di
ssipati
oni sgreat
lyreducedduet orecycli
ngprocessin RESULTS
PFAL.Whencompar edwi t
ht heprevi
ousy earitcanbe (
conv
ent
ional
)
noti
ced t hatthe powerr esult
s arer educed wit
ht he POWER 4.
6579418Pw 1.
318593Pw
decreasei nt
echnologyused. RESULTS
(
PFAL)
Infuture,researcherscandesi gnotherlogiccircuit
s TABLEIV. COMPARI
SONBETWEENTHEPOWERRESULTSOFNORGATE
l
ikede-multi
plexer,shi
ftregi
steretc.ort
hesameci rcuit
s CI
RCUITS
wit
h di f
ferent technology. The power compar i
son NORGATE PREVIOUSYEAR PRESENT
betweenconv enti
onalCMOSci rcui
tsandadi abati
cPFAL RESULTS RESULTS
CMOS di git
alci r
cuits based on 90nm t echnology at SI
MULATI
ON 1.
8:-vol
tage 1.8V:
-vol
tage
50MHzf requencyisshownbel owi nthetableII. CONDI
TIONS source sour
ce
0.05pF:- 0.
05pF:
-
TABLEII
. COMAPARISONBETWEENPOWERDISSI
PATI
ONOF capacit
ance capaci
tance
CONVENTI
ONALCMOSCI TSANDADI
RCUI CPF
ABATI ALCMOSDI GI
TAL
50MHz: - 50MHz: -
CIRCUI
TS
f
requency f
requency
CI
RCUI
TS CONVENTI
ON PFAL TECHNOLOGY 180nm 90nm
DESI
GNED AL USED
NOT 4.
223813Pw 1.
31859
POWER 9.
1454464Pw 8.
866097Pw
3 RESULTS
Pw
(
conv
ent
ional
)
NOR 8.
866097Pw 4.
13602 POWER 6.
9542012Pw 4.
136027Pw
7 RESULTS
Pw (
PFAL)
2*1 9.
5e-8Pw 7e-9Pw TABLEV.COMPARI
SONBETWEENTHEPOWERRESULTSOF2*1MULTIPLEXER
MULTI PLE (0.00000095) (0.
00000 2*1 PREVIOUSYEAR PRESENT
XER 0007) MULTIPLEXER RESULTS RESULTS
FULL 19.87048Pw 9.
86526 2.5V:
-vol
tage 1.8V:
-vol
tage
ADDER sour
ce sour
ce
SI
MULATI
ON 0.02pF:- 0.
05pF:
-
(SUM) Pw
CONDI
TIONS capacit
ance capaci
tance
FULL 3.04657 50MHz: - 50MHz: -
ADDER 4 f
requency f
requency
(CARRY) Pw TECHNOLOGY
Whencompar edwitht hepr evi
ousy earresult
si tcan 180nm 90nm
USED
observet hatf orthesamesi mul at
ioncondit
ionsast hatof
POWER 2.
2e-
7Pw 9.
5e-
8Pw
previ
ously used [ 1][
2][3][
4] but usi
ng 90nm CMOS
RESULTS (
0.0000022) (
0.00000095)
technologyi nsteadof180nm CMOSt echnologyt hent he
powerdi ssipation i
sr educed as compar ed wi tht he (
conv
ent
ional
)
previ
ousy ears. POWER 2e-8Pw 7e-
9Pw
RESULTS (
0.00000002) (
0.000000007)
TABLEI
II
. COMPARI
SONBETWEENTHEPOWERRESULTSOFNOTGATE
(
PFAL)
CIRCUI
TS
TABLEVI
. COMPARI
SONBETWEENTHEPOWERRESULTSOFFULL
NOTGATE PREVIOUSYEAR PRESENT
ADDERCIRCUI
TS
RESULTS RESULTS
PREVIOUSYEAR PRESENT
SI
MULATI
ON 1.
8:-vol
tage 1.
8V:
-vol
tage FULLADDER
RESULTS RESULTS
CONDI
TIONS source sour
ce
1.
8:-vol
tage 1.8V:
-vol
tage
0.05pF:- 0.
05pF:- source sour
ce
capacit
ance capaci
tance
SI
MULATI
ON 0.05pF:- 0.
05pF:
-
50MHz: - 50MHz :
- capacit
ance capaci
tance
CONDI
TIONS
f
requency f
requency
50MHz: - 50MHz: -
TECHNOLOGY 180nm 90nm
f
requency f
requency
USED
 TECHNOLOGY pp.764- 768.
180nm 90nm [
13]Yasuhi roTakahashi ,Toshi kazuSeki neandMi chioYokoy ama,“ A
USED
Compar isonofAdi abat icLogi casCount ermeasur esagai nstPower
Anal y sisAt t
acks,”inI EEEconf erenceI CSSE, 2010.
POWER 21.
546534Pw 19.
87048Pw
RESULTS [
14]Y.Suni l
Gav askarReddyandV. V. G.S. RajendraPr asad,“ Compar i
son
ofCMOSandAdi abat icFul lAdderCi rcuits,
”inInternat ionalJour nal
(
conv
ent
ional
) ofSci entifi
c&Engi neer ingResear ch, I
SSN2229- 5518, Vol.2, Issue9,
POWER 13.
64454Pw 9.
86526Pw Sept ember -2011.
RESULTS [
15]Moni ka Shar ma,“ Desi gn and Anal ysis of CMOS Cel ls usi ng
Adi abat icLogi c,
”inI nternat i
onalJour nalof Networ ksandSy stems,
(
PFAL-
SUM) ISSN2319–5975, Vol.1,Oct ober-Nov ember2012.
POWER 7.
654049Pw 3.
046574Pw [
16]P.Sr eeni vasulu, M. V.Nar asimha Reddy and G. V.K.
RESULTS Var apr asadSwamy ,
“Desi gnandAnal ysisofLow
(
PFAL-
CARRY)
PowerFul lAdderUsi ngAdi abat icTechni que,”i n
REFERENCES I
nternat i
onal Jour nal of Emer gi ng Technol ogy and Adv anced
[
1] At ulKumarMaur y aandGagneshKumar ,“Adi abat i
cLogi c:Ener gy Engineer i
ng, I
SSN2250- 2459, Volume2, Issue6, June2012.
Ef ficient Techni que f or VLSI Appl icat ions,”i n I nternat ional [
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Conf er enceonCommuni cat i
onSy st emsandNet wor kTechnol ogies, basedLowPowerCPALRi ppl eCar ry
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onalJour nalonRecentandI nnov ationTr endsi n
[
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ante,Jur genFi scher ,Gi useppeI annaccone,and Dor is
onCommuni cat i
onSy stemsandNet wor kTechnol ogies, 2011. Schmi tt
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at ions of t he Power Di ssipation i n
[
3] Rakesh Kumar Yadav , Ashwani K Rana, Shwet aChauhan, Adi abat icLogi cGat es”.
DeepeshRanka,Kamal eshYadav ,“ Adi abat icTechni quef orEner gy [
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”i nI EEE,Pr oceedi ngsofI CETECT, inver terusi ngf orcednMOSappr oach, ”i nInternationalJour nalof
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fi
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[
4] Ar unkumar ,andManojShar ma" Desi gnandanal ysisofMUXusi ng July -2013.
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ct echni queECRLandPFAL, ”i nI nt ernat ionalConf erenceon
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[
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[
6] Ar jun Mi shr a and Neha Si ngh,“ Low powerci rcuitdesi gn usi ng
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7] AbdulSaj i
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