Current Driver with Read-Out HV Protection for
Neural Stimulation
Dmitry Osipov and Steffen Paul Serge Strokov and Andreas K. Kreiter Andreas Schander, Tobias Tessmann,
The Institute of Electrodynamics Center for Cognitive Science
and Microelectronics (ITEM) Brain Research Center
The University of Bremen, Germany The University of Bremen, Germany
Email: osipov@item.uni-bremen.de Email: strokov@brain.uni-bremen.de
Abstract—This paper presents a current driver with a novel
high voltage (HV) switch schematic for the use as a protective
switch for recording circuits during the stimulation sequence. The
current driver can source and sink currents of amplitudes up to
±8.2 mA with HV tolerance from 30 V up to 120 V. The mismatch
between the sourced and sinked current does not exceed 20 µA.
The inter pulse current is no more than 60 pA. The output HV
compliance depends on the HV supply voltage with maximum
value of the 120 V. The proposed HV switch also tolerates the
voltage difference up to 120V between its terminals. The chip
was fabricated with AMS HV 0.35 µm CMOS technology.
I. I NTRODUCTION
Biphasic current stimulaton circuits with the epicortically
placed electrodes are widely used for brain stimulation. One
prospective application of the neural stimulation is the vision
restoration. It is known that the electrical stimulation of the suf-
ficient amplitude causes the light sensations called phospenes.
The stimulation with the electrodes placed epicortically is less
invasive, but requires currents on the order of a few mA [1],
[2]. Due to the relatively large electrode-tissue resistance up to
several kΩ [3] and the current amplitudes needed to activate
neurons up to several milliamperes high voltage (HV) ouput
interfaces should be used. Recently reported neural stimulators
utilized supply voltages of 15-90 V [4], [5], [6].
The typical stimulation and readout interface is shown in
Fig.1 [7]. The parts of the systems functionality, which could
be realized with the proposed current driver ASIC, are marked
in color. The read-out should be done with an external low
noise amplifier. However, the proposed driver is capale of
protection of that amplifier from high voltage swings arising
at point A.
During the stimulation sequence the voltage at point A can
swing from ground to VDDH, so the HV protective switch
is needed to protect the low voltage (LV) neural amplifier.
Although [7] utilizes a single HV transistor as protective
switch, this is only possible, if the technology allows the
gate-source voltage of the HV-transistor to reach VDDH. For
most of the HV CMOS technologies the acceptable gate-source
voltage can not exceed several volts, while the drain-source
voltage can reach tens and hundreds of volts.
Therefore, for higher HV supply voltages the need of HV
protective switches arises for controllable gate-source voltages
not exceeding the technology related safe region. Some circuit
solutions have been reported before [8], [9]. The limitation
978-1-5090-1095-0/16/$31.00 ©2016 European Union
Walter Lang
The Institute for Microsensors,
-Actuators and -Systems (IMSAS)
The University of Bremen, Germany
Email: aschander@imsas.uni-bremen.de
VDDH HV Stimulator LV low noise neural
amplifier
Proposed Driver
HV Protection VDDH/2+VDDL/2
Switch
Φa A to ADC
Ztissue VDDH/2-VDDL/2
Φc VDDH/2 Record/Stimulate
Fig. 1. Neural stimulation and recording interface
of the over-voltage protection control loop presented in [8] is
that the control loop creates a current path from the switch
input node to the ground, though drawing some current from
point A during the recording phase. This can lead to the non-
compensated current flowing to the tissue. The HV-switch in
[9] allows the gate-source voltage difference of HV transistor
to rise up to VDDH/2, which is not acceptable for higher
values of VDDH.
The application of a HV-switch is not restricted to the
neural stimulation, but can also be found in the area of 3D
ultrasound imaging systems [10], [11], [12] or HV Battery
Management systems [13]. The HV-switch proposed in [10]
requires the half-scale control signals, while the proposed
circuit only uses LV control signals. The zero statical power
solution provided in [11] can also not be applied directly
because of the need of additional gate-source overvoltage
protection for off-state transition.
The effective control circuit which completely isolates
switch input nodes while providing over-voltage gate protec-
tion of HVMOS transistor. The HV compliant output interface
proposed in this paper provides the highest HV compliance
among reported in range from 30 up to 120 V.
The rest of this paper is organized as follows: section II
introduces the HV protective switch used for the proposed
current driver. Section III provides the description of the HV
compliant output interface. Measurement results are given in
section IV, and, finally, section V concludes the paper.
 HV IO VDDH
VDDH

LV control
+
- Mp0 Mp2
floating VTH0 HF (wl)p w
()
20 l p
driver HV IO MPL Mp1
B
VTH1 (wl)p/2
MP0
Mhps
floating Ibias to HV switch ΦA(HV)
driver transistor Iin/2

to electrode
- VSS
+
LV
control VDDL VDDL
Iin
HV IO Iin/2 Iin/2
ΦC
Fig. 2. HV switch concept and floating driver schematic.
Mhn0 Mhns
Mnk0 Mnk
(wl)n (wl)n/2 (wl)n/2
control,

3 Mn1 Mns
and voltage LV
V

Mn0 w
()
0 (wl)n 20 l n
HV switch input

HV transistor, V

100 HV-IO VSS

HV switch transistor
at gate of

gate voltage
60
Fig. 4. HV current driver schematic.
HV switch voltage

20
transistor

0 the bias current, which is restricted by the HV-switching

Vgs, V

-1.5
Fig. 3. Floating driver simulated transient waveform
II.
The circuit, which implements the HV-switch function
(marked in Fig.1 in yellow), is shown in Fig.2. The HV IO
pins of the switch should be set between A node and input
of the LV low noise amplifier in Fig.1 to protect it from HV
swings.
HV switch PMOS transistors are implemented in isolated
N-Tubes with their bulk nodes tied to their sources. The drain
to drain connection of two PMOS HV transistors at node
B in Fig.2 eliminates the opening of both parasitic diodes
independent from HV input-output potentials of the switch.
In the chosen HV process the safe gate to source voltage of
HV PMOS transistor is limited to 1.2 V, so the floating drivers
should be used to guarantee the operation of the HV switch
transistors in the safe region.
The schematic of the proposed HV floating driver is also
shown in Fig.2. The HV PMOS transistor MP0 acts as a
source follower. While the LV control switch is closed the
current is shared between HV transistor MP0 and diode
connected LV isolated transistor MPL. The output voltage of
the floating driver is about (VHV IO +|VT H0 |−|VT H1 |), where
VT H0 is the threshold voltage of HV PMOS and VT H1 is
the threshold voltage of LV isolated PMOS transistor. The
|VT H0 | − |VT H1 | ≈ −1.3 ensures the safe gate-source voltage
of the switching HV PMOS. The switching HV PMOS is on.
While the LV control switch is open, all the current at node HF
flows through MP0, ensuring the output voltage of the floating
driver is about VHV IO + |VT H0 |. The switching HV PMOS
is off. This behavior is illustrated in Fig.3. The bottom graph
shows the HV switching PMOS transistor gate-source voltage
(VHV IO − VHF )
The power consumption of the switch is determined by
transistor size and the desired switching time of the switch.
4 8 12 16
time, ms For the current switch design the bias current was set to
40 µA. Because of the weak dependence of the setting time
(ts ≈ 4µs) from the bias current near the selected value,
the bias current source is implemented as simple polysilicon
resistor and current mirror.
HV SWITCH CONCEPT
III. HV CURRENT DRIVER
The simplified schematic of the HV output interface is
shown in Fig.4. The input current is amplified by a factor
of 20 and copied to the output node. If the switch ΦA is
closed and the switch ΦC is open, the current driver sources
the amplified current to the load, for a vice versa switch
configuration, the current driver sinks current from the load.
The level shift of the low voltage control signal ΦA switch is
implemented as in [14]. So, all driver’s control voltages are
in the low voltage domain. Output current mirrors utilize the
accurate active-feedback topology [15]. HV-transistors are only
used as shielding devices. The circuit can operate with VHH
voltages from 30 V up to 120 V.
IV. M EASUREMENT R ESULTS
A. Stimulation with the electrode-tissue model
The proposed current driver was implemented using the
AMS 0.35µm 120 V process. Fig.5 shows the test die photo-
graph and the measurement setup. The 12 bit current sourcing
DAC of C8051410 Silabs microcontroller was used to drive
the reference current input of the chip. The electrode-tissue
model describes the PEDOT electrodes of 560 µm diameter in
the phosphate buffered saline (PBS).
The Fig. 6 shows a train of 5 biphasic current pulses, ap-
plied to the electrode-tissue model. The stimulation frequency
was set to 1 kHz, the anodic and cathodic current pulses have
the duration of 100 µs and the amplitude of 4.1 mA. The
interpulse delay between anodic and cathodic phases is equal
to 10 µs. The baseline at the capacitor recovers after 115 µs
after stimulation.
 TABLE I. S TATE OF THE ART (C URRENT D RIVERS )

capacitor, mV electrode-tissue Current, mA

Stimulation
4
[16] [17] [18] [19] [20] [21] This 0
work
Year 2012 2013 2013 2015 2015 2015 2016 -4
N. of channels 16 1 1 8 16 4 2

Voltage over Voltage over

Stim. Resolulion, 8 5 5 5 ext. ext. ext. 4

model, V
bits DAC DAC DAC
M AX 0
|Iout |, mA 0.525 1.5 10 0.3 1.8 - 8.2
Istim /Isteady 0.4 - - 0.2 40 - 42.6 -4
HV Compliance, V 10 30 13 17 11.5 18 30-120
Process (µm) 0.25 0.18 0.18 0.35 0.18 0.6 0.35 80
Ch. Area,mm2 0.33 0.36 0.14 2.21 0.17 0.02 0.38
Verification Meas Sim Sim Meas Meas Meas Meas 40
0

C8051F410 MCU 0 1 2 3 4 5
voltage source/ time, ms
GPIO 12 bit Digital ammeter

capacitor, mV
80

Voltage over
Current DAC VDD VDDH VDDH/2
ΦA ΦC Iref
40 115 µs
10 µF 1 MΩ
ch0 ch1 HV ΦA ΦC Iref 0
Sw
Proposed HV 0 100 200 300 400 500
1 mm

Current Driver 700 Ω time, µs

VDD VDDH Istim
0.38 mm Electrode-tissue
model Fig. 6. Biphasic stimulation with anadic and cathodic currents equal to each
other (|IA | = |IC | = 4.1 mA), the pulses widths are equal to TA = TC =
100 µs, interpulse width is equal to TI = 10 µs, stimulation frequency is
Fig. 5. Measurement setup and die photograph equal to FS = 1 kHz.

capacitor, mV capacitor, mV electrode-tissue Current, mA

Voltage over Voltage over Voltage over Stimulation
The current amplitude of the balancing phase can be 4
2
lowered if the neuron activation is not desired in that phase. In
0
that case the duration of that phase has to be longer to balance -2
the charge. The fig. 6 shows a train of 5 biphasic current pulses
with the stimulation amplitude of 4.86 mA and the balancing 4
model, V 2
amplitude of 1.6 mA ((|IA | = 3|IC |). The baseline at the
capacitor recovers after 580 µs after stimulation. 0

B. HV protection capabilities 80
40
To test the HV protection capabilities of the proposed
0
switch the 700 Ω resistor of the electrode tissue model was 0 1 2 3 4 5
changed to the 4.1 kΩ. The AIN pin of the switch was also time, ms
80
connected to the electrode-tissue model. During the off-state
580 µs
of the switch, the electrode-tissue model was stimulated with 40
the biphasic current pulses (|IA | = |IC | = 8.2 mA). After the
end of stimulation the switch was closed. The pulses with the 0
amplitude of 8 mV and the duration of 10 µs were generated 0 200 400 600 800
time, µs
at the VDDH/2 output of the voltage source. The measured
pulses at the AIP pin of the switch are shown in Fig.9. The Fig. 7. Biphasic stimulation with anadic and cathodic currents not equal to
switch can effectively protect the recording part of the system each other (|IA | = 3|IC | = 4.8 mA), the pulses widths are set to equalize
from HV swings up to 120 V providing the off-isolation of -34 the anodic and cathodic charges TA = 3TC = 150 µs, interpulse width is
dB, which is completely sufficient for the damage prevention equal to TI = 10 µs, stimulation frequency is equal to FS = 1 kHz.
of the recording part of the neural stimulation system

C. Current Driver characteristics
The mismatch between anodic and cathodic currents (Fig.8)
were measured for two different resistive loads: 700 Ω and
4.1 kΩ. The nonlinearity of the input current amplification is
shown in Fig.8. The leakage current does not exceed 60 pA.
V. C ONCLUSION
The HV compliant current driver for the neural stimulation
has been proposed. The driver amplifies the input reference
current by a factor of 20. The HV compliance is within
{15..120 V} and depends on the HV supply voltage. The
current driver can sink and source currents of amplitudes up to
8.2 mA. The relation of sinked or sourced currents to steady-
state current is equal to 42. The interpulse leakage current does
not exceed 60 pA. The comparison with the state of the art
current drivers is given in table I.
The driver is implemented as a two channel chip in AMS
HV 0.35 µm process. One of two channels can be configured
for a safe read-out using a HV switch, which protects the low
voltage read-out electronics from large voltage swings during
the stimulation sequence. The switch provides the Off-Isolation
of -34 dB. The comparison of the proposed switch with state
of the art is given in table II.
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