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MOS 2 Power-Transistor: Features Product Summary
MOS 2 Power-Transistor: Features Product Summary
IPI09N03LA, IPP09N03LA
®
OptiMOS 2 Power-Transistor
Product Summary
Features
V DS 25 V
• Ideal for high-frequency dc/dc converters
R DS(on),max (SMD version) 8.9 m:
• N-channel
ID 50 A
• Logic level
• Excellent gate charge x R DS(on) product (FOM)
• dv /dt rated
T C=100 °C 46
I D=50 A, V DS=20 V,
Reverse diode dv /dt dv /dt di /dt =200 A/µs, 6 kV/µs
T j,max=175 °C
Thermal characteristics
Static characteristics
V DS=25 V, V GS=0 V,
Zero gate voltage drain current I DSS - 0.1 1 µA
T j=25 °C
V DS=25 V, V GS=0 V,
- 10 100
T j=125 °C
V GS=4.5 V, I D=30 A,
- 12.1 15.1
SMD version
V GS=10 V, I D=30 A,
- 7.4 8.9
SMD version
Gate resistance RG - 1 - :
1)
Current is limited by bondwire; with an R thJC=2.4 K/W the chip is able to carry 64 A.
2)
See figure 3
3)
T j,max=150 °C and duty cycle D <0.25 for V GS<-5 V
4)
Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm 2 (one layer, 70 µm thick) copper area for drain
connection. PCB is vertical in still air.
Dynamic characteristics
Q sw V GS=0 to 5 V
Switching charge - 5.5 7.9
V DS=0.1 V,
Gate charge total, sync. FET Q g(sync) - 9 12 nC
V GS=0 to 5 V
Reverse Diode
V GS=0 V, I F=50 A,
Diode forward voltage V SD - 0.98 1.2 V
T j=25 °C
V R=15 V, I F=I S,
Reverse recovery charge Q rr - - 10 nC
di F/dt =400 A/µs
5)
See figure 16 for gate charge parameter definition
70 60
60
50
40
40
P tot [W]
I D [A]
30
20
20
10
0 0
0 50 100 150 200 0 50 100 150 200
T C [°C] T C [°C]
1000 10
limited by on-state 1 µs
resistance
0.5
100 10 µs
1
Z thJC [K/W]
0.2
I D [A]
100 µs
DC
0.1
0.05
1 ms
10 0.1
10 ms 0.02
0.01
single pulse
1 0.01
0.1 1 10 100 010-6 0 -5
10 100-4 10-3
0 10 -20 10-10 10 0 1
V DS [V] t p [s]
80 30
3.5 V 3.8 V 4.1 V 4.5 V
3.2 V
10 V
70 4.5 V
25
60
20
50
R DS(on) [m:]
4.1 V
I D [A]
40 15
3.8 V
30
10
3.5 V
20 10 V
3.2 V 5
10
3V
2.8 V
0 0
0 1 2 3 0 20 40 60 80 100
V DS [V] I D [A]
100 70
90
60
80
70 50
60
40
g fs [S]
I D [A]
50
30
40
30
20
20
10
175 °C
10 25 °C
0 0
0 1 2 3 4 5 0 20 40 60 80
V GS [V] I D [A]
18 2.5
16
14 2
12 200 µA
R DS(on) [m:]
98 % 1.5
V GS(th) [V]
10
20 µA
typ
8
1
6
4
0.5
0 0
-60 -20 20 60 100 140 180 -60 -20 20 60 100 140 180
T j [°C] T j [°C]
10000 1000
25 °C
IF [A]
25°C 98%
100 Crss 10
1
10
0.0 0.5 1.0 1.5 2.0
0 5 10 15 20 25 30
VSD [V]
V DS [V]
100 12
15 V
10
25 °C
100 °C 5V
150 °C
20 V
8
V GS [V]
IAV [A]
10 6
1 0
1 10 100 1000 0 10 20
t AV [µs] Q gate [nC]
29
V GS
28
Qg
27
26
V BR(DSS) [V]
25
24
V g s(th)
23
22
Q g (th) Q sw Q gate
21
20 Q gs Q gd
-60 -20 20 60 100 140 180
T j [°C]
Package Outline
P-TO263-3-2: Outline
Footprint Packaging
Dimensions in mm
P-TO262-3-1: Outline
P-TO220-3-1: Outline
Packaging
Dimensions in mm
Published by
Infineon Technologies AG
Bereich Kommunikation
St.-Martin-Straße 53
D-81541 München
© Infineon Technologies AG 1999
All Rights Reserved.
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