Plan

Circuits logiques

Représentation des nombres

Unité Arithmétique et Logique

Time and memory

Contrôle et jonction des composants

Evolution des ordinateurs – Historique

Un microprocesseur simple

Programmation d’un microprocesseur

Système complet

Les microprocesseurs actuels

Exploitation de la performance des microprocesseurs
 Time
0 0 1 0 1 1 1 0 0/1 T=cycle
t=0 t=0 t=0 t=0
y3 x3 y2 x2 y1 x1 y0 x0
r3 r2 r1 r0
+ + + + Clock
signal
t=8 S3 t=6 S2 t=4 S1 t=2 S0
1 0 0 1
01 0 0 01
clock
t=8 1 0 0 1

Synchronization:
• Wait for the output of all adders to be valid before propagating result
• Estimate computation time to find appropriate delay

Insert « barriers » to synchronize outputs
→ Control of « barriers »: clock, periodic signal
 Notion de Temps
0 0 1 0 1 1 1 0 0/1 T=cycle
t=0 t=0 t=0 t=0
y3 x3 y2 x2 y1 x1 y0 x0
r3 r2 r1 r0
+ + + + Clock
signal
t=8 S3 t=6 S2 t=4 S1 t=2 S0
1 0 0 1
1 0 0 1
clock
t=8 1 0 0 1

Synchronization:
• Wait for the output of all adders to be valid before propagating result
• Estimate computation time to find appropriate delay

Insert « barriers » to synchronize outputs
→ Control of « barriers »: clock, periodic signal
 Notion de Mémorisation
0/1 T=cycle

0 0 1 0 1 1 t=2 10 00
t=0 t=0 t=0 t=0
0 0 1 0 1 1 1 0
y3 x3 y2 x2 y1 x1 y0 x0
r3 r2 r1 r0
+ + + +

t=8 S3 t=6 S2 t=4 S1 t=4

t=2 S0
1 0 0 1
0
10 0 00 0
1
clock
t=8 1 0 0 01

Hold inputs during computation → memory
 Memory
0/1 T=cycle

0 0 1 0 1 1 t=2 10 00
t=0 t=0 t=0 t=0
0 0 1 0 1 1 1 0
y3 x3 y2 x2 y1 x1 y0 x0
r3 r2 r1 r0
+ + + +

t=8 S3 t=6 S2 t=4 S1 t=4 S0

1 0 0 1
0
1 0 0 1
0
horloge
t=8 1 0 0 1

Maintenir les entrées pendant la durée du calcul
→ mémorisation.
How To Implement A Memory Circuit ?
C
C X Z(t) Z(t+ ∆t)
0 0 0 0
0 0 1 1
0 1 0 0 X Z
0 1 1 1
1 0 0 0 ∆t: propagation time
1 0 1 0
1 1 0 1
1 1 1 1

Z (t + ∆t ) = C ' .Z (t ) + X .Z (t ) + C. X

Barrier: input X, output Z, control using clock C:
• C=0: memory → Z(t+∆t) = Z(t)
Z(t +∆t)
• C=1: propagate information → Z(t+∆t) = X

Loop: send output to input → memory
CX Z(t)
 Latches
S R Q Q+
S q 0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 0
Q 1 0 0 1
R 1 0 1 1
1 1 0 d
Latch SR 1 1 1 d

Memorization circuits used as “building blocks”

Different types of latches (number of control
signals and behavior)

SR= Set/Reset: memorize or set 1/0.
 Latches
C D C D Q Q+
S 0 0 0 0
q
0 0 1 1
0 1 0 0
0 D
1 Q
1 Q1+
1 0 0 0
Q
1 0 1 0
1 1 0 1
R
1 1 1 1
Latch D

Latch D: Delay, memorization circuit only

Adding clock:
• C=0 → memorization
• C=1 → open
 Flips-Flops

Operators/Computations usually
in sequence

A latch can store a result but not Clock + +
truly separate two operators
0 1
1-bit adder delay 0 10 D
0 1

+
0
1
1
0 D
01
 Flips-Flops
Flip-Flop D

Latch D Latch D Latch D

1 01 10 00
1 1

Clock

Connect two latches, open on opposite clock

phases:
⇒ The signal can only go through one of the two
latches (≈ air lock).
 W
C Register
X3 X2 X1 X0

Z3 Z2 Z1 Z0

n flip-flops D in parallel

Storing one word

Read/Write; signal W=1 → Write
 Register Bank
4
Data to write 4
4
R0
w 4 4
W 4
R1 Read data 1
3 w
Write register 4
Read data 2
3 4
Read register 1 4 R7
3 w
Read register 2
k=3

Small 2k – word memory

Usually, at least 1 write port, 2 read ports

Access through register number ~ address (k bits).