Analyze the technique to detect multiple

scan chain failure

Jhanvi Ravi Sheth, Rahul Mehta, Bhavesh Soni Mtech,EC
VLSI, Ganpat university
Ganpat university, Ganpat Vidhyanagar, Mehsana-Gozaria Highway, Kherva, Mehsana-384012
jaahanviseth24@gmail.com bhavesh.soni@ganapatuniversity.ac.in
E-infochips,2,Aryan Park Complex,Nr.shilaj Railway Crossing,Thaltej,Ahmedabad,Gujarat – 380054
rahul.mehta@eitra.org

Abstract : Scan chain based testing plays a major role in yield

enhancement of the chip. In scan based testing of the device we
are converting all the sequential elements of the design into scan-
able elements. But it is also possible that chain itself can drive
faulty data and that proves that the scan chain itself can be
subject to defects as it acquires significant area of total chip.
Hence nowadays it is must an engineer should do diagnosis of
scan chain failure. So,In this paper we have run diagnosis in
ATPG only which is useful to detect multiple chain failure and
improves detection ability resolution of the design.

Keywords : Scan chain, Test pattern generation, ATPG diagnosis,

Chain masking, Yield Enhancement.

I. INTRODUCTION Fig.2 test pattern generated by ATPG tetramax tool

A. Scan-chain insertion : Scan test is able to convert sequential B.
elements into scan-able elements to observe and control intended node
of the design. Fig.1 shows a diagram of scan chain testing. By using
scan chain insertion we can test the original design. It is absolute that snapshot of a pattern which we have done for loading and
by insertion scan logic into the design overall area overhead will be
more.
Fig.1 Scan chain insertion
Basically, there are three mode of operation shift, normal, capture and
we have here 2 scan cells which has 1 combinational logic circuit
which is able to drive scan flops while scan operation and we have
data and scan inputs to the scan flops. SE input is used to select
between data and test input. There are SI and SO pin which is for Scan
input and Scan output respectively.
Chain insertion is done by Synopsis DFT-compiler tool.[5]
Test pattern generation : It can be generated by
tool depending on the structure of design and fault models
based on shortest or longest scan architecture. Fig.2 shows a
unloading binary data to or from the scan cells.[6]
C. Fault simulation : It is the first and foremost step of
failure analysis flow in any diagnosis technique flow. This
step helps to determine a particular fault/defect by localizing
the area,net or pin of the design. In ATPG diagnosis it
requires external failure log file of ATE tester and the failure
log file generated from ATPG simulation process. It will
compare both of the patterns like which pattern is failing and
which has been passed at which vector and which type of fault
at which pin of the design. For this we have done iterative
analysis in ATPG diagnosis process. After this is done ATPG
generates the target pattern which will be shorter in length
but will be able to detect the fault within specific area of the
chip.[6]
 successfully passing while simulating pattern and CPU time
is 52.583 seconds which is able to detect 2 type of stuck-at
faults.
Hardware Assisted Technique To Improve Test
Test Hardware Patterns Volume

Targeted Patterns A technique is invented earlier to modify the flow of

Failure log file
commercial ATPG tool to modify the scan chain selection
logic used to improve the volume of test pattern generation
for detecting the multiple chain failure on different scan cells.
ATPG files ATPG Diagnosis

Fig.3 Iterative Diagnosis Flow in ATPG tool [3]

The targeted pattern generated from diagnosis flow can easily merge
with existing hardware and best part is no translation of files are
required as it is already in standard pattern format ex. STIL ( Standard
test interface language). Flow which is in fig.3 can be performed until
the intended result come. ATPG tool will perform mapping the failure
data log of both while doing iterative analysis and it can helps us to
lead the cause of defect/fault within a certain pin of the chip.[3]
Fig. 6 Multiple chain failure[4]

As shown in fig. 6 it is clear that we are having multiple scan

flops are driving faulty data value and chain 1 and chain 3 are
having failure and the scan flop no. 2 is the common in both
of the chain which is having faulty value. This can lead to
Fig.4 Failing scan pattern while doing simulation of patterns multiple chain failure and if both chains have faulty value at
same no. of scan cell then it is possible that tool may not be
As we can see from fig.4 it is clearly visible that pattern no.11 while able to identify which flop is failing and to overcome the chain
unloading the data from pattern no.10 has stuck-at faults at scan cell masking logic has been invented earlier here is the flow of
3,4,5,8,9,11 at vector 37 and onto the pin test_so1. This result can be both normal chain selection flow and invented chain selection
achieved while validating patterns generated from ATPG tool.[4] logic flow.[4]
Normal chain selection flow is able to detect the failing chains
but here we are more focused on to diagnose the chain failure.
So,the invented scan chain selection logic is able to diagnose
the scan chain failure. For this we are measuring the frequency
of a scan chain masked/observed. By balancing the masking
and observation of scan chains they are improving the
probability that some failing scan chains are observed while
others are masked for some scan patterns. Invented flow is
used to mask which chains are driving X- state with nominal
increase in no. test patterns.[4]

Fig.5 Diagnosis result achieved from ATPG diagnosis for

compression

fig.5 shows a diagnosis result got from ATPG diagnosis tool it can be
seen that we have total 96 scan patterns and out of them 86 are
 Test cycles 1177 2110

No. of passing 1 86
patterns
No. of failing 7 10
patterns
Detection 0.03% 0.06%
ability
Resolution
Increased patterns 0.01% 0.03%
resolution
Table 1. Simulation result
data for stuck-at faults Fig. 7 Normal chain selection flow [4]
Here it can be observed that without compression we got bit
high simulation time and in compression we are having less
simulation time having 0 number of mismatches.

CONCLUSION
In this paper , we reviewed the detection capability of
produced test patterns with space compactors to compact the
test data. This is capable for improving diagnosis resolution
as compared to non-compressed technique as shown in table
1. In future one can work on the same technique to make the
process as much faster as possible.

REFERENCES

[1] K. K. Saluja and M. Kiupovsky, “Testing computer

Fig. 8 Invented chain selection logic [4]
EXPERIMENTAL RESULT
First to do scan insertion we have used DFT compiler by synopsis and
to generate test vectors we have used Tetramax-ATPG tool by
synopsis and to validate test vectors we used VCS-MX tool by
synopsis. Diagnosis is done in ATPG tool only and we achieved
satisfactory result for diagnosis of scan chain failures. For this we
injected faults into design and observed such results. To do this we
manually generated the failure.log file of ATE external tester and it
will map the failing scan patterns with internally generated scan
patterns.
hardware through data compression in space and time,”
Proc. ITC, pp. 83-88, 1983.
[2] I. Hamzaoglu and J. H. Patel, “Reducing test application
time for full scan embedded cores”, VTS 2000, pages
369– 375.
[3] Eric Barbian and Rommel Estores, “ATPG testing and
Diagnosis implementation in FA for fast and efficient
iterative Diagnosis and Fault isolation”.
[4] Xun Tang, Ruifeng Guo, Wu-Tung Cheng, Sudhakar M.
Reddy, “Improving Compressed Test Pattern Generation
for Multiple Scan Chain Failure Diagnosis”.
[5] Synopsys DFT-compiler userguide.
[6] Synopsys Tetramax-ATPG userguide. [7] Synopsys VCS
tool userguide [8] “VLSI Test Principle” DFT book.

Case 1 (Without 2 (With Compression )

Compression )
No. of Scan chain 8 96

No. of test vectors 391 702

Simulation time 117700000 ps 211000000 ps