Analog Lab (EE2401)

Experiment 5 : Voltage controlled oscillator

EE19BTECH11041,
Srijith Reddy Pakala
Department of Electrical Engineering
IIT Hyderabad
March 4, 2021

1 Aim
Understand the operation of a schmitt trigger based oscillator.

Design a variable frequency oscillator controlled by voltage.

Schmitt trigger

A Schmitt trigger is a comparator circuit with hysteresis implemented by applying posi-

tive feedback to the noninverting input of a comparator or differential amplifier.

2 Problem statement
1. Design a schmitt trigger based oscillator with the following specifications:

. • Oscillation frequency: 10 kHz.

. • Hysterisis width for schmitt trigger: Around 20 % of the opamp peak-to-peak output
swing.
. • LF347 opamp with +5V/-5V dual supply.

1
2. Below is a modified oscillator with a control voltage (VC ) input to vary the oscillation
frequency. Here, VC decides the rate of integration and hence controls the output frequency.
Transistor Q1 introduces an inversion, therefore the schmitt trigger is also inverting. RB is
for controlling the base current of Q1 and D1 protects the transistor from breakdown during
negative swing. :

. • Analyze and calculate component values assuming Q1 to act like an ideal switch.
. •frequency 10-15 kHz for VC ranging from 4-6 V.
. • Generate VC /2 from VC using a voltage divider.
. • Q1 : 2N3904, D1 : 1N4148
. • Plot frequency vs VC characteristics. Is it expected?

3. Change R or C to obtain new frequency range of 100-150 kHz for the same VC range as
above. Plot frequency vs VC . Is it linear? Explain. In reality Q1 doesn’t act like an ideal
switch. It has a saturation voltage of around 0.2 V. This can cause deviation in the expected
duty cycle. Modify the circuit in Problem 2 to compensate this effect. You can assume a
matched transistor is available.

2
3 Analysis and simulation
Question1
0
K2
Mw

A
V
Virhual
Shott

20 . f peak
seriss width ts
Cven
eak
opamp

Vo t+ V,P
Vo

op-omppe

Ve=0, 2V, s nystevisis widh

A
Vant R V,P
V0

V Vowt R

3
, op-cmp peak P-appek R
5

V-Vaudt
RC
et us Sppse Veo t t = o ano

4hsukure V 3.5-Vge =Vp

han
VauaeR-R Vatdt
RC

As tha Copodtor chages Ve lbetone

ert
RiRC
R
( Now h nckuol Cycl stosk s
hen Vas-Vp
t
Ve-VpR, R. Vpot R-Vp
RC RC

RR

4 ) = aNR

At-4-+1-2RC R

ere Atis hall h Tme porioo

T 2At =
4RCR 4RC
R

4RC
Schematic

Circuit schematic

6
 Output

Vout

• As we can see the frequency is 9.4KHz which is deviated from the expected value 10KHz
and duty cycle here is 50.0157%.

• The may be accounted by the non ideal characteristics of opamp we used .

7
Question2

0
K2
Mw

A
V
Virhual
Shott

20 . f peak
seriss width ts
Cven
eak
opamp

Vo t+ V,P
Vo

op-omppe

Ve=0, 2V, s nystevisis widh

A
Vant R V,P
V0

V Vowt R

8
 Ve VoudR .V
R+Ra
20. peak hy stfeai
Sirnila uSing

5
Rt3
3 4R

V-NVeJ Ve0 Vaa?0

2RC

CO
V,-t Ve Ve o ,Vot
RC
s
Ve>0 and cap
Now t's Socoy ad t =o
9 Vsia Vp
unchrged.

Ve Vou R Vc dt-Ve
2
R+ RC

AS chaqeS Vev ond attat, 0

CoP
V Voe R
- -)+
Rc RtRs
 RC-R 2Vt R

VR)
Noxd At A Ne <0 > Va-V
cyclus wr staak

be tat ouich Ve = o uohunVout -V

tt

VeVt R Ve e
2R.C
RitR3
- VR
P+R3

Ne
(-41)Ve 4RCV Ra
RtP3

Al T
2
Ve Rt R

ERC'R SRCVP
T 5V
CRtR) V
 SVe
8RCVp
Yom Simulation Vp3.5V
Now
eed
aV

5x4 0k1z

8RC (3.
35.14 nF
R 1K, C

Now Loming Re Re Contmls T

bakdown.
at , Omd mihtrin D om

Sueh that Di
R shodd be iqus
S h tht
is Sae m lovoex enona

is in Saaton i.e I

V..-0.+ R
y p i c l y

Ot

2R Rg<lUvk

we choo Rg loR
 Schematic

Circuit schematic

• To find frequency as VC varies we have used above statements and also for duty cycle.

12
 f as VC varies

f Vs VC

• We can see that the frequency is increasing linearly w.r.t to VC .

• But similar from the first question the frequency here is also deviated from the expected
values.

• The duty cycle here is 50.3009%.

13
Vout at VC =5V

Vout Vs time(ms)

14
 Voltage at collector of Q1

VCollector Vs time(ms)

• From the above plot the saturation voltage is 30mV which is quite low and good for the
circuit.

15
 Question3
Schematic

Circuit schematic

• We have changed R and C such that frequency range is 100KHz to 150KHz.

16
 f as VC varies

f Vs VC

• We can see that the frequency is increasing w.r.t to VC but non-linear.

• The frequencies observed is very much deviated from the expected value,the reason is
that opamp output cannot change faster than slew rate.

• The duty cycle here is 0.511321% at VC =6V.

17
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tor has
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-Tr Ncn(Vn-V.a

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Ve-a
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R
Vc-Vn = Vn-Vsat

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+

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V= 3Y Vat+(+1)YeVc

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Since we Ue Con

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V =Ve+ Ve

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Schematic

Circuit schematic with compensation

22
 Vout at VC =4V

Vout Vs time(ms)

• Duty cycle observed here is 0.513224%.

• There is not much of a difference in duty cycle here because of low saturation voltage
i.e 30mV.It could be helpful if our saturation would have high.

23
24