UGRD-CS6201A Architecture and

Organization (MIDTERM QUIZ 2 TO

MIDTERM EXAM)

Simple computer, like most computers, uses

machine cycles.
Select one:
True
False

Which of the following is NOT an addressing mode?

Select one:
a.
Home Addressing

b.
Indirect Addressing

c.
Direct Addressing

d.
Immediate Addressing

It can be changed either conditionally or unconditionally

Select one:
a.
Condition Branch

b.
Sequence

c.
Unconditional Branch

d.
Branching

It changes the sequence of execution irrespective of condition of the results

Select one:
a.
Sequence

b.
Conditional Branch

c.
Unconditional Branch

d.
Branching

In which phase is the instruction is executed and the results are placed in the appropriate
memory location or register?

Select one:
a.
Fetch Phase

b.
Decode Phase
 c.
Circular Phase

d.
Execute Phase

Indirect Addressing can be nested, multilevel, cascaded

Select one:
True
False

What is the meaning of branch instruction?

Select one:
a.
Changes the sequence of execution

b.
Changes the normal sequence of execution
c.
Changes the sequence only

d.
Change either conditionally or unconditionally

What are the 4 conditional codes?

Select one:
a.
CZAN
b.
NZVC

c.
VBCA
d.
NAVR

Address field contains address of operand

Select one:
True
False

A cycle is made of how many phases?

Select one:
a.
8

b.
5

c.
3

d.
4

You need to use ______ to add numbers

Select one:
a.
Branching

b.
Sum

c.
Loop

d.
Sequence

A type of branch that changes the sequence only when certain conditions are met
Select one:
a.
Sequence Branch

b.
Conditional Branch

c.
Model Branch

d.
Unconditional Branch

During the decode phase, the instruction in IR is

coded and the required operands are fetched from
the register or from memory.
Select one:
True
False

The cycle is made of three phases

Select one:
a.
fetch, decode, execute

b.
fetch, code, execute

c.
stretch, decoded, execute

d.
write, decode, exectue

The ________ keeps track of information about the results of various operations for use by
subsequent conditional branch instructions

Select one:
a.
Head

b.
 ALU

c.
Processor

d.
Flags

The process continues until the memory reaches a HALT instruction

Select one:
True
False

Which is TRUE about indirect addressing?

Select one:
a.
Very small address field needed

b.
Limited memory space

c.
none of the above

d.
Memory

cell pointed to by address field contains the

address of (pointer to) the operand
cell pointed to by address field contains the
address of (pointer to) the operand
During the execute phase, the instruction is
executed and the results are placed in the
appropriate memory location or the register.
Select one:
True
False

It is pointed to by address field contains the address of (pointer to) the operand
Select one:
a.
Processor

b.
Memory Cell

c.
ALU

d.
CU

Which is NOT TRUE about Direct Addressing?

Select one:
a.
Single memory reference to access data
b.
Address field contains address of operand
c.
Unlimited address space
d.
No additional calculations to work out effective address

It is an 8 bit or 16 bit immediate value given in the instruction.

Select one:
a.
base

b.
displacement

c.
index

d.
modes

PC – Program counter: does not hold the

address of the next instruction to be
executed
Select one:
True
False
Three basic modes of addressing
Select one:
a.
indirect, direct and unidirectional

b.
register, immediate,memory addressing

c.
indirect address

d.
none of the above

Which is NOT an addressing mode

Select one:
a.
intermediate addressing

b.
immediate addressing

c.
direct addressing

d.
indirect addressing

Set of instructions to process data

Select one:
a.
program

b.
none of the above

c.
database

d.
algorithm
Provides the location, where the data to be processed is stored.
Select one:
a.
indirect address
 b.
Operand Address

c.
Direct address

d.
none of the above

The different ways in which the

location of

the operand is specified in an

instruction

are referred to as addressing modes

Select one:
True
False

Straight line sequencing: If fetching and

executing of instructions is carried out one
by one from successive addresses of
memory, it is called straight line
sequencing.
Select one:
True
 False

  address field

contains address of operand
Select one:
True
False
Three address instruction
Select one:
a.
source, medium and receiver

b.
all of the above

c.
operational source 1, source 2 and destination

d.
sender, medium and receiver

   −In this type

either a source or destination operand is
mentioned in the instruction
Select one:
True
False

  there's
unlimited range
Select one:
True
 False

Sequence can not be changed either

conditionally or unconditionally
Select one:
True
False

Once the third phase is completed, the control

unit starts the cycle again, but now the PC is
pointing to the next instruction.
Select one:
True
False

Instruction is fetched form memory and is

placed in instruction register IR
Select one:
a.
none of the above

b.
instruction decode phase

c.
Instruction execute phase

d.
instruction fetch phase
Refers to the way in which the operand of an instruction is specified.

Select one:
 a.
addressing mode

b.
none of the above
c.
operation

d.
assembly time

Are those which changes the normal

sequence of execution
Select one:
a.
conditional branch

b.
branch instruction

c.
instruction

d.
sequence
8 bits is equivalent to 4 bytes

Select one:
True
False
Conditional branch instruction changes
the sequence only when certain
conditions are met.
Select one:
True
False

The process continues until the CPU reaches a

__________ instruction.
Select one:
a.
write

b.
fetch

c.
halt

d.
stop

Contents of IR is decoded and processor

carries out the operation either by reading
data from memory or registers.
Select one:
a.
instruction fetch phase
 b.
instruction execute phase

c.
instruction decode phase

d.
none of the above

A cycle is made of three phases: fetch, decode

and execute.
Select one:
True
False

Previous page

The instruction whose address is determined by

the PC is obtained from the memory and loaded
into the IR.
Select one:
a.
execute phase

b.
fetch phase

c.
write phase

d.
decode phase
Three phases of machine cycles
Select one:
 a.
all of the above

b.
fetch, decode and execute

c.
fetch, code and execute

d.
read, store and write

Is converted into executable machine code by a utility program referred to as an assembler.

Select one:
a.
Interpreted

b.
Compiled

c.
Assembled

d.
Assembly code
Has a constant value or an expression.

Select one:
a.
immediate addressing

b.
 memory addressing

c.
register addressing

d.
direct addressing

Can be converted to machine language, which

processor understands using assembler
Select one:
a.
Interpreter

b.
none of the above

c.
Mnemonics

d.
Assembler

Memory cell pointed to by address field

contains the address of (pointer to) the
operand
Select one:
a.
Indirect Addressing
 b.
none of the above

c.
Direct Addressing

d.
Non directional addressing

The different ways in which the

location of the operand is

specified in an instruction are referred

to as addressing

modes
Select one:
True
False
Is an assembler that is run on a computer or operating system (the host system) of a different type
from the system on which the resulting code is to run (the target system).

Select one:
a.
high level assembler

b.
cross assembler
 c.
macro assembler

d.
meta assembler
Is the computational step where an assembler is run.

Select one:
a.
counter

b.
ensemble time

c.
none of the above

d.
assembly time

The offset value is specified directly as part of the instruction, usually indicated by the
variable name.
Select one:
a.
indirect addressing mode

b.
immediate addressing mode

c.
direct addressing mode
 d.
unidirectional addressing mode

If fetching and executing of instructions is

carried out one by one from successive
addresses of memory
Select one:
a.
Curve line sequencing

b.
Program counter

c.
Straight line sequencing

d.
instruction execute phase
Holds both instructions and data
Select one:
a.
Hard Disk

b.
Memory

c.
none of the above

d.
 CPU

RTN is easy to understand and but cannot be

used to represent machine instructions
Select one:
True
False

  limited address

space
Select one:
True
False

The instruction is executed and the results are

placed in the appropriate memory location or the
register.
Select one:
a.
write phase

b.
decode phase

c.
fetch phase

d.
execute phase
The process continues when the CPU reaches a
HALT instruction.
Select one:
True
False

During the execute phase, the instruction is

executed and the results are placed in the
appropriate memory location or the register
Select one:
True
False

LHS of RTN always denotes a symbolic

name where value is to be stored and is
called
Select one:
a.
destination

b.
data

c.
address

d.
bus
Conditional branch instruction changes
the sequence of execution irrespective
of condition of the results.
Select one:
True
False

Accordingly we
have conditional branch instructions
and unconditional branch instruction.
Select one:
True
False
Is any low-level programming language in which there is a very strong correspondence between the
instructions in the language and the architecture's machine code instructions.

Select one:
a.
machine language

b.
body language
c.
high level language

d.
assembly language
 Instruction changes the sequence only
when certain conditions are met.
Select one:
a.
Unconditional branch instruction

b.
branch instruction

c.
none of the above

d.
conditional branch instruction

  no memory

reference to fetch data
Select one:
True
False
Contents of base register, BX or BP.
Select one:
a.
displacement

b.
index

c.
memory
 d.
base
is a program that provides language abstractions more often associated with high-level languages,
such as advanced control structures (IF/THEN/ELSE, DO CASE, etc.) and high-level abstract data
types, including structures/records, unions, classes, and sets.

Select one:
a.
high-level assembler

b.
micro assembler

c.
low level assembler

d.
macro assembler

Complete instruction set of the processor

Select one:
a.
program

b.
instruction set architecture

c.
architecture

d.
set architecture
Is determined by adding any combination of three address elements: displacement,
base and index.
 Select one:
a.
subset

b.
offset

c.
offspring

d.
onset

hold the address of the next instruction to

be executed
Select one:
a.
Personal counter

b.
Program counter

c.
Memory counter

d.
IR