EE101: ADC and DAC Circuits: M. B. Patil

EE101: ADC and DAC circuits
M. B. Patil
mbpatil@ee.iitb.ac.in
www.ee.iitb.ac.in/~sequel
Department of Electrical Engineering

Indian Institute of Technology Bombay
M. B. Patil, IIT Bombay

Introduction

Introduction
* Real signals (e.g., a voltage measured with a thermocouple or a speech signal

recorded with a microphone) are analog quantities, varying continuously with
time.

Introduction

time.
* Digital format offers several advantages: digital signal processing, storage, use of
computers, robust transmission, etc.

Introduction

time.
* An ADC (Analog-to-Digital Converter) is used to convert an analog signal to the
digital format.

Introduction

time.
digital format.
* The reverse conversion (from digital to analog) is also required. For example,
music stored in a DVD in digital format must be converted to an analog voltage
for playing out on a speaker.

Introduction

time.
digital format.
* The reverse conversion (from digital to analog) is also required. For example,
music stored in a DVD in digital format must be converted to an analog voltage
for playing out on a speaker.
* A DAC (Digital-to-Analog Converter) is used to convert a digital signal to the
analog format.

DAC
VR
DN−1
N-bit analog
digital VA
output
input
D2
D1
D0
ground
DAC
VR
DN−1
N-bit analog
digital VA
output
input
D2
D1
D0
ground
* For a 4-bit
DAC, with input S3 S2 S1 S0 , the output voltage
is
VA = K (S3 × 23 ) + (S2 × 22 ) + (S1 × 21 ) + (S0 × 20 ) .
PN−1
In general, VA = K 0 Sk 2k .
DAC
VA
VR
maximum
output
DN−1 voltage
N-bit analog
digital VA
output
input
D2
resolution
D1
D0
ground
digital
input
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
* For a 4-bit
is
VA = K (S3 × 23 ) + (S2 × 22 ) + (S1 × 21 ) + (S0 × 20 ) .
PN−1
DAC
VA
VR
maximum
output
DN−1 voltage
N-bit analog
digital VA
output
input
D2
resolution
D1
D0
ground
digital
input
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
* For a 4-bit
is
VA = K (S3 × 23 ) + (S2 × 22 ) + (S1 × 21 ) + (S0 × 20 ) .
PN−1
* K is proportional to the reference voltage VR . Its value depends on how the
DAC is implemented.
DAC using binary-weighted resistors
A3 I3 A3 I3
VR
S3 VR
R3 = R R3 = R
A2 I2 A2 I2
S2 VR
R2 = 2 R R2 = 2 R
A1 I1 A1 I1
Rf S1 VR Rf
R1 = 4 R R1 = 4 R
A0 I0 I A0 I0 I
S0 VR
R0 = 8 R R0 = 8 R
VA VA

A3 I3 A3 I3
VR
S3 VR
R3 = R R3 = R
A2 I2 A2 I2
S2 VR
R2 = 2 R R2 = 2 R
A1 I1 A1 I1
Rf S1 VR Rf
R1 = 4 R R1 = 4 R
A0 I0 I A0 I0 I
S0 VR
R0 = 8 R R0 = 8 R
VA VA
* If the input bit Sk is 1, Ak gets connected to VR ; else, it gets connected to ground.

A3 I3 A3 I3
VR
S3 VR
R3 = R R3 = R
A2 I2 A2 I2
S2 VR
R2 = 2 R R2 = 2 R
A1 I1 A1 I1
Rf S1 VR Rf
R1 = 4 R R1 = 4 R
A0 I0 I A0 I0 I
S0 VR
R0 = 8 R R0 = 8 R
VA VA

→ V (Ak ) = Sk × VR .

A3 I3 A3 I3
VR
S3 VR
R3 = R R3 = R
A2 I2 A2 I2
S2 VR
R2 = 2 R R2 = 2 R
A1 I1 A1 I1
Rf S1 VR Rf
R1 = 4 R R1 = 4 R
A0 I0 I A0 I0 I
S0 VR
R0 = 8 R R0 = 8 R
VA VA

→ V (Ak ) = Sk × VR .
* Since the inverting terminal of the Op Amp is at virtual ground,
V (Ak ) − 0 Sk VR
Ik = = .
Rk Rk

A3 I3 A3 I3
VR
S3 VR
R3 = R R3 = R
A2 I2 A2 I2
S2 VR
R2 = 2 R R2 = 2 R
A1 I1 A1 I1
Rf S1 VR Rf
R1 = 4 R R1 = 4 R
A0 I0 I A0 I0 I
S0 VR
R0 = 8 R R0 = 8 R
VA VA

→ V (Ak ) = Sk × VR .
V (Ak ) − 0 Sk VR
Ik = = .
Rk Rk
N−1
VR X k
* Using Rk = 2N−1 R/2k , we get I = Sk × 2 (N = 4 here).
2N−1 R 0

A3 I3 A3 I3
VR
S3 VR
R3 = R R3 = R
A2 I2 A2 I2
S2 VR
R2 = 2 R R2 = 2 R
A1 I1 A1 I1
Rf S1 VR Rf
R1 = 4 R R1 = 4 R
A0 I0 I A0 I0 I
S0 VR
R0 = 8 R R0 = 8 R
VA VA

→ V (Ak ) = Sk × VR .
V (Ak ) − 0 Sk VR
Ik = = .
Rk Rk
N−1
VR X k
* Using Rk = 2N−1 R/2k , we get I = Sk × 2 (N = 4 here).
2N−1 R 0
N−1
Rf X k
* The output voltage is Vo = −Rf I = −VR Sk × 2 .
2N−1 R 0

DAC using binary-weighted resistors: Example (from Gopalan)
A7 I7
VR
R7 = R
A1 I1
Rf
R1 = 26 R
A0 I0 I
R0 = 27 R
VA

A7 I7
VR
R7 = R
A1 I1
Rf
R1 = 26 R
A0 I0 I
R0 = 27 R
VA
* Consider an 8-bit DAC with VR = 5 V. What is the smallest value of R which will limit the
current drawn from the supply (VR ) to 10 mA?

A7 I7
VR
R7 = R
A1 I1
Rf
R1 = 26 R
A0 I0 I
R0 = 27 R
VA
Maximum current is drawn from VR when the input is 1111 1111.

A7 I7
VR
R7 = R
A1 I1
Rf
R1 = 26 R
A0 I0 I
R0 = 27 R
VA
→ All nodes A0 to A7 get connected to VR .

A7 I7
VR
R7 = R
A1 I1
Rf
R1 = 26 R
A0 I0 I
R0 = 27 R
VA
VR VR VR 1 VR 0 1 7

→ 10 mA = + + ··· + 7 = 7 2 + 2 + ··· + 2
R 2R 2 R 2 R
1 VR 8 255 VR
= 7 2 −1 =
2 R 128 R

A7 I7
VR
R7 = R
A1 I1
Rf
R1 = 26 R
A0 I0 I
R0 = 27 R
VA
VR VR VR 1 VR 0 1 7

→ 10 mA = + + ··· + 7 = 7 2 + 2 + ··· + 2
R 2R 2 R 2 R
1 VR 8 255 VR
= 7 2 −1 =
2 R 128 R
5V 255
→ Rmin = × = 996 Ω .
10 mA 128
A7 I7
VR
R7 = R
A1 I1
Rf
6
R1 = 2 R
A0 I0 I
7
R0 = 2 R
VA

A7 I7
VR
R7 = R
A1 I1
Rf
6
R1 = 2 R
A0 I0 I
7
R0 = 2 R
VA
* If Rf = R, what is the resolution (i.e., ∆VA corresponding to the input LSB changing from 0
to 1 with other input bits constant)?

A7 I7
VR
R7 = R
A1 I1
Rf
6
R1 = 2 R
A0 I0 I
7
R0 = 2 R
VA
Rf h
7 1 0
i
VA = −VR N−1 S7 2 + · · · + S1 2 + S0 2
2 R

A7 I7
VR
R7 = R
A1 I1
Rf
6
R1 = 2 R
A0 I0 I
7
R0 = 2 R
VA
Rf h
7 1 0
i
VA = −VR N−1 S7 2 + · · · + S1 2 + S0 2
2 R
VR Rf 5V 5
→ ∆VA = N−1 = 8−1 × 1 = = 0.0391 V.
2 R 2 128

A7 I7
VR
R7 = R
A1 I1
Rf
6
R1 = 2 R
A0 I0 I
R0 = 27 R
VA

A7 I7
VR
R7 = R
A1 I1
Rf
6
R1 = 2 R
A0 I0 I
R0 = 27 R
VA
* What is the maximum output voltage (in magnitude)?

A7 I7
VR
R7 = R
A1 I1
Rf
6
R1 = 2 R
A0 I0 I
R0 = 27 R
VA

VR Rf h 7 1 0
i
VA = − N−1 S7 2 + · · · + S1 2 + S0 2 .
2 R

A7 I7
VR
R7 = R
A1 I1
Rf
6
R1 = 2 R
A0 I0 I
R0 = 27 R
VA

VR Rf h 7 1 0
i
VA = − N−1 S7 2 + · · · + S1 2 + S0 2 .
2 R
Maximum VA (in magnitude) is obtained when the input is 1111 1111.

A7 I7
VR
R7 = R
A1 I1
Rf
6
R1 = 2 R
A0 I0 I
R0 = 27 R
VA

VR Rf h 7 1 0
i
VA = − N−1 S7 2 + · · · + S1 2 + S0 2 .
2 R
Maximum VA (in magnitude) is obtained when the input is 1111 1111.
5 h
0 1 7
i 5
8
255
|VA |max = × 1 × 2 + 2 + ··· + 2 = × 2 −1 =5× = 9.961 V .
128 128 128

A7 I7
VR
R7 = R
A1 I1
Rf
6
R1 = 2 R
A0 I0 I
R0 = 27 R
VA

A7 I7
VR
R7 = R
A1 I1
Rf
6
R1 = 2 R
A0 I0 I
R0 = 27 R
VA
* Find the output voltage corresponding to the input 1010 1101.

A7 I7
VR
R7 = R
A1 I1
Rf
6
R1 = 2 R
A0 I0 I
R0 = 27 R
VA

VR Rf h 7 1 0
i
VA = − N−1 S7 2 + · · · + S1 2 + S0 2 .
2 R

A7 I7
VR
R7 = R
A1 I1
Rf
6
R1 = 2 R
A0 I0 I
R0 = 27 R
VA

VR Rf h 7 1 0
i
VA = − N−1 S7 2 + · · · + S1 2 + S0 2 .
2 R
5 h
7 5 3 2 0
i 173
=− × 1 × 2 + 2 + 2 + 2 + 2 = −5 × = −6.758 V .
128 128

A7 I7
VR
R7 = R
A1 I1
Rf
R1 = 26 R
A0 I0 I
7
R0 = 2 R
VA

A7 I7
VR
R7 = R
A1 I1
Rf
R1 = 26 R
A0 I0 I
7
R0 = 2 R
VA
* If the resistors are specified to have a tolerance of 1 %, what is the range of |VA |
corresponding to input 1111 1111?

A7 I7
VR
R7 = R
A1 I1
Rf
R1 = 26 R
A0 I0 I
7
R0 = 2 R
VA
|VA | is maximum when (a) currents I0 , I1 , etc. assume their maximum values, with
Rk = Rk0 × (1 − 0.01) and (b) Rf is maximum, Rf = Rf0 × (1 + 0.01).
(The superscript ‘0’ denotes nominal value.)

A7 I7
VR
R7 = R
A1 I1
Rf
R1 = 26 R
A0 I0 I
7
R0 = 2 R
VA
max 255 Rf max 255 1.01
→ |VA |11111111 = VR × × =5× × = 10.162 V.
128 R 128 0.99

A7 I7
VR
R7 = R
A1 I1
Rf
R1 = 26 R
A0 I0 I
7
R0 = 2 R
VA
max 255 Rf max 255 1.01
→ |VA |11111111 = VR × × =5× × = 10.162 V.
128 R 128 0.99
255 0.99
Similarly, |VA |min
11111111 = 5 × × = 9.764 V.
128 1.01

A7 I7
VR
R7 = R
A1 I1
Rf
R1 = 26 R
A0 I0 I
R0 = 27 R
VA

A7 I7
VR
R7 = R
A1 I1
Rf
R1 = 26 R
A0 I0 I
R0 = 27 R
VA
* ∆VA for input 1111 1111 = 10.162 − 9.764 ≈ 0.4 V which is larger than the resolution
(0.039 V) of the DAC. This situation is not acceptable.

A7 I7
VR
R7 = R
A1 I1
Rf
R1 = 26 R
A0 I0 I
R0 = 27 R
VA
* The output voltage variation can be reduced by using resistors with a smaller tolerance.
However, it is difficult to fabricate an IC with widely varying resistance values (from R to
2N−1 R) and each with a small enough tolerance.

A7 I7
VR
R7 = R
A1 I1
Rf
R1 = 26 R
A0 I0 I
R0 = 27 R
VA
* The output voltage variation can be reduced by using resistors with a smaller tolerance.
However, it is difficult to fabricate an IC with widely varying resistance values (from R to
2N−1 R) and each with a small enough tolerance.
→ use R − 2R ladder network instead.

R-2R ladder network
R R R
2R 2R 2R 2R 2R
A0 A1 A2 A3
LSB MSB
Node Ak is connected to VR if input bit Sk is 1;

else, it is connected to ground.
R-2R ladder network
R R R
2R 2R 2R 2R 2R
A0 A1 A2 A3
LSB MSB
Node Ak is connected to VR if input bit Sk is 1;

else, it is connected to ground.
The original network is equivalent to
R R R
2R 2R 2R 2R 2R
S 0 VR S1 VR S2 VR S3 VR

R-2R ladder network: Thevenin resistance
R R R
2R 2R 2R 2R 2R
R R R
2R 2R 2R 2R 2R
R R R
2R 2R 2R 2R 2R
R R R
R 2R 2R 2R
R R R
2R 2R 2R 2R 2R
R R R
R 2R 2R 2R
R R R
2R 2R 2R 2R 2R
R R R
R 2R 2R 2R
R R
R 2R 2R
R R R
2R 2R 2R 2R 2R
R R R
R 2R 2R 2R
R R
R 2R 2R
R R R
2R 2R 2R 2R 2R
R R R
R 2R 2R 2R
R R
R 2R 2R
R
R 2R
R R R
2R 2R 2R 2R 2R
R R R
R 2R 2R 2R
R R
R 2R 2R
R
R 2R
R R R
2R 2R 2R 2R 2R
R R R
R 2R 2R 2R
R R
R 2R 2R
R
R 2R RTh = R

R-2R ladder network: VTh for S0 = 1
R R R
2R 2R 2R 2R 2R
VR
R R R
2R 2R 2R 2R 2R
VR
R R R
2R 2R 2R 2R 2R
VR
R R R
R 2R 2R 2R
VR
2
R R R
2R 2R 2R 2R 2R
VR
R R R
R 2R 2R 2R
VR
2
R R R
2R 2R 2R 2R 2R
VR
R R R
R 2R 2R 2R
VR
2
R R
R 2R 2R
VR
4
R R R
2R 2R 2R 2R 2R
VR
R R R
R 2R 2R 2R
VR
2
R R
R 2R 2R
VR
4
R R R
2R 2R 2R 2R 2R
VR
R R R
R 2R 2R 2R
VR
2
R R
R 2R 2R
VR
4
R 2R
VR
8
R R R
2R 2R 2R 2R 2R
VR
R R R
R 2R 2R 2R
VR
2
R R
R 2R 2R
VR
4
R 2R
VR
8
R R R
2R 2R 2R 2R 2R
VR
R R R
R 2R 2R 2R
VR
2
R R
R 2R 2R
VR
4
R 2R
VR
VTh =
VR 16
8

R R R
2R 2R 2R 2R 2R
VR
R R R
2R 2R 2R 2R 2R
VR
R R R
2R 2R 2R 2R 2R
VR
R R
2R 2R 2R 2R
VR
R R R
2R 2R 2R 2R 2R
VR
R R
2R 2R 2R 2R
VR
R R R
2R 2R 2R 2R 2R
VR
R R
2R 2R 2R 2R
VR
R R
R 2R 2R
VR
2
R R R
2R 2R 2R 2R 2R
VR
R R
2R 2R 2R 2R
VR
R R
R 2R 2R
VR
2
R R R
2R 2R 2R 2R 2R
VR
R R
2R 2R 2R 2R
VR
R R
R 2R 2R
VR
2
R 2R
VR
4
R R R
2R 2R 2R 2R 2R
VR
R R
2R 2R 2R 2R
VR
R R
R 2R 2R
VR
2
R 2R
VR
4
R R R
2R 2R 2R 2R 2R
VR
R R
2R 2R 2R 2R
VR
R R
R 2R 2R
VR
2
R 2R
VR
VTh =
VR 8
4

R R R
2R 2R 2R 2R 2R
VR
R R R
2R 2R 2R 2R 2R
VR
R R R
2R 2R 2R 2R 2R
VR
2R 2R 2R
VR
R R R
2R 2R 2R 2R 2R
VR
2R 2R 2R
VR
R R R
2R 2R 2R 2R 2R
VR
2R 2R 2R
VR
R 2R
VR
2
R R R
2R 2R 2R 2R 2R
VR
2R 2R 2R
VR
R 2R
VR
2
R R R
2R 2R 2R 2R 2R
VR
2R 2R 2R
VR
R 2R
VR
VTh =
VR 4
2

R R R
2R 2R 2R 2R 2R
VR
R R R
2R 2R 2R 2R 2R
VR
R R R
2R 2R 2R 2R 2R
VR
2R 2R
VR
R R R
2R 2R 2R 2R 2R
VR
2R 2R
VR
VTh =
2
VR

R-2R ladder network: RTh and VTh
R R R
2R 2R 2R 2R 2R RTh
VTh
S0 VR S1 VR S2 VR S3 VR

R R R
2R 2R 2R 2R 2R RTh
VTh
* RTh = R .

R R R
2R 2R 2R 2R 2R RTh
VTh
* RTh = R .
(S0) (S1) (S2) (S3)
* VTh = VTh + VTh + VTh + VTh
VR h 0 1 2 3
i
= S0 2 + S1 2 + S2 2 + S3 2 .
16

R R R
2R 2R 2R 2R 2R RTh
VTh
* RTh = R .
(S0) (S1) (S2) (S3)
* VTh = VTh + VTh + VTh + VTh
VR h 0 1 2 3
i
= S0 2 + S1 2 + S2 2 + S3 2 .
16
* We can use the R-2R ladder network and an Op Amp
to make up a DAC → next slide.

DAC with R-2R ladder
Rf Rf
R R R RTh
2R 2R 2R 2R 2R Vo VTh Vo
S 0 VR S 1 VR S 2 VR S 3 VR

Rf Rf
R R R RTh
Rf Rf VR h 0 1 2 3
i
* Vo = − VTh = − S0 2 + S1 2 + S2 2 + S3 2 .
RTh RTh 16

Rf Rf
R R R RTh
Rf Rf VR h 0 1 2 3
i
* Vo = − VTh = − S0 2 + S1 2 + S2 2 + S3 2 .
RTh RTh 16
N−1
Rf Rf VR X k
* For an N-bit DAC, Vo = − VTh = − Sk 2 .
RTh RTh 2N 0

Rf Rf
R R R RTh
Rf Rf VR h 0 1 2 3
i
* Vo = − VTh = − S0 2 + S1 2 + S2 2 + S3 2 .
RTh RTh 16
N−1
Rf Rf VR X k
RTh RTh 2N 0
* 6- to 20-bit DACs based on the R-2R ladder network are commercially available in
monolithic form (single chip).

Rf Rf
R R R RTh
Rf Rf VR h 0 1 2 3
i
* Vo = − VTh = − S0 2 + S1 2 + S2 2 + S3 2 .
RTh RTh 16
N−1
Rf Rf VR X k
RTh RTh 2N 0
* 6- to 20-bit DACs based on the R-2R ladder network are commercially available in
monolithic form (single chip).
* Bipolar, CMOS, or BiCMOS technology is used for these DACs.

DAC: home work
Rf
8R 4R 2R R 8R 4R 2R R Vo
S0 VR S 1 VR S2 VR S 3 VR S4 VR S5 VR S6 VR S7 VR
Combination of weighted−resistor and R−2R ladder networks

DAC: home work
Rf
* Find the valur of r for the circuit to work as a regular (i.e., binary to analog) DAC.

DAC: home work
Rf
* Find the valur of r for the circuit to work as a regular (i.e., binary to analog) DAC.
* Find the valur of r for the circuit to work as a BCD to analog DAC.

DAC: settling time
VR
VA
DN−1
final
value
N-bit analog
digital VA initial
output
input value
D2
D1
t
D0
ground

DAC: settling time
VR
VA
DN−1
final
value
N-bit analog
digital VA initial
output
input value
D2
D1
t
D0
ground
* When there is a change in the input binary number, the output VA takes a finite time to
settle to the new value.

DAC: settling time
VR
VA
DN−1
final
value
N-bit analog
digital VA initial
output
input value
D2
D1
t
D0
ground
* The finite settling time arises because of stray capacitances and switching delays of the
semiconductor devices used within the DAC chip.

DAC: settling time
VR
VA
DN−1
final
value
N-bit analog
digital VA initial
output
input value
D2
D1
t
D0
ground
* The finite settling time arises because of stray capacitances and switching delays of the
semiconductor devices used within the DAC chip.
* Example: 500 ns to 0.2 % of full scale.

ADC: introduction
Vmax
111
V7R
VR 110
V6R
101
D2 V5R
V′A 100
analog digital
VA D1 V4R
input output
011
D0 V3R
010
V2R
ground 001
V1R
3−bit ADC 000
0

ADC: introduction
Vmax
111
V7R
VR 110
V6R
101
D2 V5R
V′A 100
analog digital
VA D1 V4R
input output
011
D0 V3R
010
V2R
ground 001
V1R
3−bit ADC 000
0
* If the input VA is in the range VRk < VA < VRk+1 , the output is the binary
number corresponding to the integer k. For example, for VA = VA0 , the output is
100.

ADC: introduction
Vmax
111
V7R
VR 110
V6R
101
D2 V5R
V′A 100
analog digital
VA D1 V4R
input output
011
D0 V3R
010
V2R
ground 001
V1R
3−bit ADC 000
0
100.
* We may think of each voltage interval (corresponding to 000, 001, etc.) as a
“bin.” In the above example, the input voltage VA0 falls in the 100 bin; therefore,
the output of the ADC would be 100.

ADC: introduction
Vmax
111
V7R
VR 110
V6R
101
D2 V5R
V′A 100
analog digital
VA D1 V4R
input output
011
D0 V3R
010
V2R
ground 001
V1R
3−bit ADC 000
0
100.
* We may think of each voltage interval (corresponding to 000, 001, etc.) as a
“bin.” In the above example, the input voltage VA0 falls in the 100 bin; therefore,
the output of the ADC would be 100.
* Note that, for an N-bit ADC, there would be 2N bins.

ADC: introduction
Vmax
111
V7R
VR 110
V6R
101
D2 V5R
V′A 100
analog digital
VA D1 V4R
input output
011
D0 V3R
010
V2R
ground 001
V1R
3−bit ADC 000
0

ADC: introduction
Vmax
111
V7R
VR 110
V6R
101
D2 V5R
V′A 100
analog digital
VA D1 V4R
input output
011
D0 V3R
010
V2R
ground 001
V1R
3−bit ADC 000
0
* The basic idea behind an ADC is simple:

ADC: introduction
Vmax
111
V7R
VR 110
V6R
101
D2 V5R
V′A 100
analog digital
VA D1 V4R
input output
011
D0 V3R
010
V2R
ground 001
V1R
3−bit ADC 000
0

- Generate reference voltages VR1 , VR2 , etc.

ADC: introduction
Vmax
111
V7R
VR 110
V6R
101
D2 V5R
V′A 100
analog digital
VA D1 V4R
input output
011
D0 V3R
010
V2R
ground 001
V1R
3−bit ADC 000
0

- Compare the input VA with each of VRi to figure out which bin it
belongs to.

ADC: introduction
Vmax
111
V7R
VR 110
V6R
101
D2 V5R
V′A 100
analog digital
VA D1 V4R
input output
011
D0 V3R
010
V2R
ground 001
V1R
3−bit ADC 000
0

belongs to.
- If VA belongs to bin k (i.e., VRk < VA < VRk+1 ), convert k to the
binary format.

ADC: introduction
Vmax
111
V7R
VR 110
V6R
101
D2 V5R
V′A 100
analog digital
VA D1 V4R
input output
011
D0 V3R
010
V2R
ground 001
V1R
3−bit ADC 000
0

belongs to.
- If VA belongs to bin k (i.e., VRk < VA < VRk+1 ), convert k to the
binary format.
* A “parallel” ADC does exactly that → next slide.

3-bit parallel (flash) ADC
VA
VR
R
2
Vmax R
111
V7R
110
VR
V6R R
101
D2 V5R D2
V′A 100
digital R
analog D1 V4R D1
input VA output LOGIC
011
D0 V3R D0
010 R
V2R
ground 001
V1R R
3−bit ADC 000
0
R
2

VA
VR
R
2 C6
R C5
R C4
D2
R C3
LOGIC D1
D0
R C2
R C1
R C0
R
2
VA
VR
R
2 C6
R C5
R C4
D2
R C3
LOGIC D1
D0
R C2
R C1
R C0
R
2
* Practical difficulty: As the input changes, the comparator outputs (C0 , C1 , etc.) may not
settle to their new values at the same time.
→ ADC output will depend on when we sample it.
VA
VR
R
2 C6
R C5
R C4
D2
R C3
LOGIC D1
D0
R C2
R C1
R C0
R
2
* Add D flip-flops. Allow sifficient time (between the change in VA and the active clock edge)
so that the comprator outputs have already settled to their new values before they get
latched in.
VA
VA VR
VR
R
R C6
C6
2 D Q6
2 Q
R C5
R C5 D Q5
Q
R C4
R C4 D Q4
Q
D2 D2
R C3
R C3 D Q3
LOGIC D1 Q LOGIC D1
D0 R C2 D0
R C2 D Q2
Q
R C1
R C1 D Q1
Q
R C0
R C0 D Q0
Q
R
R
2 Clock
2
* Add D flip-flops. Allow sifficient time (between the change in VA and the active clock edge)
so that the comprator outputs have already settled to their new values before they get
latched in.
Parallel (flash) ADC
* In the parallel (flash) ADC, the conversion gets done “in parallel,” since all
comparators operate on the same input voltage.

* Conversion time is governed only by the comparator response time → fast
conversion (hence the name “flash” converter).

* Flash ADCs to handle 500 million analog samples per second are commercially
available.

* Flash ADCs to handle 500 million analog samples per second are commercially
available.
* 2N comparators are required for N-bit ADC → generally limited to 8 bits.

ADC: sampling of input signal
clock
clock
S
Va C Vs → to ADC
t
Va
Vs
clock
Vs
S buffer Tc
Va buffer C t

clock
clock
S
Va C Vs → to ADC
t
Va
Vs
clock
Vs
S buffer Tc
Va buffer C t
* An ADC typically operates on a “sampled” input signal (Vs (t) in the figure) which is
derived from the continuously varying input signal (Va (t) in the figure) with a
“sample-and-hold” (S/H) circuit.

clock
clock
S
Va C Vs → to ADC
t
Va
Vs
clock
Vs
S buffer Tc
Va buffer C t
* The S/H circuit samples the input signal Va (t) at uniform intervals of duration Tc , the
clock period.

clock
clock
S
Va C Vs → to ADC
t
Va
Vs
clock
Vs
S buffer Tc
Va buffer C t
clock period.
* When the clock goes high, switch S (e.g., a FET or a CMOS pass gate) is closed, and the
capacitor C gets charged to the signal voltage at that time. When the clock goes low,
switch S is turned off, and C holds the voltage constant, as desired.

clock
clock
S
Va C Vs → to ADC
t
Va
Vs
clock
Vs
S buffer Tc
Va buffer C t
clock period.
* When the clock goes high, switch S (e.g., a FET or a CMOS pass gate) is closed, and the
capacitor C gets charged to the signal voltage at that time. When the clock goes low,
switch S is turned off, and C holds the voltage constant, as desired.
* Op Amp buffers can be used to minimise loading effects.
Successive Approximation ADC
D3 D2 D1 D0
4−bit DAC
VDAC
o
C
VA
Comparator

D3 D2 D1 D0
4−bit DAC
VDAC
o
C
VA
Comparator
* Suppose we have a 4-bit DAC. We can use it to perform A-to-D conversion by

successively setting the four bits as follows.

D3 D2 D1 D0
4−bit DAC
VDAC
o
C
VA
Comparator

- Start with D3 D2 D1 D0 = 0000, I = 3.

D3 D2 D1 D0
4−bit DAC
VDAC
o
C
VA
Comparator

- Start with D3 D2 D1 D0 = 0000, I = 3.
- Set D[I] = 1 (keep other bits unchanged).

D3 D2 D1 D0
4−bit DAC
VDAC
o
C
VA
Comparator

- Start with D3 D2 D1 D0 = 0000, I = 3.
- If VoDAC > VA (i.e., C = 0), set D[I] = 0; else, keep D[I] = 1.

D3 D2 D1 D0
4−bit DAC
VDAC
o
C
VA
Comparator

- Start with D3 D2 D1 D0 = 0000, I = 3.
- I ← I − 1; go to step 1.

D3 D2 D1 D0
4−bit DAC
VDAC
o
C
VA
Comparator

- Start with D3 D2 D1 D0 = 0000, I = 3.
- I ← I − 1; go to step 1.
* At the end of four steps, the digital output is given by D3 D2 D1 D0 .
Example → next slide.

VDAC
o
30 k
24 k
23 k
D4 D3 D2 D1 D0
VA 22 k
20 k
20 k
VR 5−bit DAC 16 k
VDAC
o
D4 =1 D4 =1 D4 =1 D4 =1 D4 =1
D3 =0 D3 =1 D3 =0 D3 =0 D3 =0
VA C 10 k D2 =0 D2 =0 D2 =1 D2 =1 D2 =1
D1 =0 D1 =0 D1 =0 D1 =1 D1 =1
D0 =0 D0 =0 D0 =0 D0 =0 D0 =1
(Note: k ∝ VR )
C=1 C=0 C=1 C=1 C=0
→ reset D3 → reset D0
1 2 3 4 5 step

VDAC
o
30 k
24 k
23 k
D4 D3 D2 D1 D0
VA 22 k
20 k
20 k
VR 5−bit DAC 16 k
VDAC
o
D4 =1 D4 =1 D4 =1 D4 =1 D4 =1
D3 =0 D3 =1 D3 =0 D3 =0 D3 =0
VA C 10 k D2 =0 D2 =0 D2 =1 D2 =1 D2 =1
D1 =0 D1 =0 D1 =0 D1 =1 D1 =1
D0 =0 D0 =0 D0 =0 D0 =0 D0 =1
(Note: k ∝ VR )
C=1 C=0 C=1 C=1 C=0
1 2 3 4 5 step
th
* At the end of the 5 step, we know that the input voltage corresponds to 10110.

VDAC
o
30 k
24 k
23 k
D4 D3 D2 D1 D0
VA 22 k
20 k
20 k
VR 5−bit DAC 16 k
VDAC
o
D4 =1 D4 =1 D4 =1 D4 =1 D4 =1
D3 =0 D3 =1 D3 =0 D3 =0 D3 =0
VA C 10 k D2 =0 D2 =0 D2 =1 D2 =1 D2 =1
D1 =0 D1 =0 D1 =0 D1 =1 D1 =1
D0 =0 D0 =0 D0 =0 D0 =0 D0 =1
(Note: k ∝ VR )
C=1 C=0 C=1 C=1 C=0
1 2 3 4 5 step
th
* At the end of the 5 step, we know that the input voltage corresponds to 10110.
* For the digital representation to be accurate up to ± 12 LSB, ∆V corresponding to 1
2 LSB is
added to VA (see [Taub]).
VA S/H Successive
Control Approximation
logic N−bit SAR
VDAC
o
Register
Comparator
digital
output
VR N−bit DAC

VA S/H Successive
logic N−bit SAR
VDAC
o
Register
Comparator
digital
output
VR N−bit DAC
* Each step (setting SAR bits, comparison of VA and VoDAC ) is performed in one clock cycle
→ conversion time is N cycles, irrespective of the input voltage value VA .

VA S/H Successive
logic N−bit SAR
VDAC
o
Register
Comparator
digital
output
VR N−bit DAC
* S. A. ADCs with built-in or external S/H (sample-and-hold) are available for 8- to 16-bit
resolution and conversion times of a few µsec to tens of µsec.

VA S/H Successive
logic N−bit SAR
VDAC
o
Register
Comparator
digital
output
VR N−bit DAC
* S. A. ADCs with built-in or external S/H (sample-and-hold) are available for 8- to 16-bit
resolution and conversion times of a few µsec to tens of µsec.
* Useful for medium-speed applications such as speech transmission with PCM.

Counting ADC
start N−bit Counter

conversion
VDAC
o
reset clock
digital
output VA
clock
VR N−bit DAC
VDAC Comparator Tc
o
VA S/H t
C Tc

Counting ADC

conversion
VDAC
o
reset clock
digital
output VA
clock
VR N−bit DAC
VDAC Comparator Tc
o
VA S/H t
C Tc
* The “start conversion” signal clears the counter; counting begins, and VoDAC increases with
each clock cycle.

Counting ADC

conversion
VDAC
o
reset clock
digital
output VA
clock
VR N−bit DAC
VDAC Comparator Tc
o
VA S/H t
C Tc
each clock cycle.
* When VoDAC exceeds VA , C becomes 0, and counting stops.

Counting ADC

conversion
VDAC
o
reset clock
digital
output VA
clock
VR N−bit DAC
VDAC Comparator Tc
o
VA S/H t
C Tc
each clock cycle.
* When VoDAC exceeds VA , C becomes 0, and counting stops.
* Simple scheme, but (a) conversion time depends on VA , (b) slow (takes 2N clock cycles in
the worst case) → tracking ADC (next slide)

Tracking ADC
Up/Down
VDAC
o
clock
N−bit Counter
Tc VA
digital
output
VR N−bit DAC
Comparator
VA S/H t
Tc
C
VDAC
o

Tracking ADC
Up/Down
VDAC
o
clock
N−bit Counter
Tc VA
digital
output
VR N−bit DAC
Comparator
VA S/H t
Tc
C
VDAC
o
* The counter counts up if VoDAC < VA ; else, it counts down.

Tracking ADC
Up/Down
VDAC
o
clock
N−bit Counter
Tc VA
digital
output
VR N−bit DAC
Comparator
VA S/H t
Tc
C
VDAC
o

* If VA changes, the counter does not need to start from 000· · · 0, so the conversion time is
less than that required by a counting ADC.

Tracking ADC
Up/Down
VDAC
o
clock
N−bit Counter
Tc VA
digital
output
VR N−bit DAC
Comparator
VA S/H t
Tc
C
VDAC
o

* If VA changes, the counter does not need to start from 000· · · 0, so the conversion time is
less than that required by a counting ADC.
* used in low-cost, low-speed applications, e.g., measuring output from a temperature sensor
or a strain gauge

Dual-slope ADC
S
T1 T2
0
VA C t
VR
VR Vi R Z slope = −
1 RC
Vo = − Vi dt −V1
RC
VA
slope = −
RC

Dual-slope ADC
S
T1 T2
0
VA C t
VR
1 RC
RC
VA
slope = −
RC
* t = 0: reset integrator output Vo to 0 V by closing S momentarily.

Dual-slope ADC
S
T1 T2
0
VA C t
VR
1 RC
RC
VA
slope = −
RC

* Integrate VA (voltage to be converted to digital format, assumed to be positive) for a fixed
interval T1 .

Dual-slope ADC
S
T1 T2
0
VA C t
VR
1 RC
RC
VA
slope = −
RC

interval T1 .
T1
* At t = T1 , integrator output reaches −V1 = − VA .
RC

Dual-slope ADC
S
T1 T2
0
VA C t
VR
1 RC
RC
VA
slope = −
RC

interval T1 .
T1
RC
* Now apply a reference voltage VR (assumed to be negative, with |VR | > VA ), and integrate
until Vo reaches 0 V.

Dual-slope ADC
S
T1 T2
0
VA C t
VR
1 RC
RC
VA
slope = −
RC

interval T1 .
T1
RC
T1 T2 VA
* Since V1 = VA = |VR | , we have T2 = T1 → T2 gives a measure of VA .
RC RC |VR |

Dual-slope ADC
S
T1 T2
0
VA C t
VR
1 RC
RC
VA
slope = −
RC

interval T1 .
T1
RC
T1 T2 VA
* Since V1 = VA = |VR | , we have T2 = T1 → T2 gives a measure of VA .
RC RC |VR |
* In the dual-slope ADC, a counter output – which is proportional to T2 – provides the desired
digital output.

Dual-slope ADC
reset
SPDT
A C T1 = 2N Tc T2
VA comparator 0
VR B R
Vo t
VR
slope = −
integrator RC
−V1
VA
N−bit Counter slope = −
RC
overflow clock
clock
digital output Tc

Dual-slope ADC
reset
SPDT
A C T1 = 2N Tc T2
VA comparator 0
VR B R
Vo t
VR
slope = −
integrator RC
−V1
VA
RC
overflow clock
clock
digital output Tc
* Start: counter reset to 000· · · 0, SPDT in position A.

Dual-slope ADC
reset
SPDT
A C T1 = 2N Tc T2
VA comparator 0
VR B R
Vo t
VR
slope = −
integrator RC
−V1
VA
RC
overflow clock
clock
digital output Tc

* Counter counts up to 2N at which point the overflow flag becomes 1, and SPDT switches to
position B → T1 = 2N Tc where Tc is the clock period.

Dual-slope ADC
reset
SPDT
A C T1 = 2N Tc T2
VA comparator 0
VR B R
Vo t
VR
slope = −
integrator RC
−V1
VA
RC
overflow clock
clock
digital output Tc

* Counter counts up to 2N at which point the overflow flag becomes 1, and SPDT switches to
position B → T1 = 2N Tc where Tc is the clock period.
* The counter starts counting again from 000· · · 0, and stops counting when Vo crosses 0 V.
The counter output gives T2 in binary format.

References
* K. Gopalan, Introduction to Digital Microelectronic Circuits, Tata McGraw-Hill,

New Delhi, 1978.
* H. Taub and D. Schilling, Digital Integrated Electronics, McGraw-Hill, 1977.

EE101: ADC and DAC Circuits: M. B. Patil

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EE101: ADC and DAC circuits

Department of Electrical Engineering

M. B. Patil, IIT Bombay

M. B. Patil, IIT Bombay

* Real signals (e.g., a voltage measured with a thermocouple or a speech signal

M. B. Patil, IIT Bombay

* Real signals (e.g., a voltage measured with a thermocouple or a speech signal

M. B. Patil, IIT Bombay

* Real signals (e.g., a voltage measured with a thermocouple or a speech signal

M. B. Patil, IIT Bombay

* Real signals (e.g., a voltage measured with a thermocouple or a speech signal

M. B. Patil, IIT Bombay

* Real signals (e.g., a voltage measured with a thermocouple or a speech signal

M. B. Patil, IIT Bombay

M. B. Patil, IIT Bombay

* If the input bit Sk is 1, Ak gets connected to VR ; else, it gets connected to ground.

M. B. Patil, IIT Bombay

* If the input bit Sk is 1, Ak gets connected to VR ; else, it gets connected to ground.

M. B. Patil, IIT Bombay

* If the input bit Sk is 1, Ak gets connected to VR ; else, it gets connected to ground.

M. B. Patil, IIT Bombay

* If the input bit Sk is 1, Ak gets connected to VR ; else, it gets connected to ground.

M. B. Patil, IIT Bombay

* If the input bit Sk is 1, Ak gets connected to VR ; else, it gets connected to ground.

M. B. Patil, IIT Bombay

M. B. Patil, IIT Bombay

M. B. Patil, IIT Bombay

M. B. Patil, IIT Bombay

M. B. Patil, IIT Bombay

M. B. Patil, IIT Bombay

M. B. Patil, IIT Bombay

M. B. Patil, IIT Bombay

M. B. Patil, IIT Bombay

M. B. Patil, IIT Bombay

M. B. Patil, IIT Bombay

* What is the maximum output voltage (in magnitude)?

M. B. Patil, IIT Bombay

* What is the maximum output voltage (in magnitude)?

M. B. Patil, IIT Bombay

* What is the maximum output voltage (in magnitude)?

M. B. Patil, IIT Bombay

* What is the maximum output voltage (in magnitude)?

M. B. Patil, IIT Bombay

M. B. Patil, IIT Bombay

* Find the output voltage corresponding to the input 1010 1101.

M. B. Patil, IIT Bombay

* Find the output voltage corresponding to the input 1010 1101.

M. B. Patil, IIT Bombay

* Find the output voltage corresponding to the input 1010 1101.

M. B. Patil, IIT Bombay

M. B. Patil, IIT Bombay

M. B. Patil, IIT Bombay

M. B. Patil, IIT Bombay

M. B. Patil, IIT Bombay

M. B. Patil, IIT Bombay

M. B. Patil, IIT Bombay

M. B. Patil, IIT Bombay

M. B. Patil, IIT Bombay

M. B. Patil, IIT Bombay

Node Ak is connected to VR if input bit Sk is 1;

Node Ak is connected to VR if input bit Sk is 1;

M. B. Patil, IIT Bombay

M. B. Patil, IIT Bombay