Table of contents

List of Figures
List of Tables
List of Abbreviations

Chapter 1.Introduction 1
1.1 Motivation 3

1.2 Problem statement 3

1.3 Objective 4
1.4 Program outcome addressed 6

Chapter 2.Literature Survey 7

Chapter 3.Background Theory 15

3.1 Electron spins 15
3.2 QCA solution 19

3.3 QCA basic cell

3.4 QCA polarization
3.5 QCA clocking
3.6 Cell to Cell response
3.7 QCA wires
3.8 Crossover

Chapter 4.Methodology
4.1 Majority gate design 20

4.2 Design of AND gate 21

4.3 Design of OR gate 24

4.4 Design of NAND gate 26

4.5 Design of NOR gate 28

4.6 Design of NOT gate 30

4.7 Design of EX-OR gate 24

 4.8 Design of EX-NOR gate 31

4.9 Design of HALF-ADDER circuit

4.10 Design of FULL-ADDER QCA circuit

4.11 Design of HALF-SUBTRACTOR QCA circuit

4.12 Design of FULL-SUBTRACTOR QCA circuit

4.13 Design of 2:1 Mux

4.14 Design of 4:1 Mux

4.15 Design of FEYNMAN

4.16 Design of TOFFOLI

4.17 Design of CNOT

4.18 Design of MULTIPLIER block

4.19 Design of 2-bit FULL-ADDER block

Chapter 5. Implementation
5.1 Create QCA layout using QCA designer 37

5.2 Way to simulate 38

5.3 Clocking to a block

5.4 Crossover

5.5 Storing QCA layout

5.6 Sample layout 44

Chapter 6. Results and Discussions 46

6.1 Comparison of performance 49

Chapter 7.Conclusion 50
REFERENCES 51
APPENDIX-I
 APPENDIX-II
APPENDIX-III
APPENDIX-IV

List of Figures
Figure 3.1.1: Electron spin 2
Figure 3.3.1 QCA Cell Dimension 16
Figure 3.3.2 QCA Cell with Tunnel Junction 18
Figure 3.4.1 Two Cell Polarization P= -1 (Binary 0) & P= +1 (Binary 1) 18
Figure 3.5.1 QCA Clocking 21
Figure 3.6.1. Non-Linear Cell to Cell Response 21
Figure 3.7.1.1. Schematic Interaction of state propagation flow direction 22
Figure 3.7.1.2. QCA Straight Wire or 90-degree wire 22
Figure 3.7.2.1. QCA 45-Degree Wire 23
Figure 3.7.2.2. 45-Degree Wire Ripping of Binary 1 and Binary 0 23
Figure 3.8.1.1 Single layer wire crossing 23
Figure 3.8.2.1 Multilayer wire crossing 24
Figure 3.8.3.1 Logical wire crossing 25
Figure 4.1.1 (a) The basic QCA Majority gate (b) Schematic symbol and 25
Truth table of Majority gate
Figure 4.2.1 AND gate Truth Table 26
Figure 4.2.2 AND gate QCA Design 27
Figure 4.2.3 AND gate Simulation Result 27
Figure 4.3.1 OR gate Truth Table 28
Figure 4.3.1 OR gate Truth Table 28
Figure 4.3.3 OR gate Simulation Result 29
Figure 4.4.1 NAND gate Truth Table 30
Figure 4.4.2 NAND gate QCA Design 31
Figure 4.4.3 NAND gate Simulation Result 31
Figure 4.5.1 NOR gate Truth Table 32
Figure 4.5.2 NOR gate QCA Design 32
Figure 4.5.3 NOR gate Simulation Result 32
Figure 4.6.1 NOT gate Truth Table 33
Figure 4.6.2 NOT gate QCA Design
Figure 4.6.3 NOT gate Simulation Result
Figure 4.7.1 EX-OR gate Truth Table
Figure 4.7.2 EX-OR gate QCA Design
Figure 4.7.3 EX-OR gate Simulation Result 38
Figure 4.8.1 EX-NOR gate Truth Table 42
Figure 4.8.2 EX-NOR QCA Design 40
Figure 4.8.3 EX-NOR Simulation Result 41
Figure 4.9.1 HALF-ADDER Truth Table 42
Figure 4.9.2 HALF-ADDER QCA Design 43
Figure 4.9.3 HALF-ADDER Simulation Result 43
Figure 4.10.1 FULL-ADDER Truth Table 46
Figure 4.10.2 FULL-ADDER QCA Design 46
Figure 4.10.3 FULL-ADDER Simulation Result 47
Figure 4.11.1 HALF-SUB Truth Table
Figure 4.11.2 HALF-SUB QCA Design
Figure 4.11.3 HALF-SUB Simulation Result
Figure 4.12.1 FULL-SUB Truth Table
Figure 4.12.2 FULL-SUB QCA Design
Figure 4.12.3 FULL-SUB Simulation Result
Figure 4.13.1 2:1 MUX Truth Table
Figure 4.13.2 2:1 MUX QCA Design
Figure 4.13.3 2:1 MUX Simulation Result
Figure 4.14.1 4:1 MUX Truth Table
Figure 4.14.2 4:1 MUX QCA Design
Figure 4.14.3 4:1 MUX Simulation Result
Figure 4.15.1 Feynman gate Truth Table
Figure 4.15.2 Feynman gate QCA Design
Figure 4.15.3 Feynman gate Simulation Result
Figure 4.16.1 Toffoli gate Truth Table
Figure 4.16.2 Toffoli gate QCA Design
Figure 4.16.3 Toffoli gate Simulation Result
Figure 4.17.1 CNOT gate Truth Table
Figure 4.17.2 CNOT gate QCA Design
Figure 4.17.3 CNOT gate Simulation Result
Figure 4.18.1 Multiplier QCA Design
Figure 4.18.2 Multiplier Simulation Result
Figure 4.19.1 2-Bit Full-adder Truth Table
Figure 4.19.2 2-Bit Full-adder QCA Design
Figure 4.19.3 2-Bit Full adder Simulation Result
Figure 5.1 QCA Designer Window
Figure 5.1.1 QCA WIRE
Figure 5.1.2 Majority gate
Figure 5.1.3 Inverter
Figure 5.2.1 Simulation engine setup
Figure 5.2.2 Bistable approximation
Figure 5.3.1 Clock zone
Figure 5.3.2 NAND gate with clocking
Figure 5.4 Single layer Crossover
Figure 5.5 Storing QCA Layout
Figure 5.6.1 Sample layout

LIST OF TABLES

Table 6.1 Comparison of performance 48

 LIST OF ABBREVIATIONS

ALU Arithmetic and Logic Unit

CMOS Complementary Metal Oxide Semiconductor
IC Integrated Circuit
ITRS International Technology Roadmap for Semiconductors
MG Majority Gate
QCA Quantum-dot Cellular Automata
VLSI Very Large Scale Integrated