Report Ravi

B.M.S.
COLLEGE OF ENGINEERING
BENGALURU-560019
Autonomous institute, affiliated to VTU
A Project Report on
“PROGRAMMABLE HIGH FREQUENCY MULTI MODULUS
FREQUENCY DIVIDER”
Submitted in partial fulfilment of the requirement for the award of the degree of
MASTER OF TECHNOLOGY
in
ELECTRONICS
by
MAMATHA B
R 1BM19LEL10
Under the guidanceof
Dr. VEENA M B
Associate Professor
Dept. of ECE, BMSCE
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
B.M.S. COLLEGE OF ENGINEERING

Autonomous Institute, affiliated to VTU
Bull Temple Road, Bengaluru-19
2020 – 2021
B.M.S COLLEGE OF ENGINEERING
Autonomous institute, affiliated to VTU
Bull Temple Road, Bengaluru-19
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
CERTIFICATE
Certified that the Project work emitted “PROGRAMMABLE HIGH FREQUENCY MULTI MODULUS
FREQUENCY DIVIDER” is a bonofide work carried out by Mx. MAMATHA .B R, (l BM19LEL10), in
partial fulfilment for the award of degree of Master of Technology in Electronics of the Visveswaraya
Technological U•iircrsity, Belagavi during the academic year 2020-2021. It is certified that all
confections/suggestions indicated for internal assessment have been incorporated in the report deposited in tbe
departmental library. The project report has been approved as it satisfies the ecadcaiicequirements in respect of
project work prescribed for the s£iiddegree.
Signature of Guide
Or. VeenaM. B
OfPrincipal
at
Name of the project examiners:
I:
2:
DECLARATION
I, Mamatha B R (1BM19LEL10), hereby declare that the project work entitled

“Programmable high frequency multi modulus frequency divider” has been
independently carried out by me under the guidance of Dr. VEENA M.B, Associate
Professor, Dept. of Electronics and Communication Engineering, BMS College of
Engineering, Bengaluru, in partial fulfilment of the requirements of the degree of Master
of Technology in Electronics of Visvesvaraya Technological University, Belagavi.
I further declare that I have not submitted this report either in part or in full to any other
university for the award of any degree.
Place:Bengaluru MAMATHA B R
Date:04-Aug-2021 1BM19LEL10
ACKNOWLEDGEMENT
I would like to take this opportunity to express my sincere gratitude and deep regards to
Dr. B V Ravi Shankar, Principal, BMS College of Engineering, Bengaluru, for allowing
me to undertake this project at BMSCE, Bengaluru.
I would like to thank Dr. Arathi R Shankar, Associate Professor and Head, Department
of Electronics and communication Engineering, BMS College of Engineering, Bengaluru,
forprovidingmeanopportunitytocarryoutthisprojectworkandhersupportandguidance.
My deep sense of gratitude to my internal guide Dr. Veena M.B, Associate Professor,
DepartmentofElectronicsandcommunicationEngineering,BMSCollegeofEngineering,
Bengaluru, for her valuable time and guidance and precious suggestions regarding the
project.
I also thank my family and friends for their constant help and support during my academic
endeavours.
Mamatha B R
ABSTRACT
The increasing amount of data traffic in communication networks underscores

the significance of wideband transceiver design. The high-speed performance of a
transmitter or a receiver is primarily restricted by the bandwidth limitation of its circuit
blocks. One such circuit block is the clock divider, which is employed in nearly every
wirelessorwirelinetransceiver.Clockdividersarepredominantlyusedinsideapplications such
as phase-locked-loop based frequency synthesizers, in phase/quadrature down-
converters, channel equalizers, multiplexers and de-multiplexers, and clock-data recovery
circuits to name a few. Some of the key performance metrics used to characterize clock
dividers include its operating frequency range, input sensitivity, power consumption and
output powerlevel.
Clock dividers are widely considered as the speed limiting factor in
communication systems, which require a very fast settling frequency feedback loop and a
high-speed operating frequency synthesizer, This limitation is basically due to the
maximum operating frequency of the synchronous counter circuit, which is alleviated by
relying on an optimization structure and a high-speed technology Flip-Flop circuits.
Therefore,clockdividerwithlowpowerdissipationisnecessary.Themainaimofthiswork is to
design a clock divider with low power dissipation which is able to operate under low
supply voltage and at high frequency using 45nm CMOS technology. The 9.7 GHz clock
dividerisdesignedforadivisionratioofupto255at1volt.Thecomparisonresultsshows that the
proposed design achieves the best reported efficiency for a multi-modulus clock divider
operating at the lowest supplyvoltage.
Table of contents
List of Figures
List of Tables
List of Abbreviations
Chapter1.Introduction 1
1.1 Motivation 3
1.2 Problemstatement 3
1.3 Objective 4
1.4 Programoutcome addressed 6
Chapter 2.LiteratureSurvey 7
Chapter 3.BackgroundTheory 15
3.1 Electron spin 15
3.2 QCA solution 19
3.3 QCA basic cell
3.4 QCA polarization
3.5 QCA clocking
3.6 Cell to Cell response
3.7 QCA wires
3.8 Crossover
Chapter4.Methodology 20
4.1 Majority gate design 20
4.2 Design of AND gate 21
4.3 Designof OR gate 24
4.4 Designof NAND gate 26
4.5 Design of NOR gate 28
4.6 Design of NOT gate 30
4.7 Design of EX-OR gate 24

Table of contents
4.8 Design of EX-NOR gate 31
4.9 Design of HALF-ADDER circuit
4.10Design of FULL-ADDER QCA circuit
4.11 Design of HALF-SUBTRACTOR QCA circuit
4.12 Design of FULL-SUBTRACTOR QCA circuit
4.13Design of 2:1 mux
4.14Design of 4:1 mux
4.15Design of FEYNMAN
4.16Design of TOFFOLI
4.17Design of CNOT
4.18Design of MULTIPLIER block
4.19Design of 2-bit FULL-ADDER block
Chapter5.Implementation 37
5.1 Create QCA layout using QCA designer 37
5.2 Way to simulate 38
5.3 Clocking to a block
5.4 Crossover
5.5 Storing QCA layout
5.6 Sample layout 44
Chapter 6. ResultsandDiscussions 46
6.1 Comparisonof performance 49
Chapter7.Conclusion 50
REFERENCES 51
APPENDIX – I
APPENDIX – II
APPENDIX – III
Table of contents
APPENDIX – IV
List of Figures
Figure 3.1.1: Electron spin 2

Figure 3.3.1 QCA Cell Dimension 16
Figure 3.3.2 QCA Cell with Tunnel Junction 18
Figure 3.4.1 Two Cell Polarization P= -1 (Binary 0) & P= +1 (Binary 1) 18
Figure 3.5.1 QCA Clocking 21
Figure 3.6.1. Non-Linear Cell to Cell Response 21
Figure 3.7.1.1. Schematic Interaction of state propagation flow direction 22
Figure 3.7.1.2. QCA Straight Wire or 90-degree wire 22
Figure 3.7.2.1. QCA 45-Degree Wire 23
Figure 3.7.2.2. 45-Degree Wire Ripping of Binary 1 and Binary 0 23
Figure 3.8.1.1 Single layer wire crossing 23
Figure 3.8.2.1. Multilayer wire crossing 24
Figure 3.8.3.1 Logical wire crossing 25
Figure 4.1.1 (a) The basic QCA Majority gate (b) Schematic symbol and 25
Truth table of Majority gate
Figure 4.2.1 AND gate Truth Table 26
Figure 4.2.2 AND gate QCA Design 27
Figure 4.2.3 AND gate Simulation Result 27
Figure 4.3.1 OR gate Truth Table 28
Figure 4.3.1 OR gate Truth Table 28
Figure 4.3.3 OR gate Simulation Result 29
Figure 4.4.1 NAND gate Truth Table 30
Figure 4.4.2NAND gate QCA Design 31
Figure 4.4.3 NAND gate Simulation Result 31
Figure 4.5.1 NOR gate Truth Table 32
Figure 4.5.2NOR gate QCA Design 32
Figure 4.5.3 NOR gate Simulation Result 32
Figure 4.6.1 NOT gate Truth Table 33
Figure 4.6.2 NOT gate QCA Design
Figure 4.6.3 NOT gate Simulation Result
Figure 4.7.1 EX-OR gate Truth Table
Figure 4.7.2 EX-OR gate QCA Design
Figure 4.7.3 EX-OR gate Simulation Result 38
Figure 4.8.1 EX-NOR gate Truth Table 42
Figure 4.8.2 EX-NOR QCA Design 40
Figure 4.8.3 EX-NOR Simulation Result 41
Figure 4.9.1 HALF-ADDER Truth Table 42
Figure 4.9.2 HALF-ADDER QCA Design 43
Figure 4.9.3 HALF-ADDER Simulation Result 43
Figure 4.10.1 FULL-ADDER Truth Table 46
Figure 4.10.2 FULL-ADDER QCA Design 46
Figure 4.10.3 FULL-ADDER Simulation Result 47
Figure 4.11.1 HALF-SUB Truth Table
Figure 4.11.2 HALF-SUB QCA Design
Figure 4.11.3 HALF-SUB Simulation Result
Figure 4.12.1 FULL-SUB Truth Table
Figure 4.12.2 FULL-SUB QCA Design
Figure 4.12.3 FULL-SUB Simulation Result
Figure 4.13.1 2:1 MUX Truth Table
Figure 4.13.2 2:1 MUX QCA Design
Figure 4.13.3 2:1 MUX Simulation Result
Figure 4.14.1 4:1 MUX Truth Table
Figure 4.14.2 4:1 MUX QCA Design
Figure 4.14.3 4:1 MUX Simulation Result
Figure 4.15.1 Feynman gate Truth Table
Figure 4.15.2 Feynman gate QCA Design
Figure 4.15.3 Feynman gate Simulation Result
Figure 4.16.1 Toffoli gate Truth Table
Figure 4.16.2 Toffoli gate QCA Design
Figure 4.16.3 Toffoli gate Simulation Result
Figure 4.17.1 CNOT gate Truth Table
Figure 4.17.2 CNOT gate QCA Design
Figure 4.17.3 CNOT gate Simulation Result
Figure 4.18.1 Multiplier QCA Design
Figure 4.18.2 Multiplier Simulation Result
Figure 4.19.1 2-Bit Full-adder Truth Table
Figure 4.19.2 2-Bit Full-adder QCA Design
Figure 4.19.3 2-Bit Full adder Simulation Result
Figure 5.1 QCA Designer Window
Figure 5.1.1 QCA WIRE
Figure 5.1.2 Majority gate
Figure 5.1.3 Inverter
Figure 5.2.1 Simulation engine setup
Figure 5.2.2Bistable approximation

Figure 5.3.1 Clock zone
Figure 5.3.2 NAND gate with clocking
Figure 5.4 Single layer Crossover
Figure 5.5 Storing QCA Layout
Figure 5.6.1 Sample layout
List of tables
Table 6.1 Comparisonof performance 48
Design of ALU using Quantum dot cellular automat
List of Abbreviations
PLL Phase Locked Loop

CMOS Complementary Metal Oxide Semiconductor
MCD Multiple Clock Domain
VCO Voltage Controlled Oscillator
RX Receiver
TX Transmitter
IC Integrated Circuit
LO Local Oscillator
FSM Finite State Machine
SoC System on Chip
CHAPTER 1
INTRODUCTION
In 1965, Gordon Moore predicted that the number of transistors that can be
integrated on to a single chip will double in every 18 months [1]. This made a benchmark
in semiconductor scaling for more than four decades. Since the scaling is fast approaching
its fundamental limits, the IC industry which has to look into other alternatives other than
CMOS scaling. The size limit of CMOS technology will be limited to about 5-nm to 10-
nm as predicted by the International Technology Roadmap for Semiconductors (ITRS).
CMOS ICs have become irreplaceable in daily life products, ranging from portable
electronics to telecommunications and transportations. The effects of scaling CMOS
devices by shrinking transistor dimensions has made reducing power supply voltages and
increasing operating frequencies. Such shrinking transistor results in a series of non-ideal
behaviour such as high leakage current and high-power density levels. Computer chips
have become ever cheaper, smaller, power-efficient, and at the same time much more
capable, due to the incredible success of the Complementary Metal Oxide Semiconductor
(CMOS) integrated circuits. But there is a growing concern that CMOS is close to its
scaling limits that it can no longer become ever faster and cheaper. The size approaches
the atomic scale and further reduction in size makes the fundamental physical limits of
CMOS. This affects the gate electrode, making it unable to control the potential
distribution and the flow of current in the channel region. The challenges faced by the
CMOS lithography-based technology are power consumption, physical dimensions,
leakage currents and doping fluctuations. The expensive lithography and increasingly
difficult has made the researchers to find new alternatives in nano-meter regimes. So,
researchers are seeing nanotechnology as an alternative. Because of the high device
densities and low power consumption in nanotechnology, it could potentially replace
CMOS. To surpass the CMOS technology, more research has been conducted in recent
years at nano-scale. These devices might have a device density of 1012 devices/cm2, low
power and operating frequencies in Tera Hertz [2]. In this direction Quantum-dot Cellular
Automata (QCA) is a good competitor for research domain and a rising innovation. It is a
Dept. of ECE, BMSCE 13

new method of digital computation and appears to be implementing a possible alternative

nanotechnology. Because of its high device density, extremely low power consumption
and very high switching speed, QCA has received significant attention in recent years.
QCA will play an influential role in next generation computing systems, with its
efficiency in structure and power consumption. It is predicted that size of the QCA will be
of few nano-meters. Quantum mechanics is a branch of science dealing with the
behaviour of matter and light on the atomic and subatomic scale. It describes and account
for the properties of molecules and atoms and their constituents-electrons, protons,
neutrons. These properties may be the interactions of the particles with one another and
with electromagnetic radiation (i.e., light, X-rays, and gamma rays).
The results of quantum theory are accordingly difficult to understand and to believe.
Its derived observations of the everyday world concepts frequently conflict with
common-sense notions. It is impossible to find the reason, why the behaviour of the
atomic world should conform to that of the familiar, large-scale world. It is important to
know that quantum mechanics is a branch of physics and that the business of physics is
to describe and account for the way the world, on both the large and the small scale.
Quantum chemistry is the branch or application of quantum mechanical principles

and equations to the study of molecules. We must use quantum mechanical models and
methods in order to understand matter at its most fundamental level. Quantum mechanics
may be defined in two different ways that make it different from previous models of
matter. Wave-particle duality is the first concept; that is, small objects (such as electrons)
having characteristics of both particles and waves. Second, quantum mechanical models
tell that the energy of atoms and molecules is always quantized, meaning that they may
have only specific amounts of energy. Quantum chemical theories define the structure of
the periodic table, and quantum chemical calculations help us to predict the
spectroscopic behaviour of atoms and molecules, and structures of molecules.
Classical Computer:
 Classical computer use transistor to represent bits which take either of two values – 0
or 1.
 It stores information bits based on voltage or charge etc…
 It uses logic gates for processing information e.g. NOT, OR, AND etc...
Quantum Computer:
 Quantum computer can either take value of 0 or 1or both simultaneous in a state of
superposition, these values are known as qbits.
 It stores information qbits on direction of electron spin.
 It uses Quantum logic gates for processing information.
1.1 MOTIVATION
 Current transistor based semiconductor devices are becoming resistant to scaling.
 Due to the decreasing supply voltage, the power consumption from leakage current
is a big challenge for transistor circuits.
 CMOS Technology does not operate at 1 Terahertz.
 Since the rapid advancement of technology in the fields of real-time signal
processing, communication, multimedia and image processing etc. the high speed
computing architectures are needed.
 To overcome the conventional CMOS technology drawbacks, nanotechnology based
quantum cellular automata (QCA) is the best candidate.
1.2 PROBLEM STATEMENT

“Design of functional blocks for ALU using Quantum dot cellular automata”
The problem statements compress the various design aspects:
 Efficient QCA logic gates and Boolean expression design.
 Analysis of minimum number of cell counts, cell area, Clock zone, delays in the
quantum gates.
 Finding the each cell area in quantum gates.
 Interpretation of quantum bits (Qbit) using various QCA tools.
 Comparative analysis with previous QCA work.
 Contribution to open source semiconductor ecosystem since this technology is still
under research topics so anyone can implement further reduction.
Rapid change in the field of technology and communication, multimedia, data

centre, signal processing etc requires the high speed computing architectures. In this
scenario CMOS technology (Transistor based) lacks in performance, size, and power
and does not operate very high frequency. With this transistor technology lacks in the
computation speed. Alternative technology is quantum computing automata (QCA) that
can replace transistor completely and having greater advantage in high performance,
high computational speed, low power consumption and less delay. Problem statement
defines that QCA based efficient functional blocks design for ALU with comparative
analysis of previous work with consideration of area taken of each cells in the circuit,
number of cells used in the circuit, power dissipation.
1.3 OBJECTIVE
 The principle objective is to have research on the latest nano technology.
 To inter-relate theoretical aspects learnt as a part of theory with that of practical.
 Exploration new tools in QCA technology that effectively contributes the
semiconductor ecosystem.
 Comparison of the designed QCA blocks in terms of number of cell counts, Area of
cell and Clock delay with previous work.
 Contribution to open source since quantum is wide research area open source helps
us to learn very quickly
1.4 PROGRAM OUTCOMES ADDRESSED

The project work addresses a number of Program Outcomes (PO) as discussed below.
 Working on the project gave me an in-depth understanding of the complete
Quantum cellular automata (QCA) design flow in nanotechnology. IC design and
flow followed at industry level and latest features adopted by industry tools.
 (PO1) analysing a suitable problem statement is very critical aspect and requires
analysing the current engineering problems in semiconductor ecosystem. The
solution to the problem is found by looking at various possible solutions as per
industry standards and choosing the feasible solution one that suits the requirements.
 (PO1) A literature survey performed helped in identifying the metrics that need to be
considered for design the QCA based digital circuits for integrated circuit (IC) for
various real time applications. It gave an insight into the latest solutions proposed
and the strengths/drawbacks of each of them.
 (PO1, PO3) The conduction of reviews at each stage and submission of weekly
reports helped in the project management and scheduling. This helped in creating a
suitable plan and time management. Also, the reviews and presentations helped in
improving my oral and written communication skills. It helped in building my
confidence.
 (PO3) The project helped me in improving my technical and non-technical skills to a
great extent, which will help me in my future work life.
 (PO3)The end phase of the project is submission of a report. This phase helped me
in understanding the procedure that is to be followed to write a manuscript for
submission to journal and to write a technical report in the given format(PO2)

CHAPTER 2
LITERATURE SURVEY
[4] Kavitha S S, NarasimhaKaulgud, “Quantum-dot cellular automata design for the

realization of basic gates,” ICEECCOT, 2017.
In this paper authors have proposed mainly the implementation and simulation results of
various logic gates using QCA Designer tool and also implemented the majority gate
architecture and author have done Comparative analysis of QCA design and CMOS is
carried to measure performance analysis in terms of covered area (size), number of cell
counts in a design and clock phase of delay of each cell. CMOS software tools like
schematic editor (Dsch3) and layout editor (Microwind) are used to design of all
realized logic gates. In this paper author has implemented many qca gates in that xor
and xnor they are performed area (0.0305), cell counts (29) and area (0.426), cell counts
(33) respectively.
GAP: Author has mentioned XOR and XNOR qca gate design with area and number of
cell counts information. With that numerical information we can still reduce the area of
cell and number of cell count in the design based on the majority gate, since majority
gate acts as universal gate.
[5] Suman Rani, TrilokayaNathSasamal “Design of QCA Circuits Using New 1D

Clocking Scheme,” TEL-NET, 2017.
In this paper author proposed clocking scheme for Quantum-dot Cellular Automata
(QCA) designs, this 1D clocking scheme utilizes only single or regular (900) cells for
circuit design. This scheme is based on 1D clocking scheme and aim is to provide
crossing and information flow with only single or regular cells. Some Combinational
circuits such as Adders Half adder, Full adder, 2-Bit adder and 4-Bit adder are designed

using proposed 1D clocking scheme with only regular cells (900). Various clocking
schemes (1D, 2D and 2D-wave clocking schemes) which are used to solve these issues.
These schemes are uses both rotated cells and regular cells for data transformation and
crossing but to solve these issues we can also use only regular cells. QCA cells are of
two types one is Regular and another is Rotated cell. For coplanar crossings rotated cells
are used. QCA wire is a set of cells and these cells are arranged adjacent to each other in
a chain. . In this paper author has implemented many qca circuits in that FULL ADDER
and HALF ADDER design they are performed area (0.58), cell counts (264), 12 phases
clocking with delay of 3 and area (0.14), cell counts (72), 5 phases clocking with delay
of 1.25 respectively.
GAP: Observed the drawback of clocking during the fabrication, there is a possibility of
“cross-coupling” between the two wires of 900 and 450, when arrangement of any cells
is misaligned. But there is no misalignment when only single cells are used. And studied
about various qca clocking scheme we can apply to the design likes 1D, 2D.
Consideration of above design full and half adder, still we can improve the performance
of design by reducing the area of cell, number of cell count and clocking delay.
[6] RubinaAkter, NasrinJahan, Md. Mamunur Rashid Shanta, AnikBarua “A Novel

Design of Half Subtractor using Reversible Feynman Gate in Quantum Dot
cellular Automata,” American Journal of Engineering Research (AJER), 2014.
In this paper author implemented combinational circuit (half subtractor) using reversible
Feynman gate in quantum dot cellular automata. Reversible logic gates are the leading
part in Quantum Dot cellular Automata. Reversible logic gates have an extensive feature
that does not lose information with four states. This half subtractor circuit is designed
based on QCA logic gates such as QCA majority voter gate, majority AND gate,
majority OR gate and inverter gate. This circuit will provide an effective working
efficiency on computational units of the digital circuit system. The proposed work is
more efficient in terms of cell counts (114), area (0.20) and the time delay (0.75).
Gap: Observed how reversible logic gates implemented in QCA and half subtractor
design parameters like cell count, area, time delay of the circuit. There is a significant
reduction in the area of the cells and number of cell counts.
[8] Angshuman Khan, SiktaMandal, “Elimination of Static Hazard in 2:1 Multiplexer

using Quantum dot Cellular Automata,” IEEE 2016.
In this article, tatic hazard has been focused for QCA circuit where 2:1 multiplexer is
the experimental object. Both the hazardous and hazard-free multiplexers have been
designed. A digital multiplexer (MUX) is a digital switch. It allows information from
several sources to be routed onto a single output. Hazard free QCA circuit according to
the K-Map has been designed. According to the K-Map, an extra redundant term ‘AB’ is
to be added to the circuit. To realize that additional term in QCA; two additional
majority gates are required. One majority gate acts as an AND gate between A and B
and another one is used as OR gate between BS and AB.
Gap: Presented 2:1 Multiplexer design occupies more number of cells, more clock delay
phase and area taken to design is huge. By carefully observing this work we can
improve the design parameters.
[9] Heumpil Cho, “Adder and Multiplier Design in Quantum-Dot Cellular Automata,”
IEEE TRANSACTIONS ON COMPUTERS, 2009.
In this paper unique QCA characteristics to design a carry flow adder that is fast and
efficient with simulations parameters indicate very attractive performance like
complexity, area and delay. This paper also explores the design of serial parallel
multipliers. Carry flow adders use a basic ripple carry propagation scheme that is
optimized for layout in the QCA technology. A 1-bit full adder is designed. The input
bit streams flow downward and the carry propagates from right to left. The wiring
channels for the input and output synchronization should be minimized since wire
channels add significantly to the circuit area. The carry flow full adder requires a
vertical offset between the carryin and carry-out of only one cell. Multiplier design in
QCA implemented with area of 0.22 um2, number of cell used 164 and with clock phase
4 delay of 1.
GAP: Observed adder and multiplier functionality of circuit, implemented design
requires a 4 clock delay phases it will leads to the number of cell counts. Area of cell
and number of cells further we can reduce by using majority gate.
[10] J. Timler, C. S. Lent, Power gain and Dissipation in QCA, J. Appl.phys., 2002.
Power gain and dissipation in quantum-dot cellular automata, author as proposed

theoretical for power estimation based on the density of matrix formalism, which
permits examination of energy flow in QCA devices. Using a simple two-state model to
describe the cell, and an energy relaxation time to describe the coupling to the
environment, we arrive at an equation of motion well suited to the quasi-adiabatically
switched regime.For a single QCA cell using a two-state basis composed of the two
completely polarized states with polarization P=+1 and P=-1. The two-state
approximation can be obtained from a more rigorous microscopic Hamiltonian. For an
array of cells we use the intercellular Hartree approximation described .This entails
treating the Coulombic interaction between cells by a mean-field approach. Quasi
adiabatic clock switching of a single cell is accomplished by applying an input signal
modelling the polarization (P=+1 and P=-1) of neighboring cells and gradually changing
the effective switching barrier. Each of these actions has the effect of changing the
Hamiltonian vector.
[11] W.Porod, “Quantum-dot Devices and QCA”, Journal of Franklin Institute, 1997.
Authors discuss about the how cells will be viewed as carrying analog information and
network-theoretic description of such Quantum-Dot Nonlinear Networks (Q-CNN).
Along with that, discuss possible realizations of these structures in a variety of
semiconductor systems (including GaAs/AlGaAs, Si/SiGe, and Si/ SiO2), rings of
metallic tunnel junctions, and candidates for molecular implementations. Consider a
QCA array before the start of a computation. The array, left to itself, will have assumed
its physical ground state. Presenting the input data, setting the polarization (P=+1 and
P=-1) of the input cells, will deliver energy to the system, thus promoting the array to an
excited state. The computation consists in the array reaching the new ground state cell
configuration, compatible with the boundary conditions given by the fixed input cells.
Edge driven of cells computation means that only the periphery of a QCA array can be
contacted or interconnection of cells, which is used to write the input data and to read
the output of the computation with clocking phases. No internal cells may be contacted
directly. This implies that no signals or power can be delivered from the outside to the
interior of an array of cell. All interior cells only interact within their local
neighbourhood. The absence of signal and power lines to each and every interior cell
has obvious benefits for the interconnect problem and the heat dissipation.

[13] A. Gin, P.D. Tougaw and S. Williams, “An Alternative Geometry for QCA”, J.
Apllied Physics, 1999.
Authors here have presented alternative geometry for quantum-dot cellular automata.
Earlier quantum cellular automata devices has restricted the only cells to a single plane
and discussed noncoplanar arrangement in quantum dot cellular devices this method
effectively overcomes the disadvantages of single plane. These noncoplanar crossing
models are found to be capable of implementing the same logical functions as
conventional quantum cellular automata cells, and they typically require 50% of the area
required by the conventional devices. Implementing noncoplanar cells will be more
challenging than the implementing coplanar cells. However, it is important to notice that
even though the cells presented here are noncoplanar, they are biplanar. That is to say
that all the quantum dots in all the cells of each device exist in one of two planes. As
suggested by their biplanar nature, the cells would be implemented in these two nearby
2DEGs, with tunnelling permitted between the planes. Lateral confinement in the cell
would be provided by a gate above both planes. This noncoplaner arrangement is
approximately 2.5 times as large as the energy for a polarization (P=+1 and P=-1)
discontinuity in the system

CHAPTER 3
BACKGROUND THEORY
3.1 ELECTRON SPIN
In 1925, S.A. Goutsmit and G.E. Uhlenbeck, proposed that an electron has an
inherent angular momentum that is a magnetic moment which is recognized as spin. In
atomic physics, the inherent angular momentum of an electron is parametrized by spin
quantum number. The fourth number is the spin quantum number. The other three are a
principal quantum number, azimuthal quantum number and magnetic quantum number.
The unique quantum state of an electron is explained by the spin quantum number. This is
denoted as ‘s’.
The Spins plays a important role in quantum mechanics in computing the

characteristics of elementary units like an electrons. The direction of spin of an electron
regulates several things like spin quantum number, angular momentum, the degree of
freedom etc.. The electron spin describes the electron as quantum particle where as in
classical theory it is just a sphere.

Fig. 3.1.1 Electron Spin
The electron can spin two directions:
 Spin up
 Spin down
The spin up and spin down direction are in the +z or –z direction. These spins (spin up
and spin down) have s value equal to ½ for electrons.
In the quantum theory, the electron is assumed as the minute magnetic bar and its spin
points the north pole of the minute bar. If two adjacent electrons have a similar spin
direction, the magnetic field formed by them strengthens each other and therefore a strong
magnetic field is gained. If the adjacent electrons have an opposite spin direction, the
magnetic field formed by them cancels each other and no magnetic field is existent.
If the adjacent electrons have an opposite spin direction, the magnetic field formed by
them cancels each other and no magnetic field is existent.
3.2. QCA SOLUTION

Because of QCA property of high device density, extremely low power consumption,
diminutive size and faster switching speed, Quantum-dot Cellular Automata (QCA) has
received significant attention in recent years, as an alternative of CMOS technology.
QCA transfers information by propagating a polarization state, while conventional
computers in which information is transferred from one place to another by means of
electrical current.
QCA encodes binary information in the form of charge configuration within

Quantum-dot cells. Coulombic interaction provides the Computational power between
QCA cells. Neither the current flows between cells nor power or information is delivered
to internal cells. The cell-to-cell interaction provides the interconnection between QCA
cells, due to the rearrangement of electron positions. The two electrons are residing in
opposite sides due to the coulombic interaction in Quantum-dots of a QCA cell.
The movement of mobile electrons in a QCA cell to different Quantum-dots will be

by means of electron tunnelling. The electron which reside in cell, called “Quantum
Dots”. It represents the locations where the electrons can occupy. Tunnel junctions
couples the dots. the lines connecting the Quantum-dots represents Tunnelling paths. This
small size makes the electron to exhibit quantum mechanical properties.
3.3. QCA Basic Cell

A cell is a basic building block in QCA. The logical bit representation in QCA cell is
done through an appropriate configuration of charge. Each cell consists of four charge
carriers arranged in corners of a cube known as quantum dots. A single QCA cell consists
of 4 quantum dots which are aligned near four corners. The uniform size of the QCA cell
is 18x18nm having dot size of 5nm, the distance between quantum dots is 8 nm as shown
in the Fig. 3.3.1. The distance between two adjacent cells from their centre is in the order
of 2 nm. It is because electrons of neighboring cells must be separate by a larger distance.

Fig. 3.3.1 QCA Cell Dimension
In QCA cells, logic states are stored depending on the position of individual
electrons, but not based on voltage levels. If two electrons are injected and locked inside
the cell it’s gets align based on the columbic force of repulsion between them and allowed
them move between quantum dots [10]. The potential wells are linked through the
electron tunnel junctions as shown in Fig. 3.3.2. The tunneling of electrons between the
potential dots is achieved by the application of the suitable potential.
Fig. 3.3.2 QCA Cell with Tunnel Junction
3.4. QCA Polarization

A QCA cell can be represent in binary with a specific polarization which is denoted as
“P”. In this there are two polar states for each QCA cell. These two stable states are formed
because of Columbic repulsion between electrons which are denoted by a polarization, P = -1
for logic 0 and P = +1 for logic 1 as shown in Fig. 3.4.1. Apart from polarized state, they also
have unpolarized state having low inter-dot potential barriers which results in reduction in
confinement of the electrons on the individual Quantum-dots.

Fig. 3.4.1 Two Cell Polarization P= -1 (Binary 0) & P= +1 (Binary 1)
The individual single cell can be configure as normal cell, fixed polarization cell,
input cell or output cell as required for the application. A normalcell function is to switch
according to the influence of neighbouring cells. A fixedpolarization cell will retain in the
same state, its state doesn’t affects by the neighbouring cells or the clock. Input cells will
have polarization value based on the requirement. Output cells is like normal and they are
directly influenced by their neighbouring cells. If these cells arranged in a row wise or
column wise will form wire like structure which is helpful in propagation of data.
3.5. QCA Clocking

The clock is the main important reason for propagation of information in the QCA
circuits. It controls and maintains the information flow, provides synchronization in the
circuit and avoids formation of meta-stable. Meta-stable is one that corresponds to
polarization of a cell that is intermediary between logic 1 or logic 0 and it cannot be
distinctively identified as logic 1 or logic 0. The polarization is neither strongly -1 nor +1
in meta-stable state. The clock in QCA technology is different than the clock in CMOS, it
consists of four phases:
 Switch phase- In this phase input is given to some unpolarized cells and get
polarized depending on their neighbor’s polarization.
 Hold phase- In this phase cells will hold some definite polarization representing
a binary state.
 Release phase- In this phase cells lose their polarization.
 Relax phase- In this phase cells will remain unpolarized or null.
Each of these clock phases is a quarter of cycle apart from the previous phase, which
is implemented by generating four clocks each with π/2 phase difference from previous
one. The four phases of a QCA clock are shown in Fig. 3.5.1.
 Green Color Cells indicates Clock 0.
 Pink Color Cells indicates Clock 1.
 Light Blue Color Cells indicates Clock 2.
 White Color Cells indicates Clock 3.

 Orange Color Cells indicates Polarization.
 Dark Blue Cells indicates Input.
 Yellow Color Cells indicates Output.
Fig. 3.5.1 QCA Clocking
3.6. Cell to Cell Response

The cell-to-cell response function is shown in Fig. 3.6.1. It shows that the nature of
the interaction is highly non-linear in nature i.e. a weak polarization in one cell influences
a strong polarization in the neighbouring cell. This confirms that, if cells are arranged
linearly like a wire, if the input or any of the other intermediate cells has a weak
polarization, the next adjacent cell would still get strongly polarized. This acts as a buffer
storing a value for the corresponding supply voltage. This is helpful for defect tolerance
in QCA circuits because if one cell did not get polarized strongly irrespective of
placement-issues but still may results in strong polarization [11].

Fig. 3.6.1. Non-Linear Cell to Cell Response
3.7. QCA Wires

For signal propagation in QCA circuits wires play a vital role. A wire can be used
to propagate signal from input to the output. The information transmission in a QCA wire
takes place by Columbic force. When an input is applied to the input cell, the binary
information propagates from left to the right due to the Columbic repulsion between the
electrons of neighboring cells. When all cells in the wire settle down to their ground
states, they have the same polarization. Any cell along the wire that is anti-polarized with
the input would be at a higher energy level, and would soon settle down to the correct
ground state. A number of methods have been explored to tackle the problem of wire
crossings in QCA.
3.7.1. QCA Standard Wire (90-degree)

Single-layer wire crossing is achieved by using two types of QCA cells (standard
90-degree and 45-degree), that are orthogonal to each other. Standard 90- degree wire can
be obtained by placing QCA cells side-by-side [11]. This means a grid of QCA cells is
used to propagate the signal in QCA which acts as a wire. Fig. 3.7.1.1. Schematically
illustrates how a binary value propagates down the length of a QCA “wire”. In this
Figure, the wire is a horizontal row of QCA cells. The binary signal propagates from left-
to-right because of the Columbic interactions between adjacent cells.

Fig. 3.7.1.1. Schematic Interaction of state propagation flow direction.
To understand the signal propagation in straight wires (90°), assume in Fig.

3.7.1.2., cell 1 has a polarization P = -1 and cell 2 has polarization P = +1. We assume
that charges in cell 1 are trapped in polarization P = - 1 but those in cells 2-7 are not.
Therefore, there is no chance that the wire could “reverse directions” and have a
polarization propagate in the direction from which it initiated. A binary 0 (from
polarization P = -1) will propagate down the length of the wire because of the Coulombic
interactions between cells. Initially, the electron repulsion caused by Coulombic
interaction that exist between cell 1 and cell 2 will cause cell 2 to change polarizations.
Then, the electron repulsion that exist between cell 2 and cell 3 will cause cell 3 to change
polarizations. This process will continue down the length of the QCA “wire” till the
polarization change transverses to the last cell.
Fig. 3.7.1.2. QCA Straight Wire or 90-degree wire.
3.7.2. QCA Standard Wire (45-degree)

Standard 45-degree QCA wire comprises of cells oriented at 45-degree cells. It is
obtained by rotating the orientation of 90-degree. However, if a wire is formed using 45-
degree cells then it results in an Inverter chain as shown in Fig. 3.7.2.1. To understand the
signal propagation of 45-degree cells, assume that the input cell is at logic one (P = +1),
with the 45-degree orientation. As the binary value propagates down the length of the
wire, it alternates between polarization P = +1 and polarization P = -1, alternatively. An
inverted or un-complemented value can be ripped off the wire by placing a ripper cell at
the proper location considering the direction of signal propagation. The significant
advantage of the 45-degree wire is that both the transmitted value as well as its
complement can be obtained from a wire [11]. An illustration of a value being transmitted
on a 45-degree wire and an example of ripping off a value from the wire is shown in Fig.
3.7.2.2.
Fig. 3.7.2.1. QCA 45-Degree Wire
Fig. 3.7.2.2. 45-Degree Wire Ripping of Binary 1 and Binary 0

3.8. CROSSOVERS
3.8.1. Direct Single Layer Wire Crossing (Coplanar Wire Crossing)
Single layer crossing is implemented in one layer using both 45-degree and 90-
degree QCA cells, each one dedicated to one side of a crossing. These cells can pass over
the crossing without any significant effect on each other. Fig. 3.8.1.1. Depicts a Single
layer crossing mechanism. The first wire has only direct cells (non-rotating) and the
second wire has only rotating cells. It is based on the observation that, when placed in
line, 45-degree and 90-degree cells do not affect each other’s state. The two wires are
orthogonal to each other. This leads to the coupling between the two 90-degree cells at
the intersection, though they are one cell apart. Therefore, they can operate
independently. Apparently, this coupling is somewhat weaker than it would have been in
a normal wire, resulting into lesser probability of the scene of crossing. Being a never-
seen-before phenomenon offered by QCA, this efficient coplanar wire crossing has been
highly popular. However, it comes with issues of low robustness and fabrication
difficulties [12]. The weak coupling makes the crossing highly sensitive to physical
parameters like cell dimension, inter-cellular spacing, temperature etc. In spite of the
physical parameters being favourable, there are instances when a circuit with multiple
crossings may behave unexpectedly. Moreover, some researchers have tried to increase
the robustness of this wire crossing method.

Fig. 3.8.1.1 Single layer wire crossing
3.8.2. Multi-layer Wire Crossing

Multilayer wire crossing either 45-degree or 90-degree cells, one wire of the
crossing is transferred to the other layer and after passing through the crossing, the wire is
returned to the original layer back Fig. 3.8.2.1. Multi-layer wire crossing is achieved by
Multi-layer placement of QCA cells. In Multi-layer strategy the crossing will be done in
another layer, and could be implemented between two wires of the same cell type as long
as the vertical distance between the wires is enough to prevent leaked signal from one
layer to another and there is a scope to create stacked cells between the layers. This
method requires an implementation of multiple active QCA layers on the top of each
other. Multi-layer crossover gives better simulation results as well as performs smooth
operation for reliable data transmission [13].

Fig. 3.8.2.1. Multilayer wire crossing
3.8.3. Logical Wire Crossing
Logical crossing method utilizes only one type of QCA cells and is based on the
interference of clocking phases on each other. In this method cells on the switch phase
can cross over the cells on the release phase and the cells on the hold phase can cross over
the cells on the relax phase with no polarization effects on each other. In nutshell, when
the wires cross there should be the phase difference of 180-degree with each wire. The
logical wire crossing scheme is shown in Fig. 3.8.3.1. It is noteworthy that among these
methods, Logical Crossing enjoys high robustness, low circuit overhead, using one type
of cell, and compatibility with Single layer designs, which is one of the most significant
conditions for practical QCA circuits [14].

Fig. 3.8.3.1 Logical wire crossing
CHAPTER 4
METHODOLOGY
4.1 MAJORITY GATE DESIGN

In the Majority gate, computation is performed by driving the device cell, which is
the central cell as shown in Fig. 4.1.1(a). to its lowest energy state. This happens when it
assumes the polarization of the Majority of the three input cells (Input A, Input B, Input
C). We define input cell simply as one that is changed by a signal propagating in a
direction towards the device cell. The QCA cell will always assume the majority
polarization, because in this polarization repulsion between the electrons in the three
input cells and the QCA cell will be at a minimum. The schematic symbol and Truth table
of Majority logic gate is shown in Fig. 4.1.1(b).
The logic function of 3-input MG can be expressed in terms of Boolean functions
as:
Output MG (A, B, C) = MG (AB + AC + BC)
(a) (b)
Fig. 4.1.1 (a) The basic QCA Majority gate (b) Schematic symbol and Truth table of
Majority gate.
4.2 DESIGN OF AND GATE

Y = (a. b)
AND gate is designed using majority gate where two cells are input and one cell is output
and fixing one cell to polarisation -1 majority gate works as AND gate. All the cells in
Fig. 4.2.2 are in clock 0, Fig. 4.2.3 is the simulation result which satisfies the truth table
shown in Fig. 4.2.1 with 0 phase delay.
Fig. 4.2.1 AND gate Truth Table Fig. 4.2.2 AND gate QCA Design
Fig. 4.2.3 AND gate Simulation Result
4.3 DESIGN OF OR GATE

Y=a+b
OR gate is designed using majority gate where two cells are input and one cell is output
and fixing one cell to polarisation 1 majority gate works as OR gate. All the cells in Fig.
4.3.2 are in clock 0, Fig. 4.3.3 is the simulation result which satisfies the truth table
Fig. 4.3.1 OR gate Truth Table Fig. 4.3.1 OR gate Truth Table
Fig. 4.3.3 OR gate Simulation Result
4.4 DESIGN OF NAND GATE

Y = (ab)’
NAND gate is designed using majority gate and NOT gate where two cells are input and
one cell is output and fixing one cell to polarisation -1 majority gate works as AND gate
and then it is inverted by placing cell at 45 0. Output is in cell which is at clock 0 shown in
Fig. 4.4.2, Fig. 4.4.3 is the simulation result which satisfies the truth table shown inFig.
4.4.1 with 0 phase delay.
Fig. 4.4.1 NAND gate Truth Table Fig. 4.4.2NAND gate QCA Design
Fig. 4.4.3 NAND gate Simulation Result
4.5 DESIGN OF NOR GATE

y = (a + b)’
NOR gate is designed using majority gate and NOT gate where two cells are input and
one cell is output and fixing one cell to polarisation 1 majority gate works as OR gate and
then it is inverted by placing cell at 450. Output is in cell which is at clock 0 shown in Fig.
4.5.2, Fig. 4.5.3 is the simulation result which satisfies the truth table shown in Fig. 4.5.1
with 0 phase delay.
Fig. 4.5.1 NOR gate Truth Table Fig. 4.5.2NOR gate QCA Design
Fig. 4.5.3 NOR gate Simulation Result
4.6 DESIGN OF NOT GATE

y = a’ (not a)
NOT gate design in QCA is nothing but placing the cells in 45 0 which inverts the input
signal. Output is in cell which is at clock 0 shown inFig. 4.6.2, Fig. 4.6.3 is the simulation
result which satisfy the truth table shown in Fig. 4.6.1 with 0 phase delay.
Fig. 4.6.1 NOT gate Truth Table Fig. 4.6.2 NOT gate QCA Design
Fig. 4.6.3 NOT gate Simulation Result
4.7 DESIGN OF EX-OR GATE

Y = a’ b + b’ a or (a  b)
EX-OR gate is designed using 3 majority gates and NOT gates. One majority gate is OR
gate and other two are AND gates. Here input a given to one AND gate and its inverted
signal given to another AND gate similarly input b, and then the output of this 2 AND
gates are given to OR gate. Output is in cell which is at clock 2 shown in Fig. 4.7.2, Fig.
4.7.3 is the simulation result which satisfy the truth table shown in Fig. 4.7.1 with 3 phase
delay.
Fig. 4.7.1 EX-OR gate Truth Table Fig. 4.7.2 EX-OR gate QCA Design
Fig. 4.7.3 EX-OR gate Simulation Result
4.8 DESIGN OF EX-NOR GATE

Y = (a’ b + b’ a)’ or (a  b)’
EX-NOR gate is designed using 3 majority gates and NOT gates. One majority gate is
OR gate and other two are AND gates. Here input a given to one AND gate and its
inverted signal given to another AND gate similarly input b, and then the output of this 2
AND gates are given to OR gate and then it is inverted. Output is in cell which is at clock
2 shown in Fig. 4.8.2, Fig. 4.8.3 is the simulation result which satisfy the truth table
Fig. 4.8.1
EX-NOR gate Truth Table Fig. 4.8.2 EX-NOR QCA Design
Fig. 4.8.3 EX-NOR Simulation Result
4.9 DESIGN OF HALF-ADDER CIRCUIT

Sum(s) = a  b
Carry(c) = a.b
HALF-ADDER is designed using 3 majority gates and NOT gates. Majority gates are
OR, AND and NAND. Here inputs a and b are given to NAND gate and OR gate and
then output of this two given to AND gate which gives the sum and carry is taken before
AND gate output is inverted. Outputs are seen in cells which are at clock 2 shown in Fig.
4.9.2; Fig. 4.9.3 is the simulation result which satisfies the truth table shown in Fig. 4.9.1
with 3 phase delay.
Fig. 4.9.1 HALF-ADDER Truth Table Fig. 4.9.2 HALF-ADDER QCA Design
Fig. 4.9.3 HALF-ADDER Simulation Result
4.10 DESIGN OF FULL ADDER QCA CIRCUIT

Sum(s) = a  b  c
Carry(c) = abc
According to the truth table, the equations can be written as below
S=abc+ab’c+a’bc’+a’b’c
=M(M’(a,b,c),M(a,b,c’),c)
C=ab+bc+ca
=M(a,b,c).
According to the equation given above, full adder contains four majority gates.
The first majority gates are used to compute M(a,b,c) and M(a,b,c’). The output of first
majority gate is inverted. Again majority gate used to compute sum
S=M(M’(a,b,c),M(a,b,c’),c). Carry output is obtained by single majority gate as shown in
equation. The circuit contains 3 phase delay. The simulation output is shown in Fig.
4.10.3 which matches with the truth table Fig. 4.10.1 with 3 phase clock delay Fig 4.10.2.
Fig. 4.10.1 FULL-ADDER Truth Table

Fig. 4.10.2 FULL-ADDER QCA Design
Fig. 4.10.3 FULL-ADDER Simulation Result

4.11 DESIGN OF HALF-SUBTRACTOR QCA CIRCUIT

Difference (D) = a  b
Barrow (B) = ab’
HALF-SUBTRACTOR is designed using 4 majority gates and NOT gates. Majority gates
are OR, NAND and 2 AND. Here inputs a andb are given to NAND gate and OR gate
and then output of this two given to AND gate which gives the difference and borrow is
calculated by giving input a and invert of input b to AND gate. Outputs are seen in cells
which are at clock 2 shown in Fig. 4.11.2, Fig. 4.11.3 is the simulation result which
satisfy the truth table shown in Fig. 4.11.1 with 3 phase delay.
Fig. 4.11.1 HALF-SUB Truth Table Fig. 4.11.2 HALF-SUB QCA Design
Fig. 4.11.3 HALF-SUB Simulation Result

4.12 DESIGN OF FULL-SUBTRACTOR QCA CIRCUIT

D=a b c
B = (ab+ bc’+c’a )
FULL-SUBTRACTOR is designed using 7 majority gates and NOT gates. Majority gates
are 2 OR, 2 NAND, AND and one 3 input majority gate. Here full-subtractor is
implemented using half-subtractor, inputs a and b are given to half-subtractor and output
of that is given to other half-subtractor along with input c with 1 clock phase delay by
which difference is obtained and borrow is calculated by giving inputs a b and inverted c
to 3 input majority gate. Outputs are seen in cells which are at clock 2 shown in Fig.
4.12.2, Fig. 4.12.3 is the simulation result which satisfy the truth table shown in Fig.
Fig. 4.12.1 FULL-SUB Truth Table Fig. 4.12.2 FULL-SUB QCA Design
Fig. 4.12.3 FULL-SUB Simulation Result

4.13 DESIGN OF 2:1 MUX

Y = S’a+Sb
2:1 MUX is designed using 3 majority gates and NOT gate. Here input a given to upper
majority gate and input b is given to down majority gate which is shown in Fig. 3.35. If
input S is 0 then upper majority gate one cell gets 1 then whatever the value of a it
becomes majority of that cell and output of that gate is a, in the same time lower majority
gate one cell gets 0 which makes 0 as output of that gate and then the output of this 2
gates are given to middle majority gate which means a will be output of that gate,
similarly if S=1 then b will be the output. Output is in cell which is at clock 3 shown in
Fig. 4.13.2, Fig. 4.13.3 is the simulation result which satisfy the truth table shown in Fig.
Fig. 4.13.1 2:1 MUX Truth Table Fig. 4.13.2 2:1 MUX QCA Design
Fig. 4.13.3 2:1 MUX Simulation Result

4.14 DESIGN OF 4:1 MUX

Y = S1′S0′I0+S1′S0I1+S1S0′I2+S1S0I3
Here 4:1 MUX is implemented using 2:1 mux with S0 and S1 as select lines. Inputs a b
given to upper majority gates of 2:1 MUX and input c and d are given to lower gates.
Fig. 4.14.1 4:1 MUX Truth Table
Fig. 4.14.2 4:1 MUX QCA Design

Fig. 4.14.3 4:1 MUX Simulation Result
4.15 DESIGN OF FEYNMAN

P=a
Q=a b
Feynman gate is designed using 3 majority gates and NOT gates. One majority
gate is OR gate and other two are AND gates. Here input a given to one AND gate
and its inverted signal given to another AND gate similarly input b, and then the
output of this 2 AND gates are given to OR gate. One output is in cell which is at
clock 2 and other at clock 0 as shown in Fig. 4.15.2, Fig. 4.15.3 is the simulation
Fig. 4.15.1 Feynman gate Truth Table Fig. 4.15.2 Feynman gate QCA Design
Fig. 4.15.3 Feynman gate Simulation Result
4.16 DESIGN OF TOFFOLI

Z = ab c
Y=b
X=a
Toffoli gate is designed using 4 majority gates and NOT gates. Here input a and b
given to AND gate and its output given to EX-OR gate along with input c. Outputs
are seen in cell which are at clock 4 shown in Fig. 4.16.2, Fig. 4.16.3 is the simulation
Fig. 4.16.1 Toffoli gate Truth Table Fig. 4.16.2 Toffoli gate QCA Design
Fig. 4.16.3 Toffoli gate Simulation Result
4.17 DESIGN OF CNOT

X=a
Y=a b
CNOT gate is designed using 3 majority gates and NOT gates. Majority gates are
OR, AND and NAND. Here inputs a and b are given to NAND gate and OR gate and
then output of this two given to AND gate. One output is in cell which is at clock 2
and other at clock 0 as shown in Fig. 4.17.2, Fig. 4.17.3 is the simulation result which
satisfy the truth table shown in Fig. 4.17.1 with 3 phase delay.

Fig. 4.17.1 CNOT gate Truth Table Fig. 4.17.2 CNOT gate QCA Design
Fig. 4.17.3 CNOT gate Simulation Result
4.18 DESIGN OF MULTIPLIER BLOCK

Two-bit multiplier is designed using 3 majority gates. Majority gate is used draw AND,
OR, NAND. One of the two bits are given parallelly, while the other is given serially.
Because multiplication is done, one bit at a time. The first two majority gate computes the
AND of two parallel input with the one bit of serial input. The output obtained from AND
gate is added using XOR gate. The first bit is added without any delay while the second
bit is added after one clock delay. Because while multiplying the first is multiplied
without any shift, but the second bit is written with a single shift.
Fig. 4.18.1 Multiplier QCA Design.
Fig. 4.18.2 Multiplier Simulation Result.

4.19 DESIGN OF 2-BIT FULL-ADDER BLOCK

The 2-bit full adder is shown in Fig.4.19.2. It consists of two identical 1-bit full adder
layout. Only the carry flows from first adder to next adder. It has 4 phase clock delay.
The simulation result is shown in Fig. 4.19.3 which matches with the truth table Fig.
4.19.1.
Fig. 4.19.1 2-Bit Full-adder Truth Table Fig. 4.19.2 2-Bit Full-adder QCA Design

Fig. 4.19.3 2-Bit Full adder Simulation Result
CHAPTER 5
IMPLEMENTATION
QCA DESIGNER TOOL AND IMPLEMENTATION STEPS

QCA Designer is the “state of the art” QCA layout editor and simulator. All the
designs are verified using QCA Designer tool ver. 2.0.3. The main layout design window
of QCA Designer is presented in Fig. 5.1[3].
The physical layout editing facilities include:
 Drawing QCA cells individually or in arrays, optionally aligned to a grid with a

default spacing (20 nm) equal to the default cell size (18 nm) plus the default inter
cell spacing (2 nm).
 Setting clock signal for each QCA cell, which is required to synchronous circuits
to working properly.
 Multi-layer QCA layout design, which is required to have multi-layer signal
crossing.

Fig. 5.1 QCA Designer Window.
 Drawing QCA cells with 90 degrees rotation, which is required to have in plane
signal crossing.
 Graphical marking of special cells (on via and crossover layers), according to the
design parameter. Although cell in via and crossover structures may look different
in the layout, they are regular QCA cells and no distinction is made during
simulation. Cells acting as vertical via interconnections between layers are
represented by a square with a circle inside, and cells in crossover layers are
represented by a square with a cross inside, the normal cells are represented as a
square with four little circles inside and the arrangement of those circles depend on
the rotation of the cell.
 Grouping the input/output signals in buses, to simplify signal name handling,
simulation input vectors definition, and simulation results inspection.
 Importing and exporting layout blocks to files.
5.1CREATE QCA LAYOUTS USING QCADESIGNER

 Figure 5.1.1 shows cascade of QCAcells which represents a QCAwire. In a
coplanar design only one layer allowed and the default layer is “main cell layer”
(see the box above design area).
 The single cell can becreated by clicking “Cell” followed by left click on the
design window.Note a left click in the design area only append one cell. So we can
get desired number of cells by left clicking as many times as we need.
 An array of cells can be obtained byclicking “Array” and dragging the mouse in
the design area to a require length. Todelete one or more cells click “Select”
followed by selecting unwanted cell/cellsand pressing delete button.
Fig: 5.1.1 QCA WIRE

 Figure 5.1.2 shows layout of a 3-input majority gate asdescribedbyM (A,B,C) =
MV3= AB +BC + AC.Theinput/outputmodeofa cell can be identified by double
clicking corresponding cell which pop up “CellFunction” window.
5.1.2 Majority gate

 All the cells in a QCA circuit are clocked appropriately using “Clock Box” above
design area and choosing correct clock zone from the drop list. The layout design
for an inverter is obtained in similar a manner. QCA structure of an inverter is
illustrated in Fig. 5.1.3
5.1.3 Inverter

5.2 WAY TO SIMULATE

 QCA Designer 2.0.3 enables user to specify type of simulation engines Coherence
vector and bistable approximation. In addition to this, it allow user to specify the
way in which the input is to be provided.
 To select simulation engine , click Simulation and select Simulation Engine Setup,
as shown in Fig.5.2.1
Fig.5.2.1 Simulation engine setup
 The default engine appears for simulation is “bistable approximation” (see Fig:
5.2.2 in bistable approximation engine, designer can change number of samples,
maximum iteration per sample, etc.

Fig.5.2.2bistable approximation
5.3 CLOCKING TO A BLOCK

 As indicated earlier, all circuits in QCA are clocked. Appropriate clock zones need
to be assigned to different parts of the circuit for correct functionality.
 Double click on one particular cell, bottom of right side there is an option called
clock (clock 0,clock 1,clock 2,clock 3) and select clock zone and apply , is
depicted in Fig. 5.3.1.
5.3.1 Clock zone

 A simple universal NAND circuit that illustrates that takes two (data) inputs A, B,
control input (-1) and an output The QCA layout for a NAND is depicted in
Fig.5.3.2.
 The inputs are in the same clock zone (clock zone 0). Thereafter, there is a change
of clock zone for the final output (clock zone 3).
 We also note that the third input for an AND gate is logic-0 (indicated by a
polarization of -1).

5.3.2 NAND gate with clocking
5.4 CROSSOVER
 The default wire consists of cells of 90° orientations while for 45° orientation cells
select the required cell/cells followed by clicking “Rotate” button, Fig 5.4
 Single layer crossing is implemented in one layer using both 45-degree and 90-
degree QCA cells, each one dedicated to one side of a crossing.
 These cells can pass over the crossing without any significant effect on each other.
 Signals A and B pass through with coplanar crossover if the horizontal cells are
assigned clock 0 (clock 1) and the vertical cells are assigned clock 2 (clock 3) or
vice versa.

Fig.5.4 Single layer Crossover
5.5 Storing QCA Layout

 To save the layouts select File->Print-> Printer.
 The window of will be opened.
 In addition, print option enables setting like margins, scale, and printed objects.
 For coplanar layouts, deselect substrate and drawing layer in Printed Objects.
 Whereas, multilayer layouts keep all the three layers active.
 In the file name field of Fig.5.5, enter the desired circuit layout name.
 In this case, the file name used was AND_sample.eps or XOR_sample.qca .
 Note: .qca file for QCA layout and .eps file for print the layout as an image file.

Fig.5.5 Storing QCA Layout
5.6 Sample layout

Fig. 5.6.1 Sample layout

CHAPTER 6
RESULTS AND DISCUSSION
BASIC GATES:
Design No. of cells Area(um )2
Delay
AND 5 0.0059 0
OR 5 0.0059 0
NAND 7 0.0079 0
NOR 7 0.0079 0
NOT 3 0.0035 0
TAFFOLI 51 0.0829 4-phase delay = 1
FEYNMA 53 0.0658 3-phase delay = 0.75
N
CNOT 37 0.0358 3-phase delay = 0.75
COMPARISION:
Design Area Cell- Clock Compared Area Cell- Clock

(um )
2
count delay With (m )
2
count delay
(no. of [Ref] (no. of
cells) cells)
EXOR 0.0566 26 3-phase Ref [4] 0.3005 29 3-phase
delay delay
= 0.75 = 0.75
EXNOR 0.0566 26 3-phase Ref [4] 0.426 33 3-phase
delay delay
= 0.75 = 0.75
FULL- 0.0985 86 3-phase Ref [5] 0.58 264 12-phase
ADDER delay delay
= 0.75 =3
HALF- 0.0358 36 3-phase Ref [5] 0.14 72 5-phase
ADDER delay delay

= 0.75 = 1.25
HALF- 0.0511 47 3-phase Ref [6] 0.2 114 3-phase
SUBTRAC delay delay
TOR = 0.75 = 0.75
FULL- 0.0119 93 7-phase Ref [7] 1.32 12800 8-phase
SUBTRAC delay delay
TOR =1.75 = 1.50
2:1 MUX 0.0573 39 4-phase Ref [8] 0.0598 45 2-phase
2 delay delay
=1 = 0.5
MULTIPLI 0.18 91 4-phase Ref [9] 0.22 164 4-phase
ER delay=1 delay=1
2-BIT 0.21 172 4-phase Ref [6] 2.77 756 24-phase
FULL- delay=1 delay=6
ADDER
CHAPTER 7
CONCLUSION
Quantum-dot Cellular Automata (QCA) is being currently investigated as an

alternative to CMOS-VLSI technology. The work presented in this project has
summarized; theory of QCA, its unique features, useful designs and implementations
using QCA based logic circuits. The analysis of the proposed QCA based circuits in
terms of various circuit parameters has been presented in the project.
The work presented in the project is focused on the design of ALU using
Quantum-dot Cellular Automata. ALU is a unit which performs various mathematical
and logical operations with the help of electronic logic circuits; these logical circuits are
designed using QCA. Several initial designs and implementations are available, that have
been studied for an in-depth understanding of the subject. It has been observed that there
is a high scope for designing and implementing new QCA-based logic circuits and
applications which provides improved circuit parameters like area, clock delays and
circuit complexity which includes no of cells. This is the motivation to conduct the work
carried out under this project. QCA-based AND, OR, XOR, HALF ADDER, FULL
ADDER, HALF SUBTRACTOR, FULL SUBTRACTOR, MULTIPLIER,
MULTIPLEXERS and BASIC QUANTUM GATES like FEYNMAN, CNOT circuits
have been presented in this project. The circuit solutions presented in the project has
significant reduction in terms of several circuit parameters including area, clock delays
and circuit complexity which includes no of cells. All these QCA-based circuit
implementations and their analysis have been carried out using QCA Designer tool. The
results of various computational designs have been presented in the project and its
various simulation results, waveform and figures are showed.
Future Scope
The work presented in the project has been concerned with designing few new QCA-
based logic circuits and ALU design. However, the area is wide open for further
research to implement new circuits and systems with improved parameters. The area
reduction and number of cell counts analysis of QCA-based adder, subtractor and
multiplier circuits has been carried out. Several reversible logic gates proposed in this
project has an application for designing and implementing less power reversible
benchmark combinational and sequential digital functions in QCA domain where
reversibility is required. Here we have designed simple ALU circuit, this design can be
extended to design quantum computer. There are many researches going on based on the
quantum computer. QCA is one of the promising fields to replace CMOS circuits.
REFERENCES
[1] G. E. Moore, “Cramming more Components onto Integrated Circuits,”

Electronics,” Vol. 38, No. 8, April 19, 1965.
[2] M.B. Tahoori, M. Momenzadeh, H. Jingand, F. Lombardi, “Defects and Faults in
Quantum Cellular Automata at Nanoscale,” Proceedings of the 22nd IEEE
Symposium on VLSI Test, pp. 291–296, 2004.
[3] KonradWalus, Timothy J. Dysart, Graham A. Jullien, Arief R. Budiman, “A Rapid
Design and Simulation Tool for QCA”
[4] Kavitha S S, NarasimhaKaulgud, “Quantum-dot cellular automata design for the realization of basic
gates,” ICEECCOT, 2017.
[5] Suman Rani, TrilokayaNathSasamal “Design of QCA Circuits Using New 1D Clocking Scheme,” TEL-
NET, 2017.
[6] RubinaAkter, NasrinJahan, Md. Mamunur Rashid Shanta, AnikBarua “A Novel Design of Half
Subtractor using Reversible Feynman Gate in Quantum Dot cellular Automata,” American Journal of
Engineering Research (AJER), 2014.
[7] S. Karthigailakshmi, G. Athishi, M. Karthikeyan, C. Ganesh4 “Design of Subtractor using
Nanotechnology Based QCA,” ICCCCT, 2010.
[8] Angshuman Khan, SiktaMandal, “Elimination of Static Hazard in 2:1 Multiplexer using Quantum dot
Cellular Automata,” IEEE 2016.
[9] Heumpil Cho, “Adder and Multiplier Design in Quantum-Dot Cellular Automata,” IEEE
TRANSACTIONS ON COMPUTERS, 2009.
[10] J. Timler, C. S. Lent, Power gain and Dissipation in QCA, J. Appl.phys., 2002.
[11] W.Porod, “Quantum-dot Devices and QCA”, Journal of Franklin Institute, 1997.
[12] S. H. Shin, J. C. Jeon, K. Y. Yoo, “Wire-Crossing Techniques on QCA” the 2nd International
Conference on Next Generation Computer and Information Technology, 2013.
[13] A. Gin, P.D. Tougaw and S. Williams, “An Alternative Geometry for QCA”, J. Apllied Physics, 1999.
[14] R. Zhang, K. Walnut, W. Wang and G. Jullien, “A Methods of Majority Logic Reduction for QCA”,
IEEE Transaction on Nano-Technology, 2004.

67
Time Utilization Gantt Chart
68

67
Plagiarism Report
Page 2 69
Dept. of ECE, BMSCE
POSTER
A one-page poster consolidating the project report is presented below.
Dept. of ECE, BMSCE

67 Page 3 70
PUBLICATION
This paper has been submitted to IJATEE.
First two pages of the manuscript is presented below:
Dept. of ECE, BMSCE 67 Page 4 71

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PO1: An ability to independently carry out research /investigation and development work
to solve practical problems.
PO2: Ability to write and present a substantial technical report/document.
PO3: Students should be able to demonstrate a degree of mastery over the area as per the
specializationoftheprogram.Themasteryshouldbeatalevelhigherthantherequirements in the
appropriate bachelorprogram
Demo
Demo Link:
https://drive.google.com/file/d/1lOrPnSAGg9d1akTsPHFgvXtkCFVWwvsK/view?usp=s
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B.M.S.

Autonomous institute, affiliated to VTU

Under the guidanceof

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

B.M.S. COLLEGE OF ENGINEERING

Name of the project examiners:

I, Mamatha B R (1BM19LEL10), hereby declare that the project work entitled

The increasing amount of data traffic in communication networks underscores

3.1 Electron spin 15

3.2 QCA solution 19

3.3 QCA basic cell

3.4 QCA polarization

3.5 QCA clocking

3.6 Cell to Cell response

3.7 QCA wires

4.2 Design of AND gate 21

4.3 Designof OR gate 24

4.4 Designof NAND gate 26

4.5 Design of NOR gate 28

4.6 Design of NOT gate 30

4.7 Design of EX-OR gate 24

4.9 Design of HALF-ADDER circuit

4.10Design of FULL-ADDER QCA circuit

4.11 Design of HALF-SUBTRACTOR QCA circuit

4.12 Design of FULL-SUBTRACTOR QCA circuit

4.13Design of 2:1 mux

4.14Design of 4:1 mux

4.18Design of MULTIPLIER block

4.19Design of 2-bit FULL-ADDER block

5.2 Way to simulate 38

5.3 Clocking to a block

5.5 Storing QCA layout

5.6 Sample layout 44

Figure 3.1.1: Electron spin 2

Figure 5.2.2Bistable approximation

PLL Phase Locked Loop

Dept. of ECE, BMSCE 13

new method of digital computation and appears to be implementing a possible alternative

Quantum chemistry is the branch or application of quantum mechanical principles

1.2 PROBLEM STATEMENT

Rapid change in the field of technology and communication, multimedia, data

Dept. of ECE, BMSCE 15

1.4 PROGRAM OUTCOMES ADDRESSED

and the strengths/drawbacks of each of them.

Dept. of ECE, BMSCE 17

[4] Kavitha S S, NarasimhaKaulgud, “Quantum-dot cellular automata design for the

[5] Suman Rani, TrilokayaNathSasamal “Design of QCA Circuits Using New 1D

Dept. of ECE, BMSCE 18

[6] RubinaAkter, NasrinJahan, Md. Mamunur Rashid Shanta, AnikBarua “A Novel

[8] Angshuman Khan, SiktaMandal, “Elimination of Static Hazard in 2:1 Multiplexer

using Quantum dot Cellular Automata,” IEEE 2016.

Power gain and dissipation in quantum-dot cellular automata, author as proposed

Dept. of ECE, BMSCE 21

Dept. of ECE, BMSCE 22

3.1 ELECTRON SPIN

The Spins plays a important role in quantum mechanics in computing the

Dept. of ECE, BMSCE 23

Fig. 3.1.1 Electron Spin

The electron can spin two directions:

3.2. QCA SOLUTION

Dept. of ECE, BMSCE 24

QCA encodes binary information in the form of charge configuration within

The movement of mobile electrons in a QCA cell to different Quantum-dots will be