MIC511

Analysis and Design of Analog Integrated Circuits

Lecture 11

Examples

Michael H. Perrott
Masdar Institute of Science and Technology
March 4, 2012

Copyright 
c 2012 by Michael H. Perrott
All rights reserved
 Example Analysis Circuit

M15 M17
M3 M4 M7 M22

M9 M16

M18
Ibias1 M8
Q1

50 Ω M1 M2 M23 50 Ω

Vin M14
M19
50 Ω M10 Vout
M13
Cbig M21
(external)
M24
M5 M6 M11 M12 M20

• Assumptions
1. Intrinsic gain of each device  1

gmro  1 =⇒ 1/gm  ro

2. Intrinsic gain of devices similar in value

3. Output resistances of devices similar in value

ro1 ≈ ro2

• Note:
– Assumption 1 is reasonable in practice
– Assumptions 2 and 3 are invalid in practice
∗ Used here only for pedagogical reasons
 Replace Current Sources

current
current mirror current current
source bias source source

M15 M17
M3 M4 M7 M22

M9 M16 M18

Ibias1 M8
Q1

50 Ω M1 M2 M23 50 Ω

Vin M14
Cbig M19
50 Ω M10 Vout
(external) M13
M21

M24
M5 M6 M11 M12 M20
cascode
current current current current current bias current
mirror source source source source source
bias
current
mirror
bias

M15
M3 M4 ro7 ro22

M9 M16 (gm18ro18)ro17

Ibias1 M8
Q1

50 Ω M1 M2 M23 50 Ω

Vin

50 Ω Cbig Vout
(external) (gm10ro10)ro11 (gm19ro19)ro20
M21
ro6 ro24
M5 (gm13ro13)ro12
cascode
current bias
mirror
bias
 Remove Non-Signal-Path Biasing Circuitry

current
mirror
bias

1 M4 ro7 1 ro22
gm3 gm15
M9 (gm18ro18)ro17

M8
Q1

50 Ω M1 M2 M23 50 Ω

Vin

50 Ω Vout
(gm10ro10)ro11 (gm19ro19)ro20
1 ro6 1 ro24
gm5 gm21
(gm13ro13)ro12
current assume
mirror cascode
cap is short bias
bias

Stage 1 Stage 2 Stage 3

1 M4 ro7 ro22
gm3
M9

M8
Q1

M1 M2 M23

50 Ω
Vin 50 Ω Vout
(gm10ro10)ro11
vinput ro6 ro24 50 Ω
(gm13ro13)ro12

assume
cap is short
 Bipolar Modeling is similar to CMOS

MOSFET BIPOLAR

Key Small-Signal Parameters Key Small-Signal Parameters

Ic kT
gm = μnCox(W/L)(VGS - VTH) gm =
Vt
,Vt =
q
= 2μnCox(W/L)ID Vt ~
~ 25 mV at room temp
βo
gmb << gm rπ = , βo ~
~ 100 to 200
gm
1 V
ro = ro = A , VA ~ ~ 100 to 200 V
λID Ic

Thevenin Resistances Thevenin Resistances

ID RD RC
IC
Rthd Rthc
RG RB

Rthg Rthb
Rths Rthe
RS RE

Approximation Assumption Approximation Assumption

Rthd= ro (1+gmRS) gmb << gm Rthc= ro (1+gm(rπ||RE)) RB << rπ

Rthg= infinite Rthb= rπ + βoRE RC+RE << ro
1 + RD /ro
Rths= gmb << gm Rthe= 1/gm + RB/βo RC << βoro
gm

General Thevenin Model General Thevenin Model

g d b c
is ie
Rths Rthe
Rthg vg Avvg α is Rthd Rthb vb Avvb α ie Rthc

s e

Approximation Assumption Approximation Assumption

Av = 1 gmb << gm , gmro >> 1 Av = 1 RC+RE << ro, RB << rπ

α= 1 Rd << Rthd α= 1 RC+RE << βoro
 Compute 2-port for Stage 3

M23

ro22

vg vg 1 Q25 50||ro24 50
Vb gm23

1
gm25
vb25 rπ + βo50 vb25 50 vout

rπ + βo(50||ro24) ( g 1 ||ro22)
1 m23 1
rπ + βo50
Stage 3 gm25 βo gm25

ro22
1
(rπ + βo50)||ro22 gm25
vg vg 50 vout
1 (rπ + βo50)||ro22
output Vb gm23
resistance Q25
of Stage 2 Vb
M23

Vb
(gm10ro10)ro11
Vout 1
(rπ + βo50)||ro22 gm25
vg vg 50 vout
ro24 1 (rπ + βo50)||ro22
50 Ω gm23
 Compute 2-port for Stage 2

ro7
Va (ro7||ro4||ro2)(gm8ro8)(gm9(ro9||RA))
ia ro7/3(gm8ro8)(gm9ro9)

1
gm8
αis ro7/3(gm8ro8)(gm9ro9)

is

1 + RD /ro8 is Vb
gm8(gm9(ro9||RA))
Stage 2 1 + (gm10ro10)ro11 /ro8
gm8(gm9ro9) (gm10ro10)ro11
RD
(gm10ro10)ro11 /ro8
ro7 gm8(gm9ro9)
output
resistance ro11 /ro8 1
of Stage 1 Va M9 gm8 gm8

ro7
M8 input is = ia ia
ro2||ro4 resistance 1 +r
o7
of Stage 3 gm8
Vb
Va Vb
is

1 is (gm10ro10)ro11
(gm10ro10)ro11 gm8

RD RA
(gm13ro13)ro12 1 1
||r
gm8 o7 gm8
 Compute 2-port for Stage 1 (Step 1)

Stage 1

1 M4
gm3 input
resistance
Va of Stage 2

1
gm8
M1 M2

50 Ω
Vin 50 Ω

vinput ro6 Calculate Thevenin resistances

1 M4
gm3 input
resistance
ro4 of Stage 2
ro1(1+gm1 1 )
gm2 ro2(1+gm2 1 )
2ro1 gm1
2ro2 1
25 Ω gm8
M1 M2
vinput Vin
2
infinite
1 1 1 1
gm2 ||ro6 gm2 gm1 ||ro6 gm1
ro6
 Compute 2-port for Stage 1 (Step 2)

Calculate short circuit current at output

1 M4
gm3
M1 ro4
25 Ω is1 i2 = gm4 1 is1 is1
gm3
is1
vinput Vin 1
gm1
2 vg1 vg1 αis1 2ro1
is1 isc

M2
Vin
is1 =
1 1
gm1 gm2 is1
gm1 1
Vin gm2
2 ro6
isc 2is1 Vin gm1

Calculate output resistance

gm4vg4
1 vg4 ro4
gm3 vt M4
i1 ro4
it
ro1(1+gm1 1 )
gm2 vt
2ro1 i 1= 2ro2 vt
i1 2ro2
25 Ω
M1 M2
Vin
i1 i1

1
gm1
ro6 vt vt vt
it +2i1 = r +2
ro4 o4 2ro2
vt
= ro2||ro4
it
 Compute 2-port for Stage 1 (Final Step)

Stage 1

1 M4
gm3 input
resistance
Va of Stage 2

1
gm8
M1 M2

50 Ω
Vin 50 Ω

vinput ro6
25 Ω Va
Vin
vinput
vg1 gm1vg1 ro2||ro4
2
 Overall Cascade of 2-ports for Amplifier

Stage 1
25 Ω Va
Vin
vinput
vg1 gm1vg1 ro2||ro4
2

Stage 2
Vb
ib

1 ib (gm10ro10)ro11
gm8

Stage 3

1
(rπ + βo50)||ro22 gm25
vg vg 50 vout
1 (rπ + βo50)||ro22
gm23

• What is the overall input/output resistance of the amp?

• What is the overall gain?
• Which stage contributes the most gain?
• What is the function of each stage?