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Low Power & Area Efficient Digital Circuits Design for Portable Devices using
GDI

Article · January 2020

DOI: 10.37896/jxu14.6/212

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Journal of Xidian University https://doi.org/10.37896/jxu14.6/212 ISSN No:1001-2400

Low Power & Area Efficient Digital Circuits Design for

Portable Devices using GDI
Nandyala Naveena1, Nimmagadda Poojitha2, Pallewar Rageshwari3, Somashekhar Malipatil4
Department of Electronics & Communication Engineering1&2&3&4
AVN Institute of Engineering & Technology, Hyderabad1&2&3&4

Abstract: GDI (Gate Diffusion Input) is a new technique of low power digital circuit design is
proposed. This technique allows minimization of power consumption and area. The power
consumption for CMOS schematic designs are as follows Full Adder (42.285µW), 2:1 Multiplexer
(2.705µW), D-FlipFlop (6.422µW). In this paper we have achieved low power using GDI for Full
Adder, 2:1Multiplexer and D-FlipFlop logic gates 11.75µW, 0.01nW, 3.325µW respectively for
supply voltage 1.2V. The Area reduced for GDI 2:1 Multiplexer (83.33%), Full Adder(78.26%)
and D Flip Flop (33.33%) compared to CMOS technology.

Keywords: Low Power, Area, GDI, CMOS, 120nm, Full Adder, Multiplexer, Flip-Flop,
Microwind 2, DSCH 2.
I. Introduction

With Increasing demand for reliable battery life of digital devices is also demanding for low power
consumption digital devices. It has become the major focussed work for designers to design such digital
devices in order to meet the requirements of the latest advancements of the technology as these devices
mostly include phones, laptops, sensor nodes.
Significant parameters for designing any integrated circuit are area and power dissipation. Whenever
technology scales from µm to nm, the Vth of transistors is also minimized this leads to sub threshold
leakage current to increase exponentially.

II. Proposed Methodology-GDI

GDI - a new low power design technique, which allows solving most of the problems mentioned in
existing method. The intention of this work is to analyze the GDI technique by implementation of digital
circuits Full Adder, Multiplexer, D-FlipFlop and comparing their properties with their analogues in
CMOS. In order to verify the practical applicability of GDI and display its properties, the digital circuits
will design in 120nm technology, based on GDI and CMOS cell libraries. The schematic and layout of
digital circuits are implemented in DSCH and Microwind 2 software. The dynamic power is expressed
as shown in equation 1.

Pd= αcv2f …………………….1

Where α=switching activities
C=capacitance
V=supply voltage
f=frequency

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Journal of Xidian University https://doi.org/10.37896/jxu14.6/212 ISSN No:1001-2400

In this design, dynamic power is minimized by reducing switching activity and supply voltage 1.2V.

Fig1: Block diagram of Modified Full Adder

Fig 2: Full Adder schematic using GDI

Fig 3: 2:1Multiplexer using GDI

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Journal of Xidian University https://doi.org/10.37896/jxu14.6/212 ISSN No:1001-2400

Fig 4: D-Flipflop using GDI

Fig 5: Full Adder Layout using GDI

Fig 6: 2:1 Multiplexer Layout using GDI

Fig 7: D FlipFlop Layout using GDI

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Journal of Xidian University https://doi.org/10.37896/jxu14.6/212 ISSN No:1001-2400

Fig 8: Full Adder 3D using GDI

Fig 9: 2:1 Multiplexer 3D using GDI

Fig 10: D FlipFlop 3D using GDI

III. Simulation Results, Power & Area Analysis

Fig 11: Simulation of Full Adder

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Journal of Xidian University https://doi.org/10.37896/jxu14.6/212 ISSN No:1001-2400

Fig 12: Simulation of 2:1 Multiplexer

Fig 13: Simulation of D Flip Flop

Table 1: Power Analysis

Digital Circuit Technology Power Consumption Supply Voltage
CMOS 42.285µW
Full Adder
GDI 11.75 µW
CMOS 6.422µW
D Flipflop 1.2V
GDI 3.325 µW
CMOS 2.70 µW
Mux
GDI 0.01nW

Power Analysis (µW)

50

40

30 CMOS
Technology
20 Proposed
10 Work(GDI)

0
FullAdder D Flipflop MUX

Graph1: Power Analysis

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Journal of Xidian University https://doi.org/10.37896/jxu14.6/212 ISSN No:1001-2400

Table 2: Area Analysis

Transistor Count
S.No. Digital Circuits
Proposed work( GDI) Existed work(CMOS)
1 2:1 Multiplexer 2 12
2 Full Adder 10 46
3 D Flip Flop 12 18

IV. Conclusion

The power consumption for CMOS schematic designs are as follows Full Adder (42.285µW), 2:1
Multiplexer (2.705µW), D-FlipFlop (6.422µW). In this paper we have achieved low power using
GDI for Full Adder, 2:1Multiplexer and D-FlipFlop logic gates 11.75µW, 0.01nW, 3.325µW
respectively for supply voltage 1.2V. The Area reduced for GDI 2:1 Multiplexer (83.33%), Full
Adder( 78.26%) and D Flip Flop (33.33%) compared to CMOS technology.

References

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