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HFIC Chapter 7 Low-Noise Amplifier Design
HFIC Chapter 7 Low-Noise Amplifier Design
1
Outline
2
7.1 LNA overview
3
Tuned LNA topologies
CB/CG (no feedback)
4
Design goal
G× IIP3× f
FoMLNA =
F−1 PDC
5
Design philosophy
Take advantage of what silicon does best: transistors.
Use Si passives only sparingly:
Q is fairly low and undermines overall noise figure
Inductors are (significantly) larger than transistors,
hence expensive.
Make transistor sizing part of the noise matching step.
Use only reactive (loss-less) feedback or minimize the
noise contribution of resistive feedback components.
Avoid active loads if at all possible.
6
LNA design fundamentals
Device noise fundamentals:
Re{Zsopt} <> Re{ZIN} and Im{Zsopt} approx. Im {ZIN} (within 15%)
Re{Zsopt} = k fT/(fgm)
Saving power comes with the price of compromising noise and linearity!
7
Tuned and broadband LNA design
philosophy
Active device for noise impedance
∂ F MIN W f
Find optimal W f for given frequency =0
∂W f
Bias for minimum NFMIN and
∂ F 50 N f
=0
sizing (Nf) for Re{Zsopt} = 50 ∂N f
8
Biasing LNA topology for minimum
noise
MOSFET, cascode JOPT = 0.15
mA/µm irrespective of Wf, node,
and frequency
9
Sizing the MOSFET/HBT (cascode) for RSOPT
NFMIN
Noise parameters scale with
Z0 (lE)Nf for fixed Wf.
∂ F5 0 N f
ℜ[Z sop t Nf , f ]=Z 0 coincides with =0
∂N f
∂ F5 0 lE
ℜ[Z sop t l E , f ]=Z 0 coincides with =0
∂l E
10
Sizing the FET (cascode) for RSOPT
R N , FET Gu =G N , FET 2 N f N
Rn =
Nf N
B cor =B FET N f N
Gcor =G C , FET N f N
2
Y sopt = G cor
Gu
Rn
− jBcor =N N f W f 2
GC , FET
GFET
R FET
− j B FET
Zsopt FET≈
f Teff
N⋅Nf⋅W f⋅f⋅g 'meff [ g 'm⋅R 's W f⋅g 'm⋅R 'g W f
k1 ]
j = Z0 j Xsopt
N N f=
f Teff
Z 0⋅W f ⋅f⋅g ' meff g ' m⋅R ' sW f ⋅g ' m⋅R ' g W f
k1
11
Sizing the HBT (cascode) for RSOPT
R HBT Gu =G HBT 2 N l E
Rn =
N lE
2
Y sopt = G cor
Gu
Rn
− jB cor =N l E
2
G C , HBT
G HBT
RHBT
− j B HBT
[ ]
'
f Teff gm ' '
Zsopt HBT≈ r ER b j = Z0 j X sopt
f⋅N⋅lE⋅g meff
'
2
N lE=
f Teff
Z0⋅f⋅g'meff g'm '
2
r ER'b
12
RF CMOS/HBT LNA design equations
∂F5 0 N f l E
ℜ[Z sopt N f l E, f ]=Z 0 coincides with =0
∂N f l E
V
Z 0 −Rs −Rg Z 0 −Rb −r E DD
L S= L S= R L
T cascode T cascode P C
[ fT
]
V
OUT
Z IN =T L SRg Rs j L SL G −
f gm V
DD
[
Z IN = T L SRb r Ej L SL G −
fT
f gm ] Z
SOPT
V
=Z
IN
o
L
G
Z =Z L
S
fT 2
in o
LG= −L S 1 T RP
f
2
2 f gm G≤
4 f 2 Z0
13
Refinements for mm-waves: S. Nicolson (CSICS-06)
(i) Source Impedance
With bondwire RS=n×Z 0 ; M1
k =12 C2PAD Z 20
14
Refinements for mm-wave CMOS LNAs:
(ii) fT of topology with LM after extraction
LM1
M1
Cdb1 +Cgd1
gm1
f T cascode=
2 Cgs1 2 Cgd1
LM1 forms artificial t-line with parasitics of M1 and M2
An optimal LM1 exists that maximized fT.
LM1 ~ W 1-1
Both the gain and the noise figure are improved
15
(mm-wave) CMOS/HBT LNA design
methodology
Calculate effective source imp. ZS = R + jXS
VDD
JOPT VBIAS M
C2 CPAD
CD
16
Examples: SiGe HBT vs. 90-nm CMOS Cascode LNAs
VCC=3.3 V
RFOUT-DIFF
LC= 120 pH RC2 =1 k
LPRI/SEC= 160 pH
C C= 23 fF
3.58*2 3.58*2
/0.2um /0.2um
LB = 90 pH
4.52*2 3.58*2
RFIN /0.2um /0.2um
LE= 60 pH LE2 = 60 pH
480 μm
370 μm
17
Single-Transistor Stack Topologies
∆ VT
∆VDS
18
140-GHz 65-nm CMOS LNA
6-stage AC-coupled
cascode amplifier
– 63 mW at 1.2V
– 20% stage scaling
– 300m x 500m inc.
pads
[S. Nicolson RFIC-08]
Measured S-params and linearity
LNA bias network
Reference current may
come from bandgap circuit
Transistors must be in
close proximity in layout.
large IIP3
21
Bias circuits (ii)
VD D
VD D
LD 1 LD 1 LD 1
VO U T - VO U T +
VO U T
VD D
Q3,4 VD D
Q3
LG 1 BIAS L G 1 V_
V+IN IN
LG 1
VIN
Q1,2 Q1
LS 1
LS 1
BIAS
LSS2
22
Bias circuits (iii)
23
Differential noise matching
ZINdIff = 2ωΤLE
24
Tuned LNA design notes
25
Tuned LNA topologies summary
CS/CE (L or xfmr feedback)
low-voltage, low-noise, good linearity,
poor isolation => difficult to separately design input/output network
CB/CG (no feedback)
moderate noise, good isolation (HBT-only)
poor linearity, difficult to simultaneously match noise and source
impedance
Cascode (L or xfmr feedback)
best isolation, low-to-moderate noise, easy to match, good linearity
higher supply voltage (but available due to mixer)
26
Frequency scaling of CMOS LNAs
• Goal: Scale the LNA centre
frequency
f 0' = α f 0
130nm
• Step 1: Biasing for Minimum
Noise
– JOPT unchanged @
0.15mA/µm
• Step 2: Device Sizing 90nm
– W F unchanged
N F' = N F / α
W ' = W /α
27
Frequency scaling of CMOS LNAs (ii)
Step 3: Input Impedance Matching
ℜ Z 0 − R g R s
LS: unchanged L S=
2 f T
1
LG = −L S
LG: L'G = LG / α
2
C IN
L'D = LD / α
C1' = C1 / α
C2' = C2 / α
28
Experimental results
29
Frequency scaling of 90-nm CMOS LNAs
30
Design porting of CMOS LNAs
• Goal: Keep center frequency
unchanged, port LNA to another
technology node
130nm
• Step 1: Biasing for Minimum Noise
32
Benefits of scaling for RF/mm-wave
Gain and NF
improve with
scaling
33
Power-constrained LNA design
VDD
Problem: GHz-range, noise-matched CMOS
LNAs consume significant power
RP LD Solutions
CD
Current re-use with CMOS inverter (doubles
VOUT
VDD but still saves power
VDD Don't noise match, just bias at Jopt
LG
VIN Use external capacitor between gate and
source: degrades both gain and NF
C1
LS
fT
1
fT
C1
L S L S 1
C1
Cgs2 Cg d
Cgs2 Cg d
34
Lossless series-series feedback noise
matching scheme
LG LG + LS CIN
VIN VIN
M1
iin
ZO ZO
CPAD ZS ZIN CPAD ZIN
LS ZS RIN = Rg+Rs + ωTeff LS
Z*SOPT
LG + LS CIN
VIN
iin
ZO
CPAD Z*SOPT f Teff
ZS RSOPT = Rg+Rs + k2
f gmeff
VIN
iin
GO
gmeff f
CPAD+ CIN Y*SOPT GSOPT ≈
YS k2 f Teff
20um
37
Other low-noise amplifier concepts
38
Tuned, narrow-band LNA summary
39
Back-up slides
40
7.2 Tuned LNA design methodology using a
simulator
41
Cascode topology with series inductive feedback
42
Tuned LNA design steps
fT
Jopt
44
Step1b: HBT cascode low-noise bias (read J opt)
Jopt
45
Step-2: cascode sizing for Re(Zsopt)=ZO
46
Step 3a: add LE such that Re(ZIN) = ZO
ZO−Rb−RE
LE=
2 f Tcascode
47
Step 3b: add LB such that Im(ZIN, Zsopt) = 0
1
Z in ≈Z O j L B L E
j C in
1
L B≈ 2
−L E
C in
ZSOPT=ZO
ZIN=ZO
48
Step 3c: add LC for maximum gain
LC should be as large as
possible for gain
CC helps lower impedance
May use 3-terminal
inductor or transformer for
impedance transform to
ZO
Linearity is maximized by
setting:
RCTankx Icopt = VCE(Q2) –
VCESAT
RCTank is the equiv. parallel
ac resistance at the output
node 49
Step 3d: matching the output
Use the Smith chart with the series-shunt or shunt-
series technique
Make sure not to short-ckt. the output to ground (use
shunt inductor to VCC not to GND.
2
1 T RP
f
G≤ 2
4 f Z in
50