MOSFET – Short Channel

Effects, Leakage, Reliability

Dr. Rajan Pandey
Associate Professor, SENSE
 Sub-threshold Current (Off is not totally Off)
• Circuit speed improves with increasing Ion; therefore, it would be desirable to use a small Vt. Can we
set Vt at an arbitrarily small value, say 10 mV?

• The answer is no. Why?

• At Vgs < Vt, an N-channel MOSFET is in the off state. But, a leakage current can still flow between
the drain and the source.

• The MOSFET current observed at Vgs < Vt is called the sub-threshold current, the main contributors
to the MOSFET off-state current, Ioff.
• Ioff is the Id measured at Vgs = 0 and Vds = Vdd.

• It is important to keep Ioff very small in order to minimize the static power that a circuit consumes
when it is in the standby mode.

• For example, if Ioff is, say 100 nA per transistor, a cell-phone chip containing 108 transistors would
consume 10 A even in standby. The battery would be drained in minutes without receiving or
transmitting any calls.

• A desktop/laptop PC processor would dissipate more power because it contains more transistors
and it has expensive problem of cooling the chip and the system. Let us understand this graphically…
 Sub-threshold Current
The leakage current that flows at Vg< Vt is called the sub-threshold current.

When Vgs is below Vt, Ids is a

Intel, T. Ghani et al., IEDM 2003
straight line (semi-log scale), i.e.,
90nm technology. an exponential function of Vgs on a
Semi-log plot Gate length: 45nm normal scale.

Vt Vt
Vt ~ 0.2V.

The current at Vgs = 0 and Vds = Vdd is called Ioff.

 Sub-threshold Current
• Sub-threshold current: Ids  ns (surface inversion carrier concentration)
• ns  eqϕs/kT • At Vgs below Vt, the inversion
electron concentration (ns) is small
When Vgs is below Vt, but none-the-less can allow a small
Ids is an exponential ϕS leakage current to flow between
function of Vgs. Ef the source and the drain.
Ef, Ec
• A larger Vgs would pull the Ec at the
Vgs surface closer to Ef, causing ns and
Ids to rise.
• ϕs varies with Vg through a capacitor network Dimensionless

ΔVg
d s Coxe 1
From the equivalent Coxe   Integrating…..
ΔϕS dVg Coxe  Cdep 
circuit Cdep
In sub-threshold, ϕs = constant +Vg /
 Sub-threshold Leakage Current
( ) / kT 
Vgs /  qVgs /  kT
 
Ids ns e qϕs / kT
 e
q constant
e

ΔVG
Ids  e qVgs /  kT
Coxe
Δϕs
Cdep C dep
1
Coxe

Sub-threshold current changes 10x with η·60mV change in Vg.

Where 60mV is (ln10)·kT/q

Definition of Sub-threshold swing, S : the change in Vgs corresponding to

10x change in sub-threshold current. S = η·60mV, typically 80-100mV.
 Sub-threshold Leakage Current
• At room temperature,
Practical definition of Vt : the Vgs at which Ids= 100nA × W/L the function exp(qVgs/kT)
W ( - ) / kT W (V - ) changes by 10 for every
Isubthreshold (nA)  100 × × e q Vg V t  100 × ×10 g Vt / S 60 mV change in Vgs.
L L
At Vg = Vt the exponential term reduces to 1 above. Also, we can multiply
• Therefore exp(qVgs/ηkT)
and divide by ln10 in the exponential, and use eln10 = 10, S = η.ln10.kT/q.
changes by 10 for every η
W / W × 60 mV.
At Vg = 0, IOff (nA)  100 × × e- qV t kT  100 × ×10 Vt / S
-

L L
• For example, if η = 1.5, Ids
Log (Ids ) drops by ten times for
Ioff (nA) = 100 × W × 10 Vt / S
-
every 90 mV of decrease
Vds=Vdd L
in Vgs below Vt at room
100×W/L(nA) is determined only by Vt temperature.
1/S and sub-threshold swing.
• η × 60 mV is called the
Ioff sub-threshold swing and
Swing, S, is the inverse of the
Vgs slope in the sub-threshold region. represented by the
Vt
symbol, S.
 Sub-threshold Swing

• Smaller S is desirable (lower Ioff for a given Vt). Minimum possible value of
S is 60mV/decade.
 C 
• How do we reduce swing? S  60mV  1  dep 
 Coxe 
• Thinner Toxe  larger Coxe
• Lower substrate doping  smaller Cdep

• Limitations
• Thinner Tox ― oxide breakdown reliability or oxide leakage current.
• Lower substrate doping ― doping is not a free parameter but set by Vt.
 Effect of Interface States on Sub-threshold Swing
• The sub-threshold swing degrades (increases) when
Vg1 Vg2 > Vg1 interface states are present.
• When ϕS changes, some of the interface traps move from
above the Fermi level to below it or vice versa.
• As a result, these interface traps change from being
empty to being occupied by electrons.
• This change of charge in response to change of voltage
(ϕS) has the effect of a capacitor. The effect of the
interface states is to add a parallel capacitor to Cdep.

• Interface states may be filled by electrons or empty depending on its

energy relative to EF, i.e., depending on Vg.
The sub-threshold swing is
degraded after a MOSFET is
• dQint/ds (number or interface state per eV-cm2) represents another
electrically stressed and new
capacitance in parallel with Cdep
interface states are generated.
 C  dQint / ds 
S  60mV  1  dep 
 Coxe 
 Sub-threshold Leakage Current
An N-channel transistor has Vt = 0.34 V and S = 85 mV, W = 10 μm and
L = 50 nm. (a) Estimate Ioff. (b) Estimate Ids at Vg = 0.17 V (sub-threshold
conduction).

• Ioff (nA) = 100 W/L X 10–Vt ⁄ S = 100 X 10/0.05 X 10 –0.34 ⁄ 0.085 = 2 nA

• Ids = 100 W/L X 10(Vg–Vt) ⁄ S = 100 X 10/0.05 X 10(0.17 – 0.34) ⁄ 0.085 = 200 nA
 Vt Roll-off – short channel MOSFET leaks more
0.00
• We have learned that Vt must not be set too -0.05
Sym bols: TCAD
Lines: Model
low; otherwise, Ioff would be too large.

Vt Roll-off (V)
-0.10

• The channel length (L) must not be too short, -0.15

Vds = 50m V
because Vt drops with decreasing L. -0.20 Vds = 1.0V

-0.25
• Vt roll-off: Vt decreases with decreasing Lg. 0.01 0.1 1
Lg (um )
• It determines the minimum acceptable Lg because Ioff
is too large if Vt becomes too small.

• Why the data is plotted against Lg, not L?

• Because L is difficult to measure. Lg is not.
• Also, Lg is the quantity that manufacturing engineers can control directly.
 Gate Length (Lg) vs. Electrical Channel Length (L)

• Gate length is the physical length of the gate and can be accurately measured with a scanning
electron microscope (SEM). It is carefully controlled in the fabrication plant.

• The channel length, in comparison, cannot be determined very accurately due to the lateral
diffusion of the source and drain junctions. L tracks Lg but the difference between the two just
cannot be quantified precisely in spite of efforts.

• As a result, Lg is widely used in lieu of L in data presentations. L is still a useful concept and is used
in theoretical equations even though L cannot be measured easily for small transistors.

• At a certain Lg, Vt becomes so low that Ioff becomes unacceptable. Doping the bodies of the short-
channel devices more heavily than the long-channel devices would raise their Vt.

• Still, at a certain Lg, Vt is so sensitive to the manufacturing caused variation in L that the worst case
Ioff becomes unacceptable. Let us elaborate it more…
 Why does Vt decrease with L?― Poten al Barrier Concept
Long Channel Short Channel

Vgs = 0V

• When the channel Ec is only ~0.2 eV

Ec
higher than the Ec in the source (which is
Vg=0V Vds
N+ Source also ~EFn), ns in the channel reaches
about 1017 /cm3 and inversion threshold
N+ Drain
condition (Ids = 100nA × W/L) is reached.
Vgs = Vt-long

Vg=Vt ~0.2V • If the channel is short enough, Ec will not

be at the same peak value. As a result, a
smaller Vgs is needed to pull the barrier
down to 0.2 eV.
The source is like a reservoir of water; the potential barrier
is like a dam; and Vgs controls the height of the dam. When • In other words, Vt is lower in the short
Vgs is large enough, the dam is sufficiently low for the water channel device than the long channel
to flow into the channel and the drain. That defines Vt. device. This explains the Vt roll-off.
 Energy-Band Diagram from Source to Drain
• Vt is lower in the short channel
• L dependence device than the long channel
source/channel long channel device.
barrier
• Drain competes with gate to
Vds take control of the channel!
short channel
log(Ids)
• Vds dependence
long channel
Vds
Vds = 0 Vds = 0

Vds = Vdd Vds = Vdd

short channel Vgs

• When L is small, smaller Vg is needed to reduce the barrier to 0.2V, i.e. Vt

is smaller.
• Vt roll-off is greater for shorter L. Let us understand it more…
 Vt Roll-off – Simple Capacitance Model
Vgs Vds helps Vgs to invert the surface, therefore
One can intuitively C
see that as L Vt  Vt -long - Vds  d
Toxe Coxe Vds Coxe As the channel length is
decreases, Cd reduced, drain to
Cd
increases. n+ W dep
Cd
Xj Vt  Vt -long - (Vds  0.4 )  channel distance is
Coxe reduced Cd increases
 Vt decreases.
P-Sub Due to built-in potential between
channel and N+ drain & source
/
2-D Poisson equation solution shows
that Cd is an exponential function of L. Xj is the drain
junction depth.

• Thus, the drain voltage has a similar effect on the channel potential as the gate voltage. Vgs and Vds, together,
determine the channel potential barrier height.
• When Vds is present, less Vgs is needed to pull the barrier down to 0.2 eV; therefore, Vt is lower by definition.
• The roll-off is an exponential function of L. At a very large L, Vt is equal to Vt-long as expected.
• The roll off is also larger at larger Vds, which can be as large as Vdd.
 Drain-induced barrier lowering
The oxide thickness
Vertical dimensions (Toxe, Wdep, Xj) must has been scaled
be scaled to support the L reduction roughly in proportion
to the gate length.
/

• The concept that the drain can lower the source–channel barrier and reduce Vt is called drain-induced
barrier lowering or DIBL. ld may be called the DIBL characteristic length.

• In order to support the reduction of L at each new technology node, ld must be reduced in proportion to L.
This means that we must reduce Toxe, Wdep, and/or Xj. In reality, all three are reduced at each node to
achieve the desired reduction in ld.

• Reducing Toxe increases the gate control or Coxe. Reducing Xj decreases Cd by reducing the size of the drain
electrode. Reducing Wdep also reduces Cd by introducing a ground plane (the neutral region of the substrate
or the bottom of the depletion region) that tends to electrostatically shield the channel from the drain.
Reducing Gate-Insulator Electrical Thickness and Tunneling Leakage

• Oxide thickness has been reduced over the years

from 300nm to 1.2nm.

• Why reduce oxide thickness?

• Larger Cox to raise Ion (high circuit speed)
• Reduce sub-threshold swing
• Control Vt roll-off

• Thinner is better. However, if the oxide is too thin

• Breakdown due to high field
• Gate leakage current
 How can Tinv be reduced?

• Tinv is also part of Toxe and needs to be minimized. The material parameters that determine Tinv
is the electron or hole effective mass.

• A larger effective mass leads to a thinner Tinv. Unfortunately, a larger effective mass leads to a
lower mobility, too.

• Fortunately, the effective mass is a function of the spatial direction in a crystal.

• The effective mass in the direction normal to the oxide interface determines Tinv , while the
effective mass in the direction of the current flow determines the surface mobility.

• It may be possible to build a transistor with a wafer orientation that offers larger mn and mp
normal to the oxide interface but smaller mn and mp in the direction of the current flow.
 How to Reduce Wdep?
• Wdep can be reduced by increasing Nsub

qN sub 2 sst 2 sst

Vt  V fb  st   V fb  st 
Cox CoxWdep
– If Nsub is increased, Cox has to be increased in order to keep Vt the same.
– Wdep can be reduced in proportion to Tox.

• Or use retrograde doping with very

thin lightly doped surface layer

– Also, less impurity scattering in the

inversion layer  higher mobility
 Shallow Junction and Metal Source/Drain (Xj)

• The shallow junction extension helps to control Vt roll-off.

• Shallow junction and light doping combined lead to undesirable parasitic resistance that reduces the
precious Ion. That is a price to pay for suppressing Vt roll-off and the sub-threshold leakage current.
• Farther away from the channel, a deeper N+ junction is used to minimize the total parasitic resistance.
• The width of the dielectric spacer should be as small as possible to minimize the resistance.
• Theoretically, metal S/D can be used as a very shallow “junction”.
 MOSFET with Metal Source/Drain
To unleash the potentials of
Schottky S/D MOSFET, a low-
Schottky junction is needed
for NFETs and low- for PFET.

• A metal source/drain MOSFET or Schottky source/drain MOSFET

can have very shallow junctions (good for the short-channel effect)
and low series-resistance because the silicide is ten times more
conductive than N+ or P+ Si. The only problem is that the Schottky-
S/D MOSFET would have a lower Id than the regular MOSFET.

• In the on state, channel Ec is pulled down by the gate voltage, but

not at the source/drain edge, where the barrier height is fixed. This
barrier does not exist in a conventional MOSFET, and this can
degrade Id of the metal S/D MOSFET.

• A thin N+ region can be added between the metal and the channel.
This minimizes the effect of the barriers on current flow.
 Punch-through leakage or breakdown

• Once the source-channel barrier is lowered by DIBL, there can be significant drain leakage current,
with the gate being unable to shut it off.

• This leads to punch-through leakage or breakdown between the source and the drain, and loss of
gate control.

• The onset of DIBL is considered to correspond to the drain depletion region expanding and merging
with the source depletion region, and causing punch-through breakdown between source and drain.

• How can we mitigate/control it?

• DIBL is caused by the lowering of the source-junction potential barrier. Hence, the problem can be
mitigated by applying a substrate reverse bias, because that raises the potential barrier at the
source end.
Punch-through leakage
More solutions to this problem:

• The source/drain junctions must be made

sufficiently shallow (i.e., scaled properly) as the
channel lengths are reduced, to prevent DIBL.

• The channel doping must be made sufficiently

high to prevent the drain from being able to
control the source junction. This is achieved by
performing what is known as an anti-punch-
through implant in the channel.

• Alternatively, instead of such an implant

throughout the channel, a localized implant is
done only near the source/drains. These are
known as halo or pocket implants. The higher
doping reduces the source/drain depletion
widths and prevents their interaction.
 MOSFET Scaling and Hot Electron Effects
• When an electron travels from the source to the drain along the channel, it gains kinetic energy at the
expense of electrostatic potential energy in the pinch-off region, and becomes a “hot” electron.

• At the conduction band edge, the electron has potential energy only; as it gains more kinetic energy, it
moves higher up in the conduction band. A few of the electrons can become energetic enough to
overcome the 3.1- eV potential barrier between the Si channel and the gate oxide.

• Some of these injected hot electrons can go through the gate oxide and be collected as gate current,
thereby reducing the input impedance.

• Some electrons can be trapped in the gate oxide as fixed oxide charges. This increases the flat band
voltage, and therefore the VT.

• In addition, these energetic hot carriers can rupture Si–H bonds that exist at the Si-SiO2 interface,
creating fast interface states that degrade MOSFET parameters such as transconductance and
subthreshold slope, with stress.
 Hot Electron Effects

• The linear region transfer

characteristics before and after hot
carrier stress indicate an increase of
VT and decrease of transconductance
(or channel mobility) due to hot
electron damage.

• The hot electron injection into the

gate oxide increases the fixed oxide
charge.

• Also increases fast interface state

densities at the oxide–silicon
interface (indicated by x).

• What is the solution to this problem?

 MOSFET Scaling and Hot Electron Effects
• The solution to this problem is to use what is known as a lightly doped drain (LDD).

• By reducing the doping concentration in the source/drain, the depletion width at the
reverse-biased drain-channel junction is increased and the electric field is reduced.

• Hot carrier effects are less problematic for holes in p-channel MOSFETs than for
electrons in n-channel devices.

• The channel mobility of holes is approximately half that of electrons; hence, for the
same electric field, there are fewer hot holes than hot electrons.

• Also, the barrier for hole injection in the valence band between Si and SiO2 is higher
(5 eV) than for electrons in the conduction band (3.1 eV). Hence, while LDD is
mandatory for n-channel, it is often not used for p-channel devices.