Semiconductors Nanostructures Practical

Part: 2
“Static simulation of a cylindrical p–i–n photodiode”

Due: February 9th, 2021

By:
Hanna Demchenko
Jennifer Izaguirre
Iryna Yakushko
Introduction
This practical was done to understand how the doping profiles are affected at
different thickness and also to understand how to control doping.

2.3 Study of the fabrication process

Q.1 - Have a look at the init.str data with TONYPLOT. What is the doping level in the
substrate and its crystalline properties ?

Crystalline orientation: monocrystalline Silicon orientation - 100, this is shown in

the figure above and described in the deckbuild.

The doping level is around: 16.8 cm​-3​ (n-type) this is shown in the figure above.
Q.2 - Describe in detail the process flow of this photodiode by reading the script in
DECKBUILD and using TONYPLOT to study all the intermediate states of the device
before the end of its fabrication. For more details about keywords and units, have a look to
the ATHENA’s manual, in the statement chapter. The purpose of this part is to justify the
order of the elementary steps and the values of parameters. For instance, we expect that
you explain why 0:6 μm of material oxide (Silicon dioxide ? something else ?) is used for the
first deposit. Using the accurate figures / graphs / cutlines, you can justify whether you can
reduce this thickness or not.

You cannot reduce the thickness too much because it will lead to doping in the silicon substrate.
The following graphs,figures and cutlines will show the steps taken to produce the p-n junction
and also how we concluded that the thickness cannot be reduced.

In step 1, there is a doping layer of phosphorus that was added to the substrate
layer. The cutline shows the active phosphorus in the substrate. You can see this
above in the figure.
In step 2, there was a deposition of SiO2 and a resist. This was labeled the ring
guard fabrication.

In step 3, the resist has been removed with etching.

In step 4, added a gas layer of oxidation on the silicon layer and implanted the
phosphorus layer.
In step 5, the etched oxide layer was the first step then there was a deposit of
another oxide and lastly the photoresist. After all this, etching was done to obtain
the following structure.
In step 6, oxidation has occurred to add the boron layer. After this addition the oxide was
etched.
***

*** In step 6 there are two different oxides that were deposited at different thickness. The
thicker one is added for protection against doping. The thinner one is for the channel
effect in the p-n junction.
In step 7, There was a deposit of Aluminium and photoresist and then the aluminum was
etched.

Lastly, in step 8 there was a deposit of a silicon nitride layer.

Q.3 - Before the two implant steps, there is a deposit of an oxide layer. Do we really need
the same thickness for these two steps ?
We do not need the same thickness for the two steps because boron and phosphorus have
different atom sizes so they would penetrate the oxide layer deeper if the thickness is too low.
There is an expectation that if the thickness is decreased the boron which has a smaller atom size
will penetrate deeper into the silicon substrate. The purpose is to avoid the thickness being so
low that there is doping on the silicon substrate.

Q.4 - Draw the Boron concentration profile at step 6 ? Comment the previous diffuse step
and Draw once again the Boron concentration profile at step 6. Any comment?

When the diffuse step is commented there is no oxidation that has taken place so the boron
penetrates deeper into the silicon substrate.

Q.5 - What is the thickness of the layer deposited by epitaxy ? Why is it different at the end
of the process ?

The original substrate was around 10μm. The thickness of the layer deposited by the epitaxy is
around 0.6 μm because at the end there is a difference from the original, in step 1 being 10μm, to
the final, in step 8 around 10.6 μm. The difference at the end of the process has been attributed to
some loss of the original substrate due to the oxidation.

Q.6 - Why does the bottom n++ layer move in direction of the front surface ?
The n++ layer moves in the direction of the front surface because of diffusion. Also as the
overall thickness of the silicon is decreasing, the distance from the bottom n++ area to the top
edge of silicon decreases.
2.4 Electrical characteristics
Q7: where are the anode and cathode located?

Q8: Draw the electrical DC characteristic I​emitter​ = f(V​emitter​) for with and without light using
an overlay.
Q9: Is it better to use a reverse or a direct polarization of the photodiode for light
detection?

From the picture in Q7 it is easy to see that there is only a difference in the negative
range of the voltage spectrum, while in positive one it is impossible to distinguish one
current from another. This leads us to the conclusion that using reverse polarization is
better for light detection.

Q.10: As the power density D of the optical flux is 0.1 W/cm​2​, calculate the maximum
current I​max​ that the photodiode could return if its conversion efficiency is 1.

Diode active radius r = 5.1 µm (from 2D graphic in TONYPLOT)

D = 0.1 W / cm​2
λ = 650 nm
ղ=1

Following mention formula we can achieve:

ηeλP ηeλDπr2 1×1,6×10−19 ×650×10−9 ×3,14×(5,1)2 ×10−8 ×0,1
I= hc = hc = 6,62×10−34 ×3×10−8
= 42, 79 × 10−9 = 42, 79nA

Q11: Plot the I-V dark and light curves in TONYPLOT. Should we use direct or reverse
polarization?
As it was explained in Q9 reverse polarisation is preferable.

Q12: Use the exported data at the end of the simulation to calculate the efficiency of the
device I​ph​/I​max​ as a function of the applied voltage. What is the best polarization?

In the pictures above there are two different ranges of Voltage applied. First one
represents the relation between efficiency and the whole voltage range available, while
the other shows only negative voltage. As it was proven in Q9 before, negative
polarization is still better for data analysis. Exported data were analyzed via Excel.
there’s no second n++ well on the right top lvl
2.5 Influence of the ring guard.
Q.13 - What is the origin of the dark current ?
It’s a current that occurs even in the absence of light input.
There are three potential origins of the dark current:
● Thermal generation in the depletion zone;
● Thermal generation and diffusion in the bulk;
● Thermal generation due to the surface states​.

Q. 14. In the picture below you can see the band diagrams in the central part of the device
(1) and part of the device without the ring-guard (2).

In order to measure the signal - we want to ‘collect’ the electron that is on the conductive
band. But since the system always tries to minimize the energy - the same will apply to
electrons, and they will move to the right part of our diagram for both (1) and (2). For the
holes, since they have an opposite charge, - they will move to the left.
So, no matter where the electrons and holes are positioned - we can collect them. And
because there’s no light and 0 V - created electrons and holes are all due to the thermal
excitation, but even though we can collect it - it’s not actually what we want, since it is a
background noise.

Here, in the picture you can see the band diagrams in the central part of the device (1)
and under the ring-guard (2).

In the central part (1) it’s exactly the same band diagram as before, but for the band
diagram under the ring guard - it has a local minimum and maximum for the electrons
and holes.
For the conductive band: the electron can go either on the left or on the right, so they
move, but for the holes it’s impossible to minimize their energy, so they stay at the same
place for a long time, and they will recombine with the electron. Basically, the current
contribution in this case is 0.
Q. 15. The picture below is the IV characteristics of the photodiode without the ring guard
at 0V and no light.

If you look at the IV characteristics of the photodiode with the ring guard at 0V and no
light (question 11), there’s no visible difference between them.

Considering our results, we can say that the ring doesn’t change the current. Although in
the paper by Li, Q., Lu, W., Hu, W., Wang, F., Wang, P., Zhang, L., … Chen, X. (2020).
“Enhanced Performance of HgCdTe Midwavelength Infrared Electron Avalanche
Photodetectors With Guard Ring Designs.” ​IEEE Transactions on Electron Devices,​ 1–5.
doi:10.1109/TED.2019.2958105 (​https://doi.org/10.1109/TED.2019.2958105​), it’s
concluded, that the device with the ring guard and correct annealing time should have
effectively reduced dark current while maintaining the bandwidth at a high level.
Maybe in our case it’s due to the fact that we checked it with no light and 0 V, so nothing
to measure, except the thermal excitation.