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  • GCSE CS (2210) / IGCSE CS (0478) P1 NOTES Chapter 1.3: Hardware and Software 1.3.2 Computer Architecture

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    The document summarizes the components of the Von Neumann architecture. It describes the Arithmetic Logic Unit (ALU) that performs arithmetic and logic operations, and the Control Unit (CU) that manages instruction execution. It also discusses the buses that connect components - the address bus carries memory addresses, the control bus carries signals, and the data bus transfers data bidirectionally. The processing of instructions occurs in three stages: fetch, decode, execute. The CPU fetches instructions from memory and stores them in the IAS before decoding and executing. Calculations are performed by the ALU and data is held temporarily in the accumulator.

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    The document summarizes the components of the Von Neumann architecture. It describes the Arithmetic Logic Unit (ALU) that performs arithmetic and logic operations, and the Control Unit (CU) that manages instruction execution. It also discusses the buses that connect components - the address bus carries memory addresses, the control bus carries signals, and the data bus transfers data bidirectionally. The processing of instructions occurs in three stages: fetch, decode, execute. The CPU fetches instructions from memory and stores them in the IAS before decoding and executing. Calculations are performed by the ALU and data is held temporarily in the accumulator.

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    GCSE CS (2210) / IGCSE CS (0478) P1 NOTES Chapter 1.3: Hardware and Software 1.3.2 Computer Architecture

    Uploaded by

    collen
    The document summarizes the components of the Von Neumann architecture. It describes the Arithmetic Logic Unit (ALU) that performs arithmetic and logic operations, and the Control Unit (CU) that manages instruction execution. It also discusses the buses that connect components - the address bus carries memory addresses, the control bus carries signals, and the data bus transfers data bidirectionally. The processing of instructions occurs in three stages: fetch, decode, execute. The CPU fetches instructions from memory and stores them in the IAS before decoding and executing. Calculations are performed by the ALU and data is held temporarily in the accumulator.

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    GCSE CS (2210) / IGCSE CS (0478) P1 NOTES BY AWAB AQIB

    CHAPTER 1.3: HARDWARE AND SOFTWARE


    1.3.2 Computer Architecture

    COMPONENTS OF VONN NEUMANN ARCHITECTURE

    Arithmetic Logic Unit (ALU)


    -The part of a computer processor (CPU) that carries out arithmetic (addition/subtraction)
    -and logic operations (AND, OR, NOT)
    -On the operands in computer instruction

    Control Unit (CU)


    -Fetches each instruction in turn and manages their execution
    -Handles all processor control signals.
    -It directs all input and output flow, fetches code for instructions and directs them
    Bus
    -To connect the internal components of CPU
    -Pathway for transmitting data and instructions
    - Examples: Address Bus, Control Bus, Data Bus
    1. Address Bus:
    -Carries the address of the next item to be fetched
    -Data travels in only one direction (unidirectional)

    2. Control Bus:
    -Carries signals and actions of CPU
    -can be unidirectional or bidirectional

    3. Data Bus:
    -Carries data that is being processed
    -data can travel in both directions (bidirectional)

    Accumulator
    -During calculations, the data is temporarily held in a register called the Accumulator (ACC)

    Register
    -Holds data or instructions temporarily when they are being processed

    Immediate Store Access (IAS)


    - The central processing unit (CPU) fetches the data instructions needed
    - and stores them in the Immediate Access Store (IAS) to wait to be processed

    awabaqibb@gmail.com https://www.youtube.com/c/awabaqib/
    GCSE CS (2210) / IGCSE CS (0478) P1 NOTES BY AWAB AQIB
    CHAPTER 1.3: HARDWARE AND SOFTWARE
    1.3.2 Computer Architecture

    PROCESSING OF AN INSTRUCTION

    Happens in three stages:


    -fetch
    -decode
    -execute

    EXPLANATION OF A VON NEUMANN’s FETCH, DECODE, EXECUTE CYCLE

    1. Central Processing Unit (CPU) fetches the data and instructions needed and stores
    them in the Immediate Access Store (IAS) to wait to be processed.

    2. The Program Counter (PC) holds the address of the next instruction.

    3. This address is sent to the Memory Address Register (MAR) through the Address
    Bus

    4. The data from this address is sent to the Memory Data Register (MDR) which holds
    the current instruction in use, from address in MAR

    5. Instruction is transferred using Data bus

    6. From there, it’s copied onto Current Instruction Register (CIR)

    7. Program Counter (PC) is incremented to point to the next instruction that’s to be


    fetched

    8. Address of the instruction is paced in the Memory Address Register (MAR)

    9. The instruction can then be decoded and executed thus completing the fetch,
    decode, execute cycle

    -Calculations that are carried out on the data are done by the Arithmetic Logic Unit (ALU)
    -During calculations, the data is temporarily held in a register called the Accumulator (ACC)

    awabaqibb@gmail.com https://www.youtube.com/c/awabaqib/
    GCSE CS (2210) / IGCSE CS (0478) P1 NOTES BY AWAB AQIB
    CHAPTER 1.3: HARDWARE AND SOFTWARE
    1.3.2 Computer Architecture

    awabaqibb@gmail.com https://www.youtube.com/c/awabaqib/

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