Sequential Logic

Analysis and Design

of Sequential Circuits
 Registers
❖ We know that one flip-flop can store one-
bit of information. In order to store multiple
bits of information, we require multiple flip-
flops. The group of flip-flops, which are
used to hold (store) the binary data is
known as register.
❖ Registers are a collection of Flip-Flops.
❖ They perform operations like load, clear, shift.
▪ Parallel Load registers
▪ Shift register

2
 1-Parallel load register

• Note the addition of the

asynchronous clear
3
 Parallel Load Registers
❖ The D F-F loads data at every cycle. We
want to control that
❖ We can put an AND gate before the clock
and AND the clock with the Load control.
❖ OK, but not good as there should be NO
gates between the clock and clock input for
sequential circuits.
❖ The solution is to load the new data when
we want and load back the old data when
we want to keep it.
4
If Load = 1
Input data is laded
to the register

If load =0
Register keep its
output unchanged

Four‐bit register with parallel load

5
If Load =0,
R=S=0

6
 2-Shift Registers
❖ If the register is capable of shifting bits either
towards right hand side or towards left hand side
is known as shift register. An ‘N’ bit shift register
contains ‘N’ flip-flops.
❖ Shift is a very common operation
❖ Shift left is same as multiply by 2.
❖ Shift right is same as divide by 2
❖ Ex. 6=0110 shift one bit right will be 0011=3
❖ Ex. 6=0110 shift one bit left will be 1100=12

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2-Shift Registers

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9
Draw a 4-bit shift right register using D flip flops. Show the contents of the
register after three times shift right with serial input (101). Assume the
register initially contains (1100)
solution

Timing
Shift Register
Pulse
Initial
1 1 0 0
Value
After T1 1 1 1 0
After T2 0 1 1 1
After T3 1 0 1 1 10
Serial Transfer
1011 0010

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 Serial Transfer Example
Timing Serial
Shift Register A Shift Register B
Pulse Output
Initial Value 1 0 1 1 0 0 1 0 0
After T1 1 1 0 1 1 0 0 1 1
After T2 1 1 1 0 1 1 0 0 0
After T3 0 1 1 1 0 1 1 0 0
After T4 1 0 1 1 1 0 1 1 1

12